if_vge.c revision 150968
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 150968 2005-10-05 10:09:17Z glebius $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/taskqueue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <machine/bus.h> 109#include <machine/resource.h> 110#include <sys/bus.h> 111#include <sys/rman.h> 112 113#include <dev/mii/mii.h> 114#include <dev/mii/miivar.h> 115 116#include <dev/pci/pcireg.h> 117#include <dev/pci/pcivar.h> 118 119MODULE_DEPEND(vge, pci, 1, 1, 1); 120MODULE_DEPEND(vge, ether, 1, 1, 1); 121MODULE_DEPEND(vge, miibus, 1, 1, 1); 122 123/* "controller miibus0" required. See GENERIC if you get errors here. */ 124#include "miibus_if.h" 125 126#include <dev/vge/if_vgereg.h> 127#include <dev/vge/if_vgevar.h> 128 129#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct vge_type vge_devs[] = { 135 { VIA_VENDORID, VIA_DEVICEID_61XX, 136 "VIA Networking Gigabit Ethernet" }, 137 { 0, 0, NULL } 138}; 139 140static int vge_probe (device_t); 141static int vge_attach (device_t); 142static int vge_detach (device_t); 143 144static int vge_encap (struct vge_softc *, struct mbuf *, int); 145 146static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 147static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 148 bus_size_t, int); 149static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 150 bus_size_t, int); 151static int vge_allocmem (device_t, struct vge_softc *); 152static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 153static int vge_rx_list_init (struct vge_softc *); 154static int vge_tx_list_init (struct vge_softc *); 155#ifdef VGE_FIXUP_RX 156static __inline void vge_fixup_rx 157 (struct mbuf *); 158#endif 159static void vge_rxeof (struct vge_softc *); 160static void vge_txeof (struct vge_softc *); 161static void vge_intr (void *); 162static void vge_tick (void *); 163static void vge_tx_task (void *, int); 164static void vge_start (struct ifnet *); 165static int vge_ioctl (struct ifnet *, u_long, caddr_t); 166static void vge_init (void *); 167static void vge_stop (struct vge_softc *); 168static void vge_watchdog (struct ifnet *); 169static int vge_suspend (device_t); 170static int vge_resume (device_t); 171static void vge_shutdown (device_t); 172static int vge_ifmedia_upd (struct ifnet *); 173static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174 175#ifdef VGE_EEPROM 176static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177#endif 178static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179 180static void vge_miipoll_start (struct vge_softc *); 181static void vge_miipoll_stop (struct vge_softc *); 182static int vge_miibus_readreg (device_t, int, int); 183static int vge_miibus_writereg (device_t, int, int, int); 184static void vge_miibus_statchg (device_t); 185 186static void vge_cam_clear (struct vge_softc *); 187static int vge_cam_set (struct vge_softc *, uint8_t *); 188#if __FreeBSD_version < 502113 189static uint32_t vge_mchash (uint8_t *); 190#endif 191static void vge_setmulti (struct vge_softc *); 192static void vge_reset (struct vge_softc *); 193 194#define VGE_PCI_LOIO 0x10 195#define VGE_PCI_LOMEM 0x14 196 197static device_method_t vge_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, vge_probe), 200 DEVMETHOD(device_attach, vge_attach), 201 DEVMETHOD(device_detach, vge_detach), 202 DEVMETHOD(device_suspend, vge_suspend), 203 DEVMETHOD(device_resume, vge_resume), 204 DEVMETHOD(device_shutdown, vge_shutdown), 205 206 /* bus interface */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 212 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 213 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 214 215 { 0, 0 } 216}; 217 218static driver_t vge_driver = { 219 "vge", 220 vge_methods, 221 sizeof(struct vge_softc) 222}; 223 224static devclass_t vge_devclass; 225 226DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 227DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 228DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 229 230#ifdef VGE_EEPROM 231/* 232 * Read a word of data stored in the EEPROM at address 'addr.' 233 */ 234static void 235vge_eeprom_getword(sc, addr, dest) 236 struct vge_softc *sc; 237 int addr; 238 u_int16_t *dest; 239{ 240 register int i; 241 u_int16_t word = 0; 242 243 /* 244 * Enter EEPROM embedded programming mode. In order to 245 * access the EEPROM at all, we first have to set the 246 * EELOAD bit in the CHIPCFG2 register. 247 */ 248 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 249 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 250 251 /* Select the address of the word we want to read */ 252 CSR_WRITE_1(sc, VGE_EEADDR, addr); 253 254 /* Issue read command */ 255 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 256 257 /* Wait for the done bit to be set. */ 258 for (i = 0; i < VGE_TIMEOUT; i++) { 259 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 260 break; 261 } 262 263 if (i == VGE_TIMEOUT) { 264 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 265 *dest = 0; 266 return; 267 } 268 269 /* Read the result */ 270 word = CSR_READ_2(sc, VGE_EERDDAT); 271 272 /* Turn off EEPROM access mode. */ 273 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 274 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 275 276 *dest = word; 277 278 return; 279} 280#endif 281 282/* 283 * Read a sequence of words from the EEPROM. 284 */ 285static void 286vge_read_eeprom(sc, dest, off, cnt, swap) 287 struct vge_softc *sc; 288 caddr_t dest; 289 int off; 290 int cnt; 291 int swap; 292{ 293 int i; 294#ifdef VGE_EEPROM 295 u_int16_t word = 0, *ptr; 296 297 for (i = 0; i < cnt; i++) { 298 vge_eeprom_getword(sc, off + i, &word); 299 ptr = (u_int16_t *)(dest + (i * 2)); 300 if (swap) 301 *ptr = ntohs(word); 302 else 303 *ptr = word; 304 } 305#else 306 for (i = 0; i < ETHER_ADDR_LEN; i++) 307 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 308#endif 309} 310 311static void 312vge_miipoll_stop(sc) 313 struct vge_softc *sc; 314{ 315 int i; 316 317 CSR_WRITE_1(sc, VGE_MIICMD, 0); 318 319 for (i = 0; i < VGE_TIMEOUT; i++) { 320 DELAY(1); 321 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 322 break; 323 } 324 325 if (i == VGE_TIMEOUT) 326 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 327 328 return; 329} 330 331static void 332vge_miipoll_start(sc) 333 struct vge_softc *sc; 334{ 335 int i; 336 337 /* First, make sure we're idle. */ 338 339 CSR_WRITE_1(sc, VGE_MIICMD, 0); 340 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 341 342 for (i = 0; i < VGE_TIMEOUT; i++) { 343 DELAY(1); 344 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 345 break; 346 } 347 348 if (i == VGE_TIMEOUT) { 349 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 350 return; 351 } 352 353 /* Now enable auto poll mode. */ 354 355 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 356 357 /* And make sure it started. */ 358 359 for (i = 0; i < VGE_TIMEOUT; i++) { 360 DELAY(1); 361 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 362 break; 363 } 364 365 if (i == VGE_TIMEOUT) 366 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 367 368 return; 369} 370 371static int 372vge_miibus_readreg(dev, phy, reg) 373 device_t dev; 374 int phy, reg; 375{ 376 struct vge_softc *sc; 377 int i; 378 u_int16_t rval = 0; 379 380 sc = device_get_softc(dev); 381 382 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 383 return(0); 384 385 VGE_LOCK(sc); 386 vge_miipoll_stop(sc); 387 388 /* Specify the register we want to read. */ 389 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 390 391 /* Issue read command. */ 392 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 393 394 /* Wait for the read command bit to self-clear. */ 395 for (i = 0; i < VGE_TIMEOUT; i++) { 396 DELAY(1); 397 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 398 break; 399 } 400 401 if (i == VGE_TIMEOUT) 402 device_printf(sc->vge_dev, "MII read timed out\n"); 403 else 404 rval = CSR_READ_2(sc, VGE_MIIDATA); 405 406 vge_miipoll_start(sc); 407 VGE_UNLOCK(sc); 408 409 return (rval); 410} 411 412static int 413vge_miibus_writereg(dev, phy, reg, data) 414 device_t dev; 415 int phy, reg, data; 416{ 417 struct vge_softc *sc; 418 int i, rval = 0; 419 420 sc = device_get_softc(dev); 421 422 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 423 return(0); 424 425 VGE_LOCK(sc); 426 vge_miipoll_stop(sc); 427 428 /* Specify the register we want to write. */ 429 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 430 431 /* Specify the data we want to write. */ 432 CSR_WRITE_2(sc, VGE_MIIDATA, data); 433 434 /* Issue write command. */ 435 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 436 437 /* Wait for the write command bit to self-clear. */ 438 for (i = 0; i < VGE_TIMEOUT; i++) { 439 DELAY(1); 440 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 441 break; 442 } 443 444 if (i == VGE_TIMEOUT) { 445 device_printf(sc->vge_dev, "MII write timed out\n"); 446 rval = EIO; 447 } 448 449 vge_miipoll_start(sc); 450 VGE_UNLOCK(sc); 451 452 return (rval); 453} 454 455static void 456vge_cam_clear(sc) 457 struct vge_softc *sc; 458{ 459 int i; 460 461 /* 462 * Turn off all the mask bits. This tells the chip 463 * that none of the entries in the CAM filter are valid. 464 * desired entries will be enabled as we fill the filter in. 465 */ 466 467 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 468 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 469 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 470 for (i = 0; i < 8; i++) 471 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 472 473 /* Clear the VLAN filter too. */ 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 476 for (i = 0; i < 8; i++) 477 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 478 479 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 480 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 481 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 482 483 sc->vge_camidx = 0; 484 485 return; 486} 487 488static int 489vge_cam_set(sc, addr) 490 struct vge_softc *sc; 491 uint8_t *addr; 492{ 493 int i, error = 0; 494 495 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 496 return(ENOSPC); 497 498 /* Select the CAM data page. */ 499 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 500 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 501 502 /* Set the filter entry we want to update and enable writing. */ 503 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 504 505 /* Write the address to the CAM registers */ 506 for (i = 0; i < ETHER_ADDR_LEN; i++) 507 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 508 509 /* Issue a write command. */ 510 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 511 512 /* Wake for it to clear. */ 513 for (i = 0; i < VGE_TIMEOUT; i++) { 514 DELAY(1); 515 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 516 break; 517 } 518 519 if (i == VGE_TIMEOUT) { 520 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 521 error = EIO; 522 goto fail; 523 } 524 525 /* Select the CAM mask page. */ 526 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 527 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 528 529 /* Set the mask bit that enables this filter. */ 530 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 531 1<<(sc->vge_camidx & 7)); 532 533 sc->vge_camidx++; 534 535fail: 536 /* Turn off access to CAM. */ 537 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 538 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 539 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 540 541 return (error); 542} 543 544#if __FreeBSD_version < 502113 545static uint32_t 546vge_mchash(addr) 547 uint8_t *addr; 548{ 549 uint32_t crc, carry; 550 int idx, bit; 551 uint8_t data; 552 553 /* Compute CRC for the address value. */ 554 crc = 0xFFFFFFFF; /* initial value */ 555 556 for (idx = 0; idx < 6; idx++) { 557 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 558 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 559 crc <<= 1; 560 if (carry) 561 crc = (crc ^ 0x04c11db6) | carry; 562 } 563 } 564 565 return(crc); 566} 567#endif 568 569/* 570 * Program the multicast filter. We use the 64-entry CAM filter 571 * for perfect filtering. If there's more than 64 multicast addresses, 572 * we use the hash filter insted. 573 */ 574static void 575vge_setmulti(sc) 576 struct vge_softc *sc; 577{ 578 struct ifnet *ifp; 579 int error = 0/*, h = 0*/; 580 struct ifmultiaddr *ifma; 581 u_int32_t h, hashes[2] = { 0, 0 }; 582 583 ifp = sc->vge_ifp; 584 585 /* First, zot all the multicast entries. */ 586 vge_cam_clear(sc); 587 CSR_WRITE_4(sc, VGE_MAR0, 0); 588 CSR_WRITE_4(sc, VGE_MAR1, 0); 589 590 /* 591 * If the user wants allmulti or promisc mode, enable reception 592 * of all multicast frames. 593 */ 594 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 595 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 596 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 597 return; 598 } 599 600 /* Now program new ones */ 601 IF_ADDR_LOCK(ifp); 602 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 603 if (ifma->ifma_addr->sa_family != AF_LINK) 604 continue; 605 error = vge_cam_set(sc, 606 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 607 if (error) 608 break; 609 } 610 611 /* If there were too many addresses, use the hash filter. */ 612 if (error) { 613 vge_cam_clear(sc); 614 615 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 616 if (ifma->ifma_addr->sa_family != AF_LINK) 617 continue; 618#if __FreeBSD_version < 502113 619 h = vge_mchash(LLADDR((struct sockaddr_dl *) 620 ifma->ifma_addr)) >> 26; 621#else 622 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 623 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 624#endif 625 if (h < 32) 626 hashes[0] |= (1 << h); 627 else 628 hashes[1] |= (1 << (h - 32)); 629 } 630 631 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 632 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 633 } 634 IF_ADDR_UNLOCK(ifp); 635 636 return; 637} 638 639static void 640vge_reset(sc) 641 struct vge_softc *sc; 642{ 643 register int i; 644 645 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 646 647 for (i = 0; i < VGE_TIMEOUT; i++) { 648 DELAY(5); 649 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 650 break; 651 } 652 653 if (i == VGE_TIMEOUT) { 654 device_printf(sc->vge_dev, "soft reset timed out"); 655 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 656 DELAY(2000); 657 } 658 659 DELAY(5000); 660 661 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 662 663 for (i = 0; i < VGE_TIMEOUT; i++) { 664 DELAY(5); 665 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 666 break; 667 } 668 669 if (i == VGE_TIMEOUT) { 670 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 671 return; 672 } 673 674 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 675 676 return; 677} 678 679/* 680 * Probe for a VIA gigabit chip. Check the PCI vendor and device 681 * IDs against our list and return a device name if we find a match. 682 */ 683static int 684vge_probe(dev) 685 device_t dev; 686{ 687 struct vge_type *t; 688 struct vge_softc *sc; 689 690 t = vge_devs; 691 sc = device_get_softc(dev); 692 693 while (t->vge_name != NULL) { 694 if ((pci_get_vendor(dev) == t->vge_vid) && 695 (pci_get_device(dev) == t->vge_did)) { 696 device_set_desc(dev, t->vge_name); 697 return (BUS_PROBE_DEFAULT); 698 } 699 t++; 700 } 701 702 return (ENXIO); 703} 704 705static void 706vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 707 void *arg; 708 bus_dma_segment_t *segs; 709 int nseg; 710 bus_size_t mapsize; 711 int error; 712{ 713 714 struct vge_dmaload_arg *ctx; 715 struct vge_rx_desc *d = NULL; 716 717 if (error) 718 return; 719 720 ctx = arg; 721 722 /* Signal error to caller if there's too many segments */ 723 if (nseg > ctx->vge_maxsegs) { 724 ctx->vge_maxsegs = 0; 725 return; 726 } 727 728 /* 729 * Map the segment array into descriptors. 730 */ 731 732 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 733 734 /* If this descriptor is still owned by the chip, bail. */ 735 736 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 737 device_printf(ctx->sc->vge_dev, 738 "tried to map busy descriptor\n"); 739 ctx->vge_maxsegs = 0; 740 return; 741 } 742 743 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 744 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 745 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 746 d->vge_sts = 0; 747 d->vge_ctl = 0; 748 749 ctx->vge_maxsegs = 1; 750 751 return; 752} 753 754static void 755vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 756 void *arg; 757 bus_dma_segment_t *segs; 758 int nseg; 759 bus_size_t mapsize; 760 int error; 761{ 762 struct vge_dmaload_arg *ctx; 763 struct vge_tx_desc *d = NULL; 764 struct vge_tx_frag *f; 765 int i = 0; 766 767 if (error) 768 return; 769 770 ctx = arg; 771 772 /* Signal error to caller if there's too many segments */ 773 if (nseg > ctx->vge_maxsegs) { 774 ctx->vge_maxsegs = 0; 775 return; 776 } 777 778 /* Map the segment array into descriptors. */ 779 780 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 781 782 /* If this descriptor is still owned by the chip, bail. */ 783 784 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 785 ctx->vge_maxsegs = 0; 786 return; 787 } 788 789 for (i = 0; i < nseg; i++) { 790 f = &d->vge_frag[i]; 791 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 792 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 793 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 794 } 795 796 /* Argh. This chip does not autopad short frames */ 797 798 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 799 f = &d->vge_frag[i]; 800 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 801 ctx->vge_m0->m_pkthdr.len)); 802 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 803 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 804 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 805 i++; 806 } 807 808 /* 809 * When telling the chip how many segments there are, we 810 * must use nsegs + 1 instead of just nsegs. Darned if I 811 * know why. 812 */ 813 i++; 814 815 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 816 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 817 818 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 819 d->vge_ctl |= VGE_TDCTL_JUMBO; 820 821 ctx->vge_maxsegs = nseg; 822 823 return; 824} 825 826/* 827 * Map a single buffer address. 828 */ 829 830static void 831vge_dma_map_addr(arg, segs, nseg, error) 832 void *arg; 833 bus_dma_segment_t *segs; 834 int nseg; 835 int error; 836{ 837 bus_addr_t *addr; 838 839 if (error) 840 return; 841 842 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 843 addr = arg; 844 *addr = segs->ds_addr; 845 846 return; 847} 848 849static int 850vge_allocmem(dev, sc) 851 device_t dev; 852 struct vge_softc *sc; 853{ 854 int error; 855 int nseg; 856 int i; 857 858 /* 859 * Allocate map for RX mbufs. 860 */ 861 nseg = 32; 862 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 863 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 864 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 865 NULL, NULL, &sc->vge_ldata.vge_mtag); 866 if (error) { 867 device_printf(dev, "could not allocate dma tag\n"); 868 return (ENOMEM); 869 } 870 871 /* 872 * Allocate map for TX descriptor list. 873 */ 874 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 875 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 876 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 877 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 878 if (error) { 879 device_printf(dev, "could not allocate dma tag\n"); 880 return (ENOMEM); 881 } 882 883 /* Allocate DMA'able memory for the TX ring */ 884 885 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 886 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 887 &sc->vge_ldata.vge_tx_list_map); 888 if (error) 889 return (ENOMEM); 890 891 /* Load the map for the TX ring. */ 892 893 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 894 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 895 VGE_TX_LIST_SZ, vge_dma_map_addr, 896 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 897 898 /* Create DMA maps for TX buffers */ 899 900 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 901 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 902 &sc->vge_ldata.vge_tx_dmamap[i]); 903 if (error) { 904 device_printf(dev, "can't create DMA map for TX\n"); 905 return (ENOMEM); 906 } 907 } 908 909 /* 910 * Allocate map for RX descriptor list. 911 */ 912 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 913 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 914 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 915 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 916 if (error) { 917 device_printf(dev, "could not allocate dma tag\n"); 918 return (ENOMEM); 919 } 920 921 /* Allocate DMA'able memory for the RX ring */ 922 923 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 924 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 925 &sc->vge_ldata.vge_rx_list_map); 926 if (error) 927 return (ENOMEM); 928 929 /* Load the map for the RX ring. */ 930 931 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 932 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 933 VGE_TX_LIST_SZ, vge_dma_map_addr, 934 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 935 936 /* Create DMA maps for RX buffers */ 937 938 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 939 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 940 &sc->vge_ldata.vge_rx_dmamap[i]); 941 if (error) { 942 device_printf(dev, "can't create DMA map for RX\n"); 943 return (ENOMEM); 944 } 945 } 946 947 return (0); 948} 949 950/* 951 * Attach the interface. Allocate softc structures, do ifmedia 952 * setup and ethernet/BPF attach. 953 */ 954static int 955vge_attach(dev) 956 device_t dev; 957{ 958 u_char eaddr[ETHER_ADDR_LEN]; 959 struct vge_softc *sc; 960 struct ifnet *ifp; 961 int unit, error = 0, rid; 962 963 sc = device_get_softc(dev); 964 unit = device_get_unit(dev); 965 sc->vge_dev = dev; 966 967 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 968 MTX_DEF | MTX_RECURSE); 969 /* 970 * Map control/status registers. 971 */ 972 pci_enable_busmaster(dev); 973 974 rid = VGE_PCI_LOMEM; 975 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 976 0, ~0, 1, RF_ACTIVE); 977 978 if (sc->vge_res == NULL) { 979 printf ("vge%d: couldn't map ports/memory\n", unit); 980 error = ENXIO; 981 goto fail; 982 } 983 984 sc->vge_btag = rman_get_bustag(sc->vge_res); 985 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 986 987 /* Allocate interrupt */ 988 rid = 0; 989 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 990 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 991 992 if (sc->vge_irq == NULL) { 993 printf("vge%d: couldn't map interrupt\n", unit); 994 error = ENXIO; 995 goto fail; 996 } 997 998 /* Reset the adapter. */ 999 vge_reset(sc); 1000 1001 /* 1002 * Get station address from the EEPROM. 1003 */ 1004 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1005 1006 sc->vge_unit = unit; 1007 1008#if __FreeBSD_version < 502113 1009 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1010#endif 1011 1012 /* 1013 * Allocate the parent bus DMA tag appropriate for PCI. 1014 */ 1015#define VGE_NSEG_NEW 32 1016 error = bus_dma_tag_create(NULL, /* parent */ 1017 1, 0, /* alignment, boundary */ 1018 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1019 BUS_SPACE_MAXADDR, /* highaddr */ 1020 NULL, NULL, /* filter, filterarg */ 1021 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1022 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1023 BUS_DMA_ALLOCNOW, /* flags */ 1024 NULL, NULL, /* lockfunc, lockarg */ 1025 &sc->vge_parent_tag); 1026 if (error) 1027 goto fail; 1028 1029 error = vge_allocmem(dev, sc); 1030 1031 if (error) 1032 goto fail; 1033 1034 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1035 if (ifp == NULL) { 1036 printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1037 error = ENOSPC; 1038 goto fail; 1039 } 1040 1041 /* Do MII setup */ 1042 if (mii_phy_probe(dev, &sc->vge_miibus, 1043 vge_ifmedia_upd, vge_ifmedia_sts)) { 1044 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1045 error = ENXIO; 1046 goto fail; 1047 } 1048 1049 ifp->if_softc = sc; 1050 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1051 ifp->if_mtu = ETHERMTU; 1052 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1053 ifp->if_ioctl = vge_ioctl; 1054 ifp->if_capabilities = IFCAP_VLAN_MTU; 1055 ifp->if_start = vge_start; 1056 ifp->if_hwassist = VGE_CSUM_FEATURES; 1057 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1058 ifp->if_capenable = ifp->if_capabilities; 1059#ifdef DEVICE_POLLING 1060 ifp->if_capabilities |= IFCAP_POLLING; 1061#endif 1062 ifp->if_watchdog = vge_watchdog; 1063 ifp->if_init = vge_init; 1064 ifp->if_baudrate = 1000000000; 1065 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1066 1067 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1068 1069 /* 1070 * Call MI attach routine. 1071 */ 1072 ether_ifattach(ifp, eaddr); 1073 1074 /* Hook interrupt last to avoid having to lock softc */ 1075 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1076 vge_intr, sc, &sc->vge_intrhand); 1077 1078 if (error) { 1079 printf("vge%d: couldn't set up irq\n", unit); 1080 ether_ifdetach(ifp); 1081 goto fail; 1082 } 1083 1084fail: 1085 if (error) 1086 vge_detach(dev); 1087 1088 return (error); 1089} 1090 1091/* 1092 * Shutdown hardware and free up resources. This can be called any 1093 * time after the mutex has been initialized. It is called in both 1094 * the error case in attach and the normal detach case so it needs 1095 * to be careful about only freeing resources that have actually been 1096 * allocated. 1097 */ 1098static int 1099vge_detach(dev) 1100 device_t dev; 1101{ 1102 struct vge_softc *sc; 1103 struct ifnet *ifp; 1104 int i; 1105 1106 sc = device_get_softc(dev); 1107 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1108 ifp = sc->vge_ifp; 1109 1110#ifdef DEVICE_POLLING 1111 if (ifp->if_capenable & IFCAP_POLLING) 1112 ether_poll_deregister(ifp); 1113#endif 1114 1115 /* These should only be active if attach succeeded */ 1116 if (device_is_attached(dev)) { 1117 vge_stop(sc); 1118 /* 1119 * Force off the IFF_UP flag here, in case someone 1120 * still had a BPF descriptor attached to this 1121 * interface. If they do, ether_ifattach() will cause 1122 * the BPF code to try and clear the promisc mode 1123 * flag, which will bubble down to vge_ioctl(), 1124 * which will try to call vge_init() again. This will 1125 * turn the NIC back on and restart the MII ticker, 1126 * which will panic the system when the kernel tries 1127 * to invoke the vge_tick() function that isn't there 1128 * anymore. 1129 */ 1130 ifp->if_flags &= ~IFF_UP; 1131 ether_ifdetach(ifp); 1132 } 1133 if (sc->vge_miibus) 1134 device_delete_child(dev, sc->vge_miibus); 1135 bus_generic_detach(dev); 1136 1137 if (sc->vge_intrhand) 1138 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1139 if (sc->vge_irq) 1140 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1141 if (sc->vge_res) 1142 bus_release_resource(dev, SYS_RES_MEMORY, 1143 VGE_PCI_LOMEM, sc->vge_res); 1144 if (ifp) 1145 if_free(ifp); 1146 1147 /* Unload and free the RX DMA ring memory and map */ 1148 1149 if (sc->vge_ldata.vge_rx_list_tag) { 1150 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1151 sc->vge_ldata.vge_rx_list_map); 1152 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1153 sc->vge_ldata.vge_rx_list, 1154 sc->vge_ldata.vge_rx_list_map); 1155 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1156 } 1157 1158 /* Unload and free the TX DMA ring memory and map */ 1159 1160 if (sc->vge_ldata.vge_tx_list_tag) { 1161 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1162 sc->vge_ldata.vge_tx_list_map); 1163 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1164 sc->vge_ldata.vge_tx_list, 1165 sc->vge_ldata.vge_tx_list_map); 1166 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1167 } 1168 1169 /* Destroy all the RX and TX buffer maps */ 1170 1171 if (sc->vge_ldata.vge_mtag) { 1172 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1173 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1174 sc->vge_ldata.vge_tx_dmamap[i]); 1175 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1176 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1177 sc->vge_ldata.vge_rx_dmamap[i]); 1178 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1179 } 1180 1181 if (sc->vge_parent_tag) 1182 bus_dma_tag_destroy(sc->vge_parent_tag); 1183 1184 mtx_destroy(&sc->vge_mtx); 1185 1186 return (0); 1187} 1188 1189static int 1190vge_newbuf(sc, idx, m) 1191 struct vge_softc *sc; 1192 int idx; 1193 struct mbuf *m; 1194{ 1195 struct vge_dmaload_arg arg; 1196 struct mbuf *n = NULL; 1197 int i, error; 1198 1199 if (m == NULL) { 1200 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1201 if (n == NULL) 1202 return (ENOBUFS); 1203 m = n; 1204 } else 1205 m->m_data = m->m_ext.ext_buf; 1206 1207 1208#ifdef VGE_FIXUP_RX 1209 /* 1210 * This is part of an evil trick to deal with non-x86 platforms. 1211 * The VIA chip requires RX buffers to be aligned on 32-bit 1212 * boundaries, but that will hose non-x86 machines. To get around 1213 * this, we leave some empty space at the start of each buffer 1214 * and for non-x86 hosts, we copy the buffer back two bytes 1215 * to achieve word alignment. This is slightly more efficient 1216 * than allocating a new buffer, copying the contents, and 1217 * discarding the old buffer. 1218 */ 1219 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1220 m_adj(m, VGE_ETHER_ALIGN); 1221#else 1222 m->m_len = m->m_pkthdr.len = MCLBYTES; 1223#endif 1224 1225 arg.sc = sc; 1226 arg.vge_idx = idx; 1227 arg.vge_maxsegs = 1; 1228 arg.vge_flags = 0; 1229 1230 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1231 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1232 &arg, BUS_DMA_NOWAIT); 1233 if (error || arg.vge_maxsegs != 1) { 1234 if (n != NULL) 1235 m_freem(n); 1236 return (ENOMEM); 1237 } 1238 1239 /* 1240 * Note: the manual fails to document the fact that for 1241 * proper opration, the driver needs to replentish the RX 1242 * DMA ring 4 descriptors at a time (rather than one at a 1243 * time, like most chips). We can allocate the new buffers 1244 * but we should not set the OWN bits until we're ready 1245 * to hand back 4 of them in one shot. 1246 */ 1247 1248#define VGE_RXCHUNK 4 1249 sc->vge_rx_consumed++; 1250 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1251 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1252 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1253 htole32(VGE_RDSTS_OWN); 1254 sc->vge_rx_consumed = 0; 1255 } 1256 1257 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1258 1259 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1260 sc->vge_ldata.vge_rx_dmamap[idx], 1261 BUS_DMASYNC_PREREAD); 1262 1263 return (0); 1264} 1265 1266static int 1267vge_tx_list_init(sc) 1268 struct vge_softc *sc; 1269{ 1270 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1271 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1272 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1273 1274 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1275 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1276 sc->vge_ldata.vge_tx_prodidx = 0; 1277 sc->vge_ldata.vge_tx_considx = 0; 1278 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1279 1280 return (0); 1281} 1282 1283static int 1284vge_rx_list_init(sc) 1285 struct vge_softc *sc; 1286{ 1287 int i; 1288 1289 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1290 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1291 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1292 1293 sc->vge_rx_consumed = 0; 1294 1295 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1296 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1297 return (ENOBUFS); 1298 } 1299 1300 /* Flush the RX descriptors */ 1301 1302 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1303 sc->vge_ldata.vge_rx_list_map, 1304 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1305 1306 sc->vge_ldata.vge_rx_prodidx = 0; 1307 sc->vge_rx_consumed = 0; 1308 sc->vge_head = sc->vge_tail = NULL; 1309 1310 return (0); 1311} 1312 1313#ifdef VGE_FIXUP_RX 1314static __inline void 1315vge_fixup_rx(m) 1316 struct mbuf *m; 1317{ 1318 int i; 1319 uint16_t *src, *dst; 1320 1321 src = mtod(m, uint16_t *); 1322 dst = src - 1; 1323 1324 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1325 *dst++ = *src++; 1326 1327 m->m_data -= ETHER_ALIGN; 1328 1329 return; 1330} 1331#endif 1332 1333/* 1334 * RX handler. We support the reception of jumbo frames that have 1335 * been fragmented across multiple 2K mbuf cluster buffers. 1336 */ 1337static void 1338vge_rxeof(sc) 1339 struct vge_softc *sc; 1340{ 1341 struct mbuf *m; 1342 struct ifnet *ifp; 1343 int i, total_len; 1344 int lim = 0; 1345 struct vge_rx_desc *cur_rx; 1346 u_int32_t rxstat, rxctl; 1347 1348 VGE_LOCK_ASSERT(sc); 1349 ifp = sc->vge_ifp; 1350 i = sc->vge_ldata.vge_rx_prodidx; 1351 1352 /* Invalidate the descriptor memory */ 1353 1354 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1355 sc->vge_ldata.vge_rx_list_map, 1356 BUS_DMASYNC_POSTREAD); 1357 1358 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1359 1360#ifdef DEVICE_POLLING 1361 if (ifp->if_capenable & IFCAP_POLLING) { 1362 if (sc->rxcycles <= 0) 1363 break; 1364 sc->rxcycles--; 1365 } 1366#endif 1367 1368 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1369 m = sc->vge_ldata.vge_rx_mbuf[i]; 1370 total_len = VGE_RXBYTES(cur_rx); 1371 rxstat = le32toh(cur_rx->vge_sts); 1372 rxctl = le32toh(cur_rx->vge_ctl); 1373 1374 /* Invalidate the RX mbuf and unload its map */ 1375 1376 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1377 sc->vge_ldata.vge_rx_dmamap[i], 1378 BUS_DMASYNC_POSTWRITE); 1379 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1380 sc->vge_ldata.vge_rx_dmamap[i]); 1381 1382 /* 1383 * If the 'start of frame' bit is set, this indicates 1384 * either the first fragment in a multi-fragment receive, 1385 * or an intermediate fragment. Either way, we want to 1386 * accumulate the buffers. 1387 */ 1388 if (rxstat & VGE_RXPKT_SOF) { 1389 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1390 if (sc->vge_head == NULL) 1391 sc->vge_head = sc->vge_tail = m; 1392 else { 1393 m->m_flags &= ~M_PKTHDR; 1394 sc->vge_tail->m_next = m; 1395 sc->vge_tail = m; 1396 } 1397 vge_newbuf(sc, i, NULL); 1398 VGE_RX_DESC_INC(i); 1399 continue; 1400 } 1401 1402 /* 1403 * Bad/error frames will have the RXOK bit cleared. 1404 * However, there's one error case we want to allow: 1405 * if a VLAN tagged frame arrives and the chip can't 1406 * match it against the CAM filter, it considers this 1407 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1408 * We don't want to drop the frame though: our VLAN 1409 * filtering is done in software. 1410 */ 1411 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1412 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1413 ifp->if_ierrors++; 1414 /* 1415 * If this is part of a multi-fragment packet, 1416 * discard all the pieces. 1417 */ 1418 if (sc->vge_head != NULL) { 1419 m_freem(sc->vge_head); 1420 sc->vge_head = sc->vge_tail = NULL; 1421 } 1422 vge_newbuf(sc, i, m); 1423 VGE_RX_DESC_INC(i); 1424 continue; 1425 } 1426 1427 /* 1428 * If allocating a replacement mbuf fails, 1429 * reload the current one. 1430 */ 1431 1432 if (vge_newbuf(sc, i, NULL)) { 1433 ifp->if_ierrors++; 1434 if (sc->vge_head != NULL) { 1435 m_freem(sc->vge_head); 1436 sc->vge_head = sc->vge_tail = NULL; 1437 } 1438 vge_newbuf(sc, i, m); 1439 VGE_RX_DESC_INC(i); 1440 continue; 1441 } 1442 1443 VGE_RX_DESC_INC(i); 1444 1445 if (sc->vge_head != NULL) { 1446 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1447 /* 1448 * Special case: if there's 4 bytes or less 1449 * in this buffer, the mbuf can be discarded: 1450 * the last 4 bytes is the CRC, which we don't 1451 * care about anyway. 1452 */ 1453 if (m->m_len <= ETHER_CRC_LEN) { 1454 sc->vge_tail->m_len -= 1455 (ETHER_CRC_LEN - m->m_len); 1456 m_freem(m); 1457 } else { 1458 m->m_len -= ETHER_CRC_LEN; 1459 m->m_flags &= ~M_PKTHDR; 1460 sc->vge_tail->m_next = m; 1461 } 1462 m = sc->vge_head; 1463 sc->vge_head = sc->vge_tail = NULL; 1464 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1465 } else 1466 m->m_pkthdr.len = m->m_len = 1467 (total_len - ETHER_CRC_LEN); 1468 1469#ifdef VGE_FIXUP_RX 1470 vge_fixup_rx(m); 1471#endif 1472 ifp->if_ipackets++; 1473 m->m_pkthdr.rcvif = ifp; 1474 1475 /* Do RX checksumming if enabled */ 1476 if (ifp->if_capenable & IFCAP_RXCSUM) { 1477 1478 /* Check IP header checksum */ 1479 if (rxctl & VGE_RDCTL_IPPKT) 1480 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1481 if (rxctl & VGE_RDCTL_IPCSUMOK) 1482 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1483 1484 /* Check TCP/UDP checksum */ 1485 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1486 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1487 m->m_pkthdr.csum_flags |= 1488 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1489 m->m_pkthdr.csum_data = 0xffff; 1490 } 1491 } 1492 1493 if (rxstat & VGE_RDSTS_VTAG) 1494 VLAN_INPUT_TAG(ifp, m, 1495 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1496 1497 VGE_UNLOCK(sc); 1498 (*ifp->if_input)(ifp, m); 1499 VGE_LOCK(sc); 1500 1501 lim++; 1502 if (lim == VGE_RX_DESC_CNT) 1503 break; 1504 1505 } 1506 1507 /* Flush the RX DMA ring */ 1508 1509 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1510 sc->vge_ldata.vge_rx_list_map, 1511 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1512 1513 sc->vge_ldata.vge_rx_prodidx = i; 1514 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1515 1516 1517 return; 1518} 1519 1520static void 1521vge_txeof(sc) 1522 struct vge_softc *sc; 1523{ 1524 struct ifnet *ifp; 1525 u_int32_t txstat; 1526 int idx; 1527 1528 ifp = sc->vge_ifp; 1529 idx = sc->vge_ldata.vge_tx_considx; 1530 1531 /* Invalidate the TX descriptor list */ 1532 1533 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1534 sc->vge_ldata.vge_tx_list_map, 1535 BUS_DMASYNC_POSTREAD); 1536 1537 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1538 1539 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1540 if (txstat & VGE_TDSTS_OWN) 1541 break; 1542 1543 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1544 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1545 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1546 sc->vge_ldata.vge_tx_dmamap[idx]); 1547 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1548 ifp->if_collisions++; 1549 if (txstat & VGE_TDSTS_TXERR) 1550 ifp->if_oerrors++; 1551 else 1552 ifp->if_opackets++; 1553 1554 sc->vge_ldata.vge_tx_free++; 1555 VGE_TX_DESC_INC(idx); 1556 } 1557 1558 /* No changes made to the TX ring, so no flush needed */ 1559 1560 if (idx != sc->vge_ldata.vge_tx_considx) { 1561 sc->vge_ldata.vge_tx_considx = idx; 1562 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1563 ifp->if_timer = 0; 1564 } 1565 1566 /* 1567 * If not all descriptors have been released reaped yet, 1568 * reload the timer so that we will eventually get another 1569 * interrupt that will cause us to re-enter this routine. 1570 * This is done in case the transmitter has gone idle. 1571 */ 1572 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1573 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1574 } 1575 1576 return; 1577} 1578 1579static void 1580vge_tick(xsc) 1581 void *xsc; 1582{ 1583 struct vge_softc *sc; 1584 struct ifnet *ifp; 1585 struct mii_data *mii; 1586 1587 sc = xsc; 1588 ifp = sc->vge_ifp; 1589 VGE_LOCK(sc); 1590 mii = device_get_softc(sc->vge_miibus); 1591 1592 mii_tick(mii); 1593 if (sc->vge_link) { 1594 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1595 sc->vge_link = 0; 1596 if_link_state_change(sc->vge_ifp, 1597 LINK_STATE_DOWN); 1598 } 1599 } else { 1600 if (mii->mii_media_status & IFM_ACTIVE && 1601 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1602 sc->vge_link = 1; 1603 if_link_state_change(sc->vge_ifp, 1604 LINK_STATE_UP); 1605#if __FreeBSD_version < 502114 1606 if (ifp->if_snd.ifq_head != NULL) 1607#else 1608 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1609#endif 1610 taskqueue_enqueue(taskqueue_swi, 1611 &sc->vge_txtask); 1612 } 1613 } 1614 1615 VGE_UNLOCK(sc); 1616 1617 return; 1618} 1619 1620#ifdef DEVICE_POLLING 1621static void 1622vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1623{ 1624 struct vge_softc *sc = ifp->if_softc; 1625 1626 VGE_LOCK(sc); 1627 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1628 goto done; 1629 1630 sc->rxcycles = count; 1631 vge_rxeof(sc); 1632 vge_txeof(sc); 1633 1634#if __FreeBSD_version < 502114 1635 if (ifp->if_snd.ifq_head != NULL) 1636#else 1637 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1638#endif 1639 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1640 1641 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1642 u_int32_t status; 1643 status = CSR_READ_4(sc, VGE_ISR); 1644 if (status == 0xFFFFFFFF) 1645 goto done; 1646 if (status) 1647 CSR_WRITE_4(sc, VGE_ISR, status); 1648 1649 /* 1650 * XXX check behaviour on receiver stalls. 1651 */ 1652 1653 if (status & VGE_ISR_TXDMA_STALL || 1654 status & VGE_ISR_RXDMA_STALL) 1655 vge_init(sc); 1656 1657 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1658 vge_rxeof(sc); 1659 ifp->if_ierrors++; 1660 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1661 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1662 } 1663 } 1664done: 1665 VGE_UNLOCK(sc); 1666} 1667#endif /* DEVICE_POLLING */ 1668 1669static void 1670vge_intr(arg) 1671 void *arg; 1672{ 1673 struct vge_softc *sc; 1674 struct ifnet *ifp; 1675 u_int32_t status; 1676 1677 sc = arg; 1678 1679 if (sc->suspended) { 1680 return; 1681 } 1682 1683 VGE_LOCK(sc); 1684 ifp = sc->vge_ifp; 1685 1686 if (!(ifp->if_flags & IFF_UP)) { 1687 VGE_UNLOCK(sc); 1688 return; 1689 } 1690 1691#ifdef DEVICE_POLLING 1692 if (ifp->if_capenable & IFCAP_POLLING) { 1693 VGE_UNLOCK(sc); 1694 return; 1695 } 1696#endif 1697 1698 /* Disable interrupts */ 1699 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1700 1701 for (;;) { 1702 1703 status = CSR_READ_4(sc, VGE_ISR); 1704 /* If the card has gone away the read returns 0xffff. */ 1705 if (status == 0xFFFFFFFF) 1706 break; 1707 1708 if (status) 1709 CSR_WRITE_4(sc, VGE_ISR, status); 1710 1711 if ((status & VGE_INTRS) == 0) 1712 break; 1713 1714 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1715 vge_rxeof(sc); 1716 1717 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1718 vge_rxeof(sc); 1719 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1720 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1721 } 1722 1723 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1724 vge_txeof(sc); 1725 1726 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1727 vge_init(sc); 1728 1729 if (status & VGE_ISR_LINKSTS) 1730 vge_tick(sc); 1731 } 1732 1733 /* Re-enable interrupts */ 1734 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1735 1736 VGE_UNLOCK(sc); 1737 1738#if __FreeBSD_version < 502114 1739 if (ifp->if_snd.ifq_head != NULL) 1740#else 1741 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1742#endif 1743 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1744 1745 return; 1746} 1747 1748static int 1749vge_encap(sc, m_head, idx) 1750 struct vge_softc *sc; 1751 struct mbuf *m_head; 1752 int idx; 1753{ 1754 struct mbuf *m_new = NULL; 1755 struct vge_dmaload_arg arg; 1756 bus_dmamap_t map; 1757 int error; 1758 struct m_tag *mtag; 1759 1760 if (sc->vge_ldata.vge_tx_free <= 2) 1761 return (EFBIG); 1762 1763 arg.vge_flags = 0; 1764 1765 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1766 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1767 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1768 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1769 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1770 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1771 1772 arg.sc = sc; 1773 arg.vge_idx = idx; 1774 arg.vge_m0 = m_head; 1775 arg.vge_maxsegs = VGE_TX_FRAGS; 1776 1777 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1778 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1779 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1780 1781 if (error && error != EFBIG) { 1782 printf("vge%d: can't map mbuf (error %d)\n", 1783 sc->vge_unit, error); 1784 return (ENOBUFS); 1785 } 1786 1787 /* Too many segments to map, coalesce into a single mbuf */ 1788 1789 if (error || arg.vge_maxsegs == 0) { 1790 m_new = m_defrag(m_head, M_DONTWAIT); 1791 if (m_new == NULL) 1792 return (1); 1793 else 1794 m_head = m_new; 1795 1796 arg.sc = sc; 1797 arg.vge_m0 = m_head; 1798 arg.vge_idx = idx; 1799 arg.vge_maxsegs = 1; 1800 1801 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1802 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1803 if (error) { 1804 printf("vge%d: can't map mbuf (error %d)\n", 1805 sc->vge_unit, error); 1806 return (EFBIG); 1807 } 1808 } 1809 1810 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1811 sc->vge_ldata.vge_tx_free--; 1812 1813 /* 1814 * Set up hardware VLAN tagging. 1815 */ 1816 1817 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head); 1818 if (mtag != NULL) 1819 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1820 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1821 1822 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1823 1824 return (0); 1825} 1826 1827static void 1828vge_tx_task(arg, npending) 1829 void *arg; 1830 int npending; 1831{ 1832 struct ifnet *ifp; 1833 1834 ifp = arg; 1835 vge_start(ifp); 1836 1837 return; 1838} 1839 1840/* 1841 * Main transmit routine. 1842 */ 1843 1844static void 1845vge_start(ifp) 1846 struct ifnet *ifp; 1847{ 1848 struct vge_softc *sc; 1849 struct mbuf *m_head = NULL; 1850 int idx, pidx = 0; 1851 1852 sc = ifp->if_softc; 1853 VGE_LOCK(sc); 1854 1855 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1856 VGE_UNLOCK(sc); 1857 return; 1858 } 1859 1860#if __FreeBSD_version < 502114 1861 if (ifp->if_snd.ifq_head == NULL) { 1862#else 1863 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1864#endif 1865 VGE_UNLOCK(sc); 1866 return; 1867 } 1868 1869 idx = sc->vge_ldata.vge_tx_prodidx; 1870 1871 pidx = idx - 1; 1872 if (pidx < 0) 1873 pidx = VGE_TX_DESC_CNT - 1; 1874 1875 1876 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1877#if __FreeBSD_version < 502114 1878 IF_DEQUEUE(&ifp->if_snd, m_head); 1879#else 1880 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1881#endif 1882 if (m_head == NULL) 1883 break; 1884 1885 if (vge_encap(sc, m_head, idx)) { 1886#if __FreeBSD_version >= 502114 1887 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1888#else 1889 IF_PREPEND(&ifp->if_snd, m_head); 1890#endif 1891 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1892 break; 1893 } 1894 1895 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1896 htole16(VGE_TXDESC_Q); 1897 1898 pidx = idx; 1899 VGE_TX_DESC_INC(idx); 1900 1901 /* 1902 * If there's a BPF listener, bounce a copy of this frame 1903 * to him. 1904 */ 1905 BPF_MTAP(ifp, m_head); 1906 } 1907 1908 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1909 VGE_UNLOCK(sc); 1910 return; 1911 } 1912 1913 /* Flush the TX descriptors */ 1914 1915 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1916 sc->vge_ldata.vge_tx_list_map, 1917 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1918 1919 /* Issue a transmit command. */ 1920 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1921 1922 sc->vge_ldata.vge_tx_prodidx = idx; 1923 1924 /* 1925 * Use the countdown timer for interrupt moderation. 1926 * 'TX done' interrupts are disabled. Instead, we reset the 1927 * countdown timer, which will begin counting until it hits 1928 * the value in the SSTIMER register, and then trigger an 1929 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1930 * the timer count is reloaded. Only when the transmitter 1931 * is idle will the timer hit 0 and an interrupt fire. 1932 */ 1933 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1934 1935 VGE_UNLOCK(sc); 1936 1937 /* 1938 * Set a timeout in case the chip goes out to lunch. 1939 */ 1940 ifp->if_timer = 5; 1941 1942 return; 1943} 1944 1945static void 1946vge_init(xsc) 1947 void *xsc; 1948{ 1949 struct vge_softc *sc = xsc; 1950 struct ifnet *ifp = sc->vge_ifp; 1951 struct mii_data *mii; 1952 int i; 1953 1954 VGE_LOCK(sc); 1955 mii = device_get_softc(sc->vge_miibus); 1956 1957 /* 1958 * Cancel pending I/O and free all RX/TX buffers. 1959 */ 1960 vge_stop(sc); 1961 vge_reset(sc); 1962 1963 /* 1964 * Initialize the RX and TX descriptors and mbufs. 1965 */ 1966 1967 vge_rx_list_init(sc); 1968 vge_tx_list_init(sc); 1969 1970 /* Set our station address */ 1971 for (i = 0; i < ETHER_ADDR_LEN; i++) 1972 CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]); 1973 1974 /* 1975 * Set receive FIFO threshold. Also allow transmission and 1976 * reception of VLAN tagged frames. 1977 */ 1978 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1979 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1980 1981 /* Set DMA burst length */ 1982 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1983 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1984 1985 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1986 1987 /* Set collision backoff algorithm */ 1988 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1989 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1990 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1991 1992 /* Disable LPSEL field in priority resolution */ 1993 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1994 1995 /* 1996 * Load the addresses of the DMA queues into the chip. 1997 * Note that we only use one transmit queue. 1998 */ 1999 2000 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2001 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2002 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2003 2004 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2005 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2006 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2007 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2008 2009 /* Enable and wake up the RX descriptor queue */ 2010 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2011 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2012 2013 /* Enable the TX descriptor queue */ 2014 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2015 2016 /* Set up the receive filter -- allow large frames for VLANs. */ 2017 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2018 2019 /* If we want promiscuous mode, set the allframes bit. */ 2020 if (ifp->if_flags & IFF_PROMISC) { 2021 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2022 } 2023 2024 /* Set capture broadcast bit to capture broadcast frames. */ 2025 if (ifp->if_flags & IFF_BROADCAST) { 2026 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2027 } 2028 2029 /* Set multicast bit to capture multicast frames. */ 2030 if (ifp->if_flags & IFF_MULTICAST) { 2031 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2032 } 2033 2034 /* Init the cam filter. */ 2035 vge_cam_clear(sc); 2036 2037 /* Init the multicast filter. */ 2038 vge_setmulti(sc); 2039 2040 /* Enable flow control */ 2041 2042 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2043 2044 /* Enable jumbo frame reception (if desired) */ 2045 2046 /* Start the MAC. */ 2047 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2048 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2049 CSR_WRITE_1(sc, VGE_CRS0, 2050 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2051 2052 /* 2053 * Configure one-shot timer for microsecond 2054 * resulution and load it for 500 usecs. 2055 */ 2056 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2057 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2058 2059 /* 2060 * Configure interrupt moderation for receive. Enable 2061 * the holdoff counter and load it, and set the RX 2062 * suppression count to the number of descriptors we 2063 * want to allow before triggering an interrupt. 2064 * The holdoff timer is in units of 20 usecs. 2065 */ 2066 2067#ifdef notyet 2068 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2069 /* Select the interrupt holdoff timer page. */ 2070 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2071 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2072 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2073 2074 /* Enable use of the holdoff timer. */ 2075 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2076 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2077 2078 /* Select the RX suppression threshold page. */ 2079 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2080 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2081 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2082 2083 /* Restore the page select bits. */ 2084 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2085 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2086#endif 2087 2088#ifdef DEVICE_POLLING 2089 /* 2090 * Disable interrupts if we are polling. 2091 */ 2092 if (ifp->if_capenable & IFCAP_POLLING) { 2093 CSR_WRITE_4(sc, VGE_IMR, 0); 2094 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2095 } else /* otherwise ... */ 2096#endif 2097 { 2098 /* 2099 * Enable interrupts. 2100 */ 2101 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2102 CSR_WRITE_4(sc, VGE_ISR, 0); 2103 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2104 } 2105 2106 mii_mediachg(mii); 2107 2108 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2109 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2110 2111 sc->vge_if_flags = 0; 2112 sc->vge_link = 0; 2113 2114 VGE_UNLOCK(sc); 2115 2116 return; 2117} 2118 2119/* 2120 * Set media options. 2121 */ 2122static int 2123vge_ifmedia_upd(ifp) 2124 struct ifnet *ifp; 2125{ 2126 struct vge_softc *sc; 2127 struct mii_data *mii; 2128 2129 sc = ifp->if_softc; 2130 mii = device_get_softc(sc->vge_miibus); 2131 mii_mediachg(mii); 2132 2133 return (0); 2134} 2135 2136/* 2137 * Report current media status. 2138 */ 2139static void 2140vge_ifmedia_sts(ifp, ifmr) 2141 struct ifnet *ifp; 2142 struct ifmediareq *ifmr; 2143{ 2144 struct vge_softc *sc; 2145 struct mii_data *mii; 2146 2147 sc = ifp->if_softc; 2148 mii = device_get_softc(sc->vge_miibus); 2149 2150 mii_pollstat(mii); 2151 ifmr->ifm_active = mii->mii_media_active; 2152 ifmr->ifm_status = mii->mii_media_status; 2153 2154 return; 2155} 2156 2157static void 2158vge_miibus_statchg(dev) 2159 device_t dev; 2160{ 2161 struct vge_softc *sc; 2162 struct mii_data *mii; 2163 struct ifmedia_entry *ife; 2164 2165 sc = device_get_softc(dev); 2166 mii = device_get_softc(sc->vge_miibus); 2167 ife = mii->mii_media.ifm_cur; 2168 2169 /* 2170 * If the user manually selects a media mode, we need to turn 2171 * on the forced MAC mode bit in the DIAGCTL register. If the 2172 * user happens to choose a full duplex mode, we also need to 2173 * set the 'force full duplex' bit. This applies only to 2174 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2175 * mode is disabled, and in 1000baseT mode, full duplex is 2176 * always implied, so we turn on the forced mode bit but leave 2177 * the FDX bit cleared. 2178 */ 2179 2180 switch (IFM_SUBTYPE(ife->ifm_media)) { 2181 case IFM_AUTO: 2182 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2183 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2184 break; 2185 case IFM_1000_T: 2186 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2187 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2188 break; 2189 case IFM_100_TX: 2190 case IFM_10_T: 2191 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2192 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2193 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2194 } else { 2195 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2196 } 2197 break; 2198 default: 2199 device_printf(dev, "unknown media type: %x\n", 2200 IFM_SUBTYPE(ife->ifm_media)); 2201 break; 2202 } 2203 2204 return; 2205} 2206 2207static int 2208vge_ioctl(ifp, command, data) 2209 struct ifnet *ifp; 2210 u_long command; 2211 caddr_t data; 2212{ 2213 struct vge_softc *sc = ifp->if_softc; 2214 struct ifreq *ifr = (struct ifreq *) data; 2215 struct mii_data *mii; 2216 int error = 0; 2217 2218 switch (command) { 2219 case SIOCSIFMTU: 2220 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2221 error = EINVAL; 2222 ifp->if_mtu = ifr->ifr_mtu; 2223 break; 2224 case SIOCSIFFLAGS: 2225 if (ifp->if_flags & IFF_UP) { 2226 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2227 ifp->if_flags & IFF_PROMISC && 2228 !(sc->vge_if_flags & IFF_PROMISC)) { 2229 CSR_SETBIT_1(sc, VGE_RXCTL, 2230 VGE_RXCTL_RX_PROMISC); 2231 vge_setmulti(sc); 2232 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2233 !(ifp->if_flags & IFF_PROMISC) && 2234 sc->vge_if_flags & IFF_PROMISC) { 2235 CSR_CLRBIT_1(sc, VGE_RXCTL, 2236 VGE_RXCTL_RX_PROMISC); 2237 vge_setmulti(sc); 2238 } else 2239 vge_init(sc); 2240 } else { 2241 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2242 vge_stop(sc); 2243 } 2244 sc->vge_if_flags = ifp->if_flags; 2245 break; 2246 case SIOCADDMULTI: 2247 case SIOCDELMULTI: 2248 vge_setmulti(sc); 2249 break; 2250 case SIOCGIFMEDIA: 2251 case SIOCSIFMEDIA: 2252 mii = device_get_softc(sc->vge_miibus); 2253 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2254 break; 2255 case SIOCSIFCAP: 2256 { 2257 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2258#ifdef DEVICE_POLLING 2259 if (mask & IFCAP_POLLING) { 2260 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2261 error = ether_poll_register(vge_poll, ifp); 2262 if (error) 2263 return(error); 2264 VGE_LOCK(sc); 2265 /* Disable interrupts */ 2266 CSR_WRITE_4(sc, VGE_IMR, 0); 2267 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2268 ifp->if_capenable |= IFCAP_POLLING; 2269 VGE_UNLOCK(sc); 2270 } else { 2271 error = ether_poll_deregister(ifp); 2272 /* Enable interrupts. */ 2273 VGE_LOCK(sc); 2274 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2275 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2276 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2277 ifp->if_capenable &= ~IFCAP_POLLING; 2278 VGE_UNLOCK(sc); 2279 } 2280 } 2281#endif /* DEVICE_POLLING */ 2282 if (mask & IFCAP_HWCSUM) { 2283 ifp->if_capenable |= ifr->ifr_reqcap & (IFCAP_HWCSUM); 2284 if (ifp->if_capenable & IFCAP_TXCSUM) 2285 ifp->if_hwassist = VGE_CSUM_FEATURES; 2286 else 2287 ifp->if_hwassist = 0; 2288 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2289 vge_init(sc); 2290 } 2291 } 2292 break; 2293 default: 2294 error = ether_ioctl(ifp, command, data); 2295 break; 2296 } 2297 2298 return (error); 2299} 2300 2301static void 2302vge_watchdog(ifp) 2303 struct ifnet *ifp; 2304{ 2305 struct vge_softc *sc; 2306 2307 sc = ifp->if_softc; 2308 VGE_LOCK(sc); 2309 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2310 ifp->if_oerrors++; 2311 2312 vge_txeof(sc); 2313 vge_rxeof(sc); 2314 2315 vge_init(sc); 2316 2317 VGE_UNLOCK(sc); 2318 2319 return; 2320} 2321 2322/* 2323 * Stop the adapter and free any mbufs allocated to the 2324 * RX and TX lists. 2325 */ 2326static void 2327vge_stop(sc) 2328 struct vge_softc *sc; 2329{ 2330 register int i; 2331 struct ifnet *ifp; 2332 2333 VGE_LOCK(sc); 2334 ifp = sc->vge_ifp; 2335 ifp->if_timer = 0; 2336 2337 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2338 2339 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2340 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2341 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2342 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2343 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2344 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2345 2346 if (sc->vge_head != NULL) { 2347 m_freem(sc->vge_head); 2348 sc->vge_head = sc->vge_tail = NULL; 2349 } 2350 2351 /* Free the TX list buffers. */ 2352 2353 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2354 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2355 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2356 sc->vge_ldata.vge_tx_dmamap[i]); 2357 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2358 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2359 } 2360 } 2361 2362 /* Free the RX list buffers. */ 2363 2364 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2365 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2366 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2367 sc->vge_ldata.vge_rx_dmamap[i]); 2368 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2369 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2370 } 2371 } 2372 2373 VGE_UNLOCK(sc); 2374 2375 return; 2376} 2377 2378/* 2379 * Device suspend routine. Stop the interface and save some PCI 2380 * settings in case the BIOS doesn't restore them properly on 2381 * resume. 2382 */ 2383static int 2384vge_suspend(dev) 2385 device_t dev; 2386{ 2387 struct vge_softc *sc; 2388 2389 sc = device_get_softc(dev); 2390 2391 vge_stop(sc); 2392 2393 sc->suspended = 1; 2394 2395 return (0); 2396} 2397 2398/* 2399 * Device resume routine. Restore some PCI settings in case the BIOS 2400 * doesn't, re-enable busmastering, and restart the interface if 2401 * appropriate. 2402 */ 2403static int 2404vge_resume(dev) 2405 device_t dev; 2406{ 2407 struct vge_softc *sc; 2408 struct ifnet *ifp; 2409 2410 sc = device_get_softc(dev); 2411 ifp = sc->vge_ifp; 2412 2413 /* reenable busmastering */ 2414 pci_enable_busmaster(dev); 2415 pci_enable_io(dev, SYS_RES_MEMORY); 2416 2417 /* reinitialize interface if necessary */ 2418 if (ifp->if_flags & IFF_UP) 2419 vge_init(sc); 2420 2421 sc->suspended = 0; 2422 2423 return (0); 2424} 2425 2426/* 2427 * Stop all chip I/O so that the kernel's probe routines don't 2428 * get confused by errant DMAs when rebooting. 2429 */ 2430static void 2431vge_shutdown(dev) 2432 device_t dev; 2433{ 2434 struct vge_softc *sc; 2435 2436 sc = device_get_softc(dev); 2437 2438 vge_stop(sc); 2439} 2440