if_vge.c revision 150306
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 150306 2005-09-19 03:10:21Z imp $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#include <sys/param.h> 84#include <sys/endian.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/module.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92#include <sys/taskqueue.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_types.h> 100#include <net/if_vlan_var.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus.h> 105#include <machine/resource.h> 106#include <sys/bus.h> 107#include <sys/rman.h> 108 109#include <dev/mii/mii.h> 110#include <dev/mii/miivar.h> 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115MODULE_DEPEND(vge, pci, 1, 1, 1); 116MODULE_DEPEND(vge, ether, 1, 1, 1); 117MODULE_DEPEND(vge, miibus, 1, 1, 1); 118 119/* "controller miibus0" required. See GENERIC if you get errors here. */ 120#include "miibus_if.h" 121 122#include <dev/vge/if_vgereg.h> 123#include <dev/vge/if_vgevar.h> 124 125#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 126 127/* 128 * Various supported device vendors/types and their names. 129 */ 130static struct vge_type vge_devs[] = { 131 { VIA_VENDORID, VIA_DEVICEID_61XX, 132 "VIA Networking Gigabit Ethernet" }, 133 { 0, 0, NULL } 134}; 135 136static int vge_probe (device_t); 137static int vge_attach (device_t); 138static int vge_detach (device_t); 139 140static int vge_encap (struct vge_softc *, struct mbuf *, int); 141 142static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 143static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 144 bus_size_t, int); 145static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 146 bus_size_t, int); 147static int vge_allocmem (device_t, struct vge_softc *); 148static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 149static int vge_rx_list_init (struct vge_softc *); 150static int vge_tx_list_init (struct vge_softc *); 151#ifdef VGE_FIXUP_RX 152static __inline void vge_fixup_rx 153 (struct mbuf *); 154#endif 155static void vge_rxeof (struct vge_softc *); 156static void vge_txeof (struct vge_softc *); 157static void vge_intr (void *); 158static void vge_tick (void *); 159static void vge_tx_task (void *, int); 160static void vge_start (struct ifnet *); 161static int vge_ioctl (struct ifnet *, u_long, caddr_t); 162static void vge_init (void *); 163static void vge_stop (struct vge_softc *); 164static void vge_watchdog (struct ifnet *); 165static int vge_suspend (device_t); 166static int vge_resume (device_t); 167static void vge_shutdown (device_t); 168static int vge_ifmedia_upd (struct ifnet *); 169static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170 171#ifdef VGE_EEPROM 172static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 173#endif 174static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 175 176static void vge_miipoll_start (struct vge_softc *); 177static void vge_miipoll_stop (struct vge_softc *); 178static int vge_miibus_readreg (device_t, int, int); 179static int vge_miibus_writereg (device_t, int, int, int); 180static void vge_miibus_statchg (device_t); 181 182static void vge_cam_clear (struct vge_softc *); 183static int vge_cam_set (struct vge_softc *, uint8_t *); 184#if __FreeBSD_version < 502113 185static uint32_t vge_mchash (uint8_t *); 186#endif 187static void vge_setmulti (struct vge_softc *); 188static void vge_reset (struct vge_softc *); 189 190#define VGE_PCI_LOIO 0x10 191#define VGE_PCI_LOMEM 0x14 192 193static device_method_t vge_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, vge_probe), 196 DEVMETHOD(device_attach, vge_attach), 197 DEVMETHOD(device_detach, vge_detach), 198 DEVMETHOD(device_suspend, vge_suspend), 199 DEVMETHOD(device_resume, vge_resume), 200 DEVMETHOD(device_shutdown, vge_shutdown), 201 202 /* bus interface */ 203 DEVMETHOD(bus_print_child, bus_generic_print_child), 204 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 205 206 /* MII interface */ 207 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 208 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 209 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 210 211 { 0, 0 } 212}; 213 214static driver_t vge_driver = { 215 "vge", 216 vge_methods, 217 sizeof(struct vge_softc) 218}; 219 220static devclass_t vge_devclass; 221 222DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 223DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226#ifdef VGE_EEPROM 227/* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230static void 231vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235{ 236 register int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275} 276#endif 277 278/* 279 * Read a sequence of words from the EEPROM. 280 */ 281static void 282vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288{ 289 int i; 290#ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301#else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304#endif 305} 306 307static void 308vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310{ 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325} 326 327static void 328vge_miipoll_start(sc) 329 struct vge_softc *sc; 330{ 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365} 366 367static int 368vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371{ 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 VGE_LOCK(sc); 382 vge_miipoll_stop(sc); 383 384 /* Specify the register we want to read. */ 385 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386 387 /* Issue read command. */ 388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389 390 /* Wait for the read command bit to self-clear. */ 391 for (i = 0; i < VGE_TIMEOUT; i++) { 392 DELAY(1); 393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394 break; 395 } 396 397 if (i == VGE_TIMEOUT) 398 device_printf(sc->vge_dev, "MII read timed out\n"); 399 else 400 rval = CSR_READ_2(sc, VGE_MIIDATA); 401 402 vge_miipoll_start(sc); 403 VGE_UNLOCK(sc); 404 405 return (rval); 406} 407 408static int 409vge_miibus_writereg(dev, phy, reg, data) 410 device_t dev; 411 int phy, reg, data; 412{ 413 struct vge_softc *sc; 414 int i, rval = 0; 415 416 sc = device_get_softc(dev); 417 418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 419 return(0); 420 421 VGE_LOCK(sc); 422 vge_miipoll_stop(sc); 423 424 /* Specify the register we want to write. */ 425 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 426 427 /* Specify the data we want to write. */ 428 CSR_WRITE_2(sc, VGE_MIIDATA, data); 429 430 /* Issue write command. */ 431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 432 433 /* Wait for the write command bit to self-clear. */ 434 for (i = 0; i < VGE_TIMEOUT; i++) { 435 DELAY(1); 436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 437 break; 438 } 439 440 if (i == VGE_TIMEOUT) { 441 device_printf(sc->vge_dev, "MII write timed out\n"); 442 rval = EIO; 443 } 444 445 vge_miipoll_start(sc); 446 VGE_UNLOCK(sc); 447 448 return (rval); 449} 450 451static void 452vge_cam_clear(sc) 453 struct vge_softc *sc; 454{ 455 int i; 456 457 /* 458 * Turn off all the mask bits. This tells the chip 459 * that none of the entries in the CAM filter are valid. 460 * desired entries will be enabled as we fill the filter in. 461 */ 462 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 466 for (i = 0; i < 8; i++) 467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 468 469 /* Clear the VLAN filter too. */ 470 471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 472 for (i = 0; i < 8; i++) 473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 478 479 sc->vge_camidx = 0; 480 481 return; 482} 483 484static int 485vge_cam_set(sc, addr) 486 struct vge_softc *sc; 487 uint8_t *addr; 488{ 489 int i, error = 0; 490 491 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 492 return(ENOSPC); 493 494 /* Select the CAM data page. */ 495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 497 498 /* Set the filter entry we want to update and enable writing. */ 499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 500 501 /* Write the address to the CAM registers */ 502 for (i = 0; i < ETHER_ADDR_LEN; i++) 503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 504 505 /* Issue a write command. */ 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 507 508 /* Wake for it to clear. */ 509 for (i = 0; i < VGE_TIMEOUT; i++) { 510 DELAY(1); 511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 512 break; 513 } 514 515 if (i == VGE_TIMEOUT) { 516 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 517 error = EIO; 518 goto fail; 519 } 520 521 /* Select the CAM mask page. */ 522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 524 525 /* Set the mask bit that enables this filter. */ 526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 527 1<<(sc->vge_camidx & 7)); 528 529 sc->vge_camidx++; 530 531fail: 532 /* Turn off access to CAM. */ 533 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 536 537 return (error); 538} 539 540#if __FreeBSD_version < 502113 541static uint32_t 542vge_mchash(addr) 543 uint8_t *addr; 544{ 545 uint32_t crc, carry; 546 int idx, bit; 547 uint8_t data; 548 549 /* Compute CRC for the address value. */ 550 crc = 0xFFFFFFFF; /* initial value */ 551 552 for (idx = 0; idx < 6; idx++) { 553 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 554 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 555 crc <<= 1; 556 if (carry) 557 crc = (crc ^ 0x04c11db6) | carry; 558 } 559 } 560 561 return(crc); 562} 563#endif 564 565/* 566 * Program the multicast filter. We use the 64-entry CAM filter 567 * for perfect filtering. If there's more than 64 multicast addresses, 568 * we use the hash filter insted. 569 */ 570static void 571vge_setmulti(sc) 572 struct vge_softc *sc; 573{ 574 struct ifnet *ifp; 575 int error = 0/*, h = 0*/; 576 struct ifmultiaddr *ifma; 577 u_int32_t h, hashes[2] = { 0, 0 }; 578 579 ifp = sc->vge_ifp; 580 581 /* First, zot all the multicast entries. */ 582 vge_cam_clear(sc); 583 CSR_WRITE_4(sc, VGE_MAR0, 0); 584 CSR_WRITE_4(sc, VGE_MAR1, 0); 585 586 /* 587 * If the user wants allmulti or promisc mode, enable reception 588 * of all multicast frames. 589 */ 590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 592 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 593 return; 594 } 595 596 /* Now program new ones */ 597 IF_ADDR_LOCK(ifp); 598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 599 if (ifma->ifma_addr->sa_family != AF_LINK) 600 continue; 601 error = vge_cam_set(sc, 602 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 603 if (error) 604 break; 605 } 606 607 /* If there were too many addresses, use the hash filter. */ 608 if (error) { 609 vge_cam_clear(sc); 610 611 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 612 if (ifma->ifma_addr->sa_family != AF_LINK) 613 continue; 614#if __FreeBSD_version < 502113 615 h = vge_mchash(LLADDR((struct sockaddr_dl *) 616 ifma->ifma_addr)) >> 26; 617#else 618 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 619 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 620#endif 621 if (h < 32) 622 hashes[0] |= (1 << h); 623 else 624 hashes[1] |= (1 << (h - 32)); 625 } 626 627 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 628 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 629 } 630 IF_ADDR_UNLOCK(ifp); 631 632 return; 633} 634 635static void 636vge_reset(sc) 637 struct vge_softc *sc; 638{ 639 register int i; 640 641 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 642 643 for (i = 0; i < VGE_TIMEOUT; i++) { 644 DELAY(5); 645 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 646 break; 647 } 648 649 if (i == VGE_TIMEOUT) { 650 device_printf(sc->vge_dev, "soft reset timed out"); 651 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 652 DELAY(2000); 653 } 654 655 DELAY(5000); 656 657 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 658 659 for (i = 0; i < VGE_TIMEOUT; i++) { 660 DELAY(5); 661 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 662 break; 663 } 664 665 if (i == VGE_TIMEOUT) { 666 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 667 return; 668 } 669 670 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 671 672 return; 673} 674 675/* 676 * Probe for a VIA gigabit chip. Check the PCI vendor and device 677 * IDs against our list and return a device name if we find a match. 678 */ 679static int 680vge_probe(dev) 681 device_t dev; 682{ 683 struct vge_type *t; 684 struct vge_softc *sc; 685 686 t = vge_devs; 687 sc = device_get_softc(dev); 688 689 while (t->vge_name != NULL) { 690 if ((pci_get_vendor(dev) == t->vge_vid) && 691 (pci_get_device(dev) == t->vge_did)) { 692 device_set_desc(dev, t->vge_name); 693 return (BUS_PROBE_DEFAULT); 694 } 695 t++; 696 } 697 698 return (ENXIO); 699} 700 701static void 702vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 703 void *arg; 704 bus_dma_segment_t *segs; 705 int nseg; 706 bus_size_t mapsize; 707 int error; 708{ 709 710 struct vge_dmaload_arg *ctx; 711 struct vge_rx_desc *d = NULL; 712 713 if (error) 714 return; 715 716 ctx = arg; 717 718 /* Signal error to caller if there's too many segments */ 719 if (nseg > ctx->vge_maxsegs) { 720 ctx->vge_maxsegs = 0; 721 return; 722 } 723 724 /* 725 * Map the segment array into descriptors. 726 */ 727 728 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 729 730 /* If this descriptor is still owned by the chip, bail. */ 731 732 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 733 device_printf(ctx->sc->vge_dev, 734 "tried to map busy descriptor\n"); 735 ctx->vge_maxsegs = 0; 736 return; 737 } 738 739 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 740 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 741 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 742 d->vge_sts = 0; 743 d->vge_ctl = 0; 744 745 ctx->vge_maxsegs = 1; 746 747 return; 748} 749 750static void 751vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 752 void *arg; 753 bus_dma_segment_t *segs; 754 int nseg; 755 bus_size_t mapsize; 756 int error; 757{ 758 struct vge_dmaload_arg *ctx; 759 struct vge_tx_desc *d = NULL; 760 struct vge_tx_frag *f; 761 int i = 0; 762 763 if (error) 764 return; 765 766 ctx = arg; 767 768 /* Signal error to caller if there's too many segments */ 769 if (nseg > ctx->vge_maxsegs) { 770 ctx->vge_maxsegs = 0; 771 return; 772 } 773 774 /* Map the segment array into descriptors. */ 775 776 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 777 778 /* If this descriptor is still owned by the chip, bail. */ 779 780 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 781 ctx->vge_maxsegs = 0; 782 return; 783 } 784 785 for (i = 0; i < nseg; i++) { 786 f = &d->vge_frag[i]; 787 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 788 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 789 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 790 } 791 792 /* Argh. This chip does not autopad short frames */ 793 794 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 795 f = &d->vge_frag[i]; 796 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 797 ctx->vge_m0->m_pkthdr.len)); 798 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 799 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 800 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 801 i++; 802 } 803 804 /* 805 * When telling the chip how many segments there are, we 806 * must use nsegs + 1 instead of just nsegs. Darned if I 807 * know why. 808 */ 809 i++; 810 811 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 812 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 813 814 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 815 d->vge_ctl |= VGE_TDCTL_JUMBO; 816 817 ctx->vge_maxsegs = nseg; 818 819 return; 820} 821 822/* 823 * Map a single buffer address. 824 */ 825 826static void 827vge_dma_map_addr(arg, segs, nseg, error) 828 void *arg; 829 bus_dma_segment_t *segs; 830 int nseg; 831 int error; 832{ 833 bus_addr_t *addr; 834 835 if (error) 836 return; 837 838 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 839 addr = arg; 840 *addr = segs->ds_addr; 841 842 return; 843} 844 845static int 846vge_allocmem(dev, sc) 847 device_t dev; 848 struct vge_softc *sc; 849{ 850 int error; 851 int nseg; 852 int i; 853 854 /* 855 * Allocate map for RX mbufs. 856 */ 857 nseg = 32; 858 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 859 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 860 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 861 NULL, NULL, &sc->vge_ldata.vge_mtag); 862 if (error) { 863 device_printf(dev, "could not allocate dma tag\n"); 864 return (ENOMEM); 865 } 866 867 /* 868 * Allocate map for TX descriptor list. 869 */ 870 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 871 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 872 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 873 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 874 if (error) { 875 device_printf(dev, "could not allocate dma tag\n"); 876 return (ENOMEM); 877 } 878 879 /* Allocate DMA'able memory for the TX ring */ 880 881 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 882 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 883 &sc->vge_ldata.vge_tx_list_map); 884 if (error) 885 return (ENOMEM); 886 887 /* Load the map for the TX ring. */ 888 889 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 890 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 891 VGE_TX_LIST_SZ, vge_dma_map_addr, 892 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 893 894 /* Create DMA maps for TX buffers */ 895 896 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 897 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 898 &sc->vge_ldata.vge_tx_dmamap[i]); 899 if (error) { 900 device_printf(dev, "can't create DMA map for TX\n"); 901 return (ENOMEM); 902 } 903 } 904 905 /* 906 * Allocate map for RX descriptor list. 907 */ 908 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 909 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 910 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 911 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 912 if (error) { 913 device_printf(dev, "could not allocate dma tag\n"); 914 return (ENOMEM); 915 } 916 917 /* Allocate DMA'able memory for the RX ring */ 918 919 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 920 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 921 &sc->vge_ldata.vge_rx_list_map); 922 if (error) 923 return (ENOMEM); 924 925 /* Load the map for the RX ring. */ 926 927 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 928 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 929 VGE_TX_LIST_SZ, vge_dma_map_addr, 930 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 931 932 /* Create DMA maps for RX buffers */ 933 934 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 935 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 936 &sc->vge_ldata.vge_rx_dmamap[i]); 937 if (error) { 938 device_printf(dev, "can't create DMA map for RX\n"); 939 return (ENOMEM); 940 } 941 } 942 943 return (0); 944} 945 946/* 947 * Attach the interface. Allocate softc structures, do ifmedia 948 * setup and ethernet/BPF attach. 949 */ 950static int 951vge_attach(dev) 952 device_t dev; 953{ 954 u_char eaddr[ETHER_ADDR_LEN]; 955 struct vge_softc *sc; 956 struct ifnet *ifp; 957 int unit, error = 0, rid; 958 959 sc = device_get_softc(dev); 960 unit = device_get_unit(dev); 961 sc->vge_dev = dev; 962 963 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 964 MTX_DEF | MTX_RECURSE); 965 /* 966 * Map control/status registers. 967 */ 968 pci_enable_busmaster(dev); 969 970 rid = VGE_PCI_LOMEM; 971 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 972 0, ~0, 1, RF_ACTIVE); 973 974 if (sc->vge_res == NULL) { 975 printf ("vge%d: couldn't map ports/memory\n", unit); 976 error = ENXIO; 977 goto fail; 978 } 979 980 sc->vge_btag = rman_get_bustag(sc->vge_res); 981 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 982 983 /* Allocate interrupt */ 984 rid = 0; 985 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 986 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 987 988 if (sc->vge_irq == NULL) { 989 printf("vge%d: couldn't map interrupt\n", unit); 990 error = ENXIO; 991 goto fail; 992 } 993 994 /* Reset the adapter. */ 995 vge_reset(sc); 996 997 /* 998 * Get station address from the EEPROM. 999 */ 1000 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1001 1002 sc->vge_unit = unit; 1003 1004#if __FreeBSD_version < 502113 1005 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1006#endif 1007 1008 /* 1009 * Allocate the parent bus DMA tag appropriate for PCI. 1010 */ 1011#define VGE_NSEG_NEW 32 1012 error = bus_dma_tag_create(NULL, /* parent */ 1013 1, 0, /* alignment, boundary */ 1014 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1015 BUS_SPACE_MAXADDR, /* highaddr */ 1016 NULL, NULL, /* filter, filterarg */ 1017 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1018 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1019 BUS_DMA_ALLOCNOW, /* flags */ 1020 NULL, NULL, /* lockfunc, lockarg */ 1021 &sc->vge_parent_tag); 1022 if (error) 1023 goto fail; 1024 1025 error = vge_allocmem(dev, sc); 1026 1027 if (error) 1028 goto fail; 1029 1030 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1031 if (ifp == NULL) { 1032 printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1033 error = ENOSPC; 1034 goto fail; 1035 } 1036 1037 /* Do MII setup */ 1038 if (mii_phy_probe(dev, &sc->vge_miibus, 1039 vge_ifmedia_upd, vge_ifmedia_sts)) { 1040 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1041 error = ENXIO; 1042 goto fail; 1043 } 1044 1045 ifp->if_softc = sc; 1046 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1047 ifp->if_mtu = ETHERMTU; 1048 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1049 ifp->if_ioctl = vge_ioctl; 1050 ifp->if_capabilities = IFCAP_VLAN_MTU; 1051 ifp->if_start = vge_start; 1052 ifp->if_hwassist = VGE_CSUM_FEATURES; 1053 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1054#ifdef DEVICE_POLLING 1055#ifdef IFCAP_POLLING 1056 ifp->if_capabilities |= IFCAP_POLLING; 1057#endif 1058#endif 1059 ifp->if_watchdog = vge_watchdog; 1060 ifp->if_init = vge_init; 1061 ifp->if_baudrate = 1000000000; 1062 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1063 ifp->if_capenable = ifp->if_capabilities; 1064 1065 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1066 1067 /* 1068 * Call MI attach routine. 1069 */ 1070 ether_ifattach(ifp, eaddr); 1071 1072 /* Hook interrupt last to avoid having to lock softc */ 1073 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1074 vge_intr, sc, &sc->vge_intrhand); 1075 1076 if (error) { 1077 printf("vge%d: couldn't set up irq\n", unit); 1078 ether_ifdetach(ifp); 1079 goto fail; 1080 } 1081 1082fail: 1083 if (error) 1084 vge_detach(dev); 1085 1086 return (error); 1087} 1088 1089/* 1090 * Shutdown hardware and free up resources. This can be called any 1091 * time after the mutex has been initialized. It is called in both 1092 * the error case in attach and the normal detach case so it needs 1093 * to be careful about only freeing resources that have actually been 1094 * allocated. 1095 */ 1096static int 1097vge_detach(dev) 1098 device_t dev; 1099{ 1100 struct vge_softc *sc; 1101 struct ifnet *ifp; 1102 int i; 1103 1104 sc = device_get_softc(dev); 1105 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1106 ifp = sc->vge_ifp; 1107 1108 /* These should only be active if attach succeeded */ 1109 if (device_is_attached(dev)) { 1110 vge_stop(sc); 1111 /* 1112 * Force off the IFF_UP flag here, in case someone 1113 * still had a BPF descriptor attached to this 1114 * interface. If they do, ether_ifattach() will cause 1115 * the BPF code to try and clear the promisc mode 1116 * flag, which will bubble down to vge_ioctl(), 1117 * which will try to call vge_init() again. This will 1118 * turn the NIC back on and restart the MII ticker, 1119 * which will panic the system when the kernel tries 1120 * to invoke the vge_tick() function that isn't there 1121 * anymore. 1122 */ 1123 ifp->if_flags &= ~IFF_UP; 1124 ether_ifdetach(ifp); 1125 } 1126 if (sc->vge_miibus) 1127 device_delete_child(dev, sc->vge_miibus); 1128 bus_generic_detach(dev); 1129 1130 if (sc->vge_intrhand) 1131 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1132 if (sc->vge_irq) 1133 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1134 if (sc->vge_res) 1135 bus_release_resource(dev, SYS_RES_MEMORY, 1136 VGE_PCI_LOMEM, sc->vge_res); 1137 if (ifp) 1138 if_free(ifp); 1139 1140 /* Unload and free the RX DMA ring memory and map */ 1141 1142 if (sc->vge_ldata.vge_rx_list_tag) { 1143 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1144 sc->vge_ldata.vge_rx_list_map); 1145 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1146 sc->vge_ldata.vge_rx_list, 1147 sc->vge_ldata.vge_rx_list_map); 1148 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1149 } 1150 1151 /* Unload and free the TX DMA ring memory and map */ 1152 1153 if (sc->vge_ldata.vge_tx_list_tag) { 1154 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1155 sc->vge_ldata.vge_tx_list_map); 1156 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1157 sc->vge_ldata.vge_tx_list, 1158 sc->vge_ldata.vge_tx_list_map); 1159 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1160 } 1161 1162 /* Destroy all the RX and TX buffer maps */ 1163 1164 if (sc->vge_ldata.vge_mtag) { 1165 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1166 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1167 sc->vge_ldata.vge_tx_dmamap[i]); 1168 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1169 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1170 sc->vge_ldata.vge_rx_dmamap[i]); 1171 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1172 } 1173 1174 if (sc->vge_parent_tag) 1175 bus_dma_tag_destroy(sc->vge_parent_tag); 1176 1177 mtx_destroy(&sc->vge_mtx); 1178 1179 return (0); 1180} 1181 1182static int 1183vge_newbuf(sc, idx, m) 1184 struct vge_softc *sc; 1185 int idx; 1186 struct mbuf *m; 1187{ 1188 struct vge_dmaload_arg arg; 1189 struct mbuf *n = NULL; 1190 int i, error; 1191 1192 if (m == NULL) { 1193 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1194 if (n == NULL) 1195 return (ENOBUFS); 1196 m = n; 1197 } else 1198 m->m_data = m->m_ext.ext_buf; 1199 1200 1201#ifdef VGE_FIXUP_RX 1202 /* 1203 * This is part of an evil trick to deal with non-x86 platforms. 1204 * The VIA chip requires RX buffers to be aligned on 32-bit 1205 * boundaries, but that will hose non-x86 machines. To get around 1206 * this, we leave some empty space at the start of each buffer 1207 * and for non-x86 hosts, we copy the buffer back two bytes 1208 * to achieve word alignment. This is slightly more efficient 1209 * than allocating a new buffer, copying the contents, and 1210 * discarding the old buffer. 1211 */ 1212 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1213 m_adj(m, VGE_ETHER_ALIGN); 1214#else 1215 m->m_len = m->m_pkthdr.len = MCLBYTES; 1216#endif 1217 1218 arg.sc = sc; 1219 arg.vge_idx = idx; 1220 arg.vge_maxsegs = 1; 1221 arg.vge_flags = 0; 1222 1223 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1224 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1225 &arg, BUS_DMA_NOWAIT); 1226 if (error || arg.vge_maxsegs != 1) { 1227 if (n != NULL) 1228 m_freem(n); 1229 return (ENOMEM); 1230 } 1231 1232 /* 1233 * Note: the manual fails to document the fact that for 1234 * proper opration, the driver needs to replentish the RX 1235 * DMA ring 4 descriptors at a time (rather than one at a 1236 * time, like most chips). We can allocate the new buffers 1237 * but we should not set the OWN bits until we're ready 1238 * to hand back 4 of them in one shot. 1239 */ 1240 1241#define VGE_RXCHUNK 4 1242 sc->vge_rx_consumed++; 1243 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1244 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1245 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1246 htole32(VGE_RDSTS_OWN); 1247 sc->vge_rx_consumed = 0; 1248 } 1249 1250 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1251 1252 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1253 sc->vge_ldata.vge_rx_dmamap[idx], 1254 BUS_DMASYNC_PREREAD); 1255 1256 return (0); 1257} 1258 1259static int 1260vge_tx_list_init(sc) 1261 struct vge_softc *sc; 1262{ 1263 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1264 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1265 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1266 1267 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1268 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1269 sc->vge_ldata.vge_tx_prodidx = 0; 1270 sc->vge_ldata.vge_tx_considx = 0; 1271 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1272 1273 return (0); 1274} 1275 1276static int 1277vge_rx_list_init(sc) 1278 struct vge_softc *sc; 1279{ 1280 int i; 1281 1282 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1283 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1284 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1285 1286 sc->vge_rx_consumed = 0; 1287 1288 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1289 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1290 return (ENOBUFS); 1291 } 1292 1293 /* Flush the RX descriptors */ 1294 1295 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1296 sc->vge_ldata.vge_rx_list_map, 1297 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1298 1299 sc->vge_ldata.vge_rx_prodidx = 0; 1300 sc->vge_rx_consumed = 0; 1301 sc->vge_head = sc->vge_tail = NULL; 1302 1303 return (0); 1304} 1305 1306#ifdef VGE_FIXUP_RX 1307static __inline void 1308vge_fixup_rx(m) 1309 struct mbuf *m; 1310{ 1311 int i; 1312 uint16_t *src, *dst; 1313 1314 src = mtod(m, uint16_t *); 1315 dst = src - 1; 1316 1317 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1318 *dst++ = *src++; 1319 1320 m->m_data -= ETHER_ALIGN; 1321 1322 return; 1323} 1324#endif 1325 1326/* 1327 * RX handler. We support the reception of jumbo frames that have 1328 * been fragmented across multiple 2K mbuf cluster buffers. 1329 */ 1330static void 1331vge_rxeof(sc) 1332 struct vge_softc *sc; 1333{ 1334 struct mbuf *m; 1335 struct ifnet *ifp; 1336 int i, total_len; 1337 int lim = 0; 1338 struct vge_rx_desc *cur_rx; 1339 u_int32_t rxstat, rxctl; 1340 1341 VGE_LOCK_ASSERT(sc); 1342 ifp = sc->vge_ifp; 1343 i = sc->vge_ldata.vge_rx_prodidx; 1344 1345 /* Invalidate the descriptor memory */ 1346 1347 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1348 sc->vge_ldata.vge_rx_list_map, 1349 BUS_DMASYNC_POSTREAD); 1350 1351 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1352 1353#ifdef DEVICE_POLLING 1354 if (ifp->if_flags & IFF_POLLING) { 1355 if (sc->rxcycles <= 0) 1356 break; 1357 sc->rxcycles--; 1358 } 1359#endif /* DEVICE_POLLING */ 1360 1361 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1362 m = sc->vge_ldata.vge_rx_mbuf[i]; 1363 total_len = VGE_RXBYTES(cur_rx); 1364 rxstat = le32toh(cur_rx->vge_sts); 1365 rxctl = le32toh(cur_rx->vge_ctl); 1366 1367 /* Invalidate the RX mbuf and unload its map */ 1368 1369 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1370 sc->vge_ldata.vge_rx_dmamap[i], 1371 BUS_DMASYNC_POSTWRITE); 1372 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1373 sc->vge_ldata.vge_rx_dmamap[i]); 1374 1375 /* 1376 * If the 'start of frame' bit is set, this indicates 1377 * either the first fragment in a multi-fragment receive, 1378 * or an intermediate fragment. Either way, we want to 1379 * accumulate the buffers. 1380 */ 1381 if (rxstat & VGE_RXPKT_SOF) { 1382 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1383 if (sc->vge_head == NULL) 1384 sc->vge_head = sc->vge_tail = m; 1385 else { 1386 m->m_flags &= ~M_PKTHDR; 1387 sc->vge_tail->m_next = m; 1388 sc->vge_tail = m; 1389 } 1390 vge_newbuf(sc, i, NULL); 1391 VGE_RX_DESC_INC(i); 1392 continue; 1393 } 1394 1395 /* 1396 * Bad/error frames will have the RXOK bit cleared. 1397 * However, there's one error case we want to allow: 1398 * if a VLAN tagged frame arrives and the chip can't 1399 * match it against the CAM filter, it considers this 1400 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1401 * We don't want to drop the frame though: our VLAN 1402 * filtering is done in software. 1403 */ 1404 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1405 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1406 ifp->if_ierrors++; 1407 /* 1408 * If this is part of a multi-fragment packet, 1409 * discard all the pieces. 1410 */ 1411 if (sc->vge_head != NULL) { 1412 m_freem(sc->vge_head); 1413 sc->vge_head = sc->vge_tail = NULL; 1414 } 1415 vge_newbuf(sc, i, m); 1416 VGE_RX_DESC_INC(i); 1417 continue; 1418 } 1419 1420 /* 1421 * If allocating a replacement mbuf fails, 1422 * reload the current one. 1423 */ 1424 1425 if (vge_newbuf(sc, i, NULL)) { 1426 ifp->if_ierrors++; 1427 if (sc->vge_head != NULL) { 1428 m_freem(sc->vge_head); 1429 sc->vge_head = sc->vge_tail = NULL; 1430 } 1431 vge_newbuf(sc, i, m); 1432 VGE_RX_DESC_INC(i); 1433 continue; 1434 } 1435 1436 VGE_RX_DESC_INC(i); 1437 1438 if (sc->vge_head != NULL) { 1439 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1440 /* 1441 * Special case: if there's 4 bytes or less 1442 * in this buffer, the mbuf can be discarded: 1443 * the last 4 bytes is the CRC, which we don't 1444 * care about anyway. 1445 */ 1446 if (m->m_len <= ETHER_CRC_LEN) { 1447 sc->vge_tail->m_len -= 1448 (ETHER_CRC_LEN - m->m_len); 1449 m_freem(m); 1450 } else { 1451 m->m_len -= ETHER_CRC_LEN; 1452 m->m_flags &= ~M_PKTHDR; 1453 sc->vge_tail->m_next = m; 1454 } 1455 m = sc->vge_head; 1456 sc->vge_head = sc->vge_tail = NULL; 1457 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1458 } else 1459 m->m_pkthdr.len = m->m_len = 1460 (total_len - ETHER_CRC_LEN); 1461 1462#ifdef VGE_FIXUP_RX 1463 vge_fixup_rx(m); 1464#endif 1465 ifp->if_ipackets++; 1466 m->m_pkthdr.rcvif = ifp; 1467 1468 /* Do RX checksumming if enabled */ 1469 if (ifp->if_capenable & IFCAP_RXCSUM) { 1470 1471 /* Check IP header checksum */ 1472 if (rxctl & VGE_RDCTL_IPPKT) 1473 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1474 if (rxctl & VGE_RDCTL_IPCSUMOK) 1475 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1476 1477 /* Check TCP/UDP checksum */ 1478 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1479 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1480 m->m_pkthdr.csum_flags |= 1481 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1482 m->m_pkthdr.csum_data = 0xffff; 1483 } 1484 } 1485 1486 if (rxstat & VGE_RDSTS_VTAG) 1487 VLAN_INPUT_TAG(ifp, m, 1488 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1489 1490 VGE_UNLOCK(sc); 1491 (*ifp->if_input)(ifp, m); 1492 VGE_LOCK(sc); 1493 1494 lim++; 1495 if (lim == VGE_RX_DESC_CNT) 1496 break; 1497 1498 } 1499 1500 /* Flush the RX DMA ring */ 1501 1502 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1503 sc->vge_ldata.vge_rx_list_map, 1504 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1505 1506 sc->vge_ldata.vge_rx_prodidx = i; 1507 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1508 1509 1510 return; 1511} 1512 1513static void 1514vge_txeof(sc) 1515 struct vge_softc *sc; 1516{ 1517 struct ifnet *ifp; 1518 u_int32_t txstat; 1519 int idx; 1520 1521 ifp = sc->vge_ifp; 1522 idx = sc->vge_ldata.vge_tx_considx; 1523 1524 /* Invalidate the TX descriptor list */ 1525 1526 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1527 sc->vge_ldata.vge_tx_list_map, 1528 BUS_DMASYNC_POSTREAD); 1529 1530 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1531 1532 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1533 if (txstat & VGE_TDSTS_OWN) 1534 break; 1535 1536 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1537 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1538 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1539 sc->vge_ldata.vge_tx_dmamap[idx]); 1540 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1541 ifp->if_collisions++; 1542 if (txstat & VGE_TDSTS_TXERR) 1543 ifp->if_oerrors++; 1544 else 1545 ifp->if_opackets++; 1546 1547 sc->vge_ldata.vge_tx_free++; 1548 VGE_TX_DESC_INC(idx); 1549 } 1550 1551 /* No changes made to the TX ring, so no flush needed */ 1552 1553 if (idx != sc->vge_ldata.vge_tx_considx) { 1554 sc->vge_ldata.vge_tx_considx = idx; 1555 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1556 ifp->if_timer = 0; 1557 } 1558 1559 /* 1560 * If not all descriptors have been released reaped yet, 1561 * reload the timer so that we will eventually get another 1562 * interrupt that will cause us to re-enter this routine. 1563 * This is done in case the transmitter has gone idle. 1564 */ 1565 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1566 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1567 } 1568 1569 return; 1570} 1571 1572static void 1573vge_tick(xsc) 1574 void *xsc; 1575{ 1576 struct vge_softc *sc; 1577 struct ifnet *ifp; 1578 struct mii_data *mii; 1579 1580 sc = xsc; 1581 ifp = sc->vge_ifp; 1582 VGE_LOCK(sc); 1583 mii = device_get_softc(sc->vge_miibus); 1584 1585 mii_tick(mii); 1586 if (sc->vge_link) { 1587 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1588 sc->vge_link = 0; 1589 if_link_state_change(sc->vge_ifp, 1590 LINK_STATE_DOWN); 1591 } 1592 } else { 1593 if (mii->mii_media_status & IFM_ACTIVE && 1594 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1595 sc->vge_link = 1; 1596 if_link_state_change(sc->vge_ifp, 1597 LINK_STATE_UP); 1598#if __FreeBSD_version < 502114 1599 if (ifp->if_snd.ifq_head != NULL) 1600#else 1601 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1602#endif 1603 taskqueue_enqueue(taskqueue_swi, 1604 &sc->vge_txtask); 1605 } 1606 } 1607 1608 VGE_UNLOCK(sc); 1609 1610 return; 1611} 1612 1613#ifdef DEVICE_POLLING 1614static void 1615vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1616{ 1617 struct vge_softc *sc = ifp->if_softc; 1618 1619 VGE_LOCK(sc); 1620#ifdef IFCAP_POLLING 1621 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1622 ether_poll_deregister(ifp); 1623 cmd = POLL_DEREGISTER; 1624 } 1625#endif 1626 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1627 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1628 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1629 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1630 goto done; 1631 } 1632 1633 sc->rxcycles = count; 1634 vge_rxeof(sc); 1635 vge_txeof(sc); 1636 1637#if __FreeBSD_version < 502114 1638 if (ifp->if_snd.ifq_head != NULL) 1639#else 1640 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1641#endif 1642 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1643 1644 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1645 u_int32_t status; 1646 status = CSR_READ_4(sc, VGE_ISR); 1647 if (status == 0xFFFFFFFF) 1648 goto done; 1649 if (status) 1650 CSR_WRITE_4(sc, VGE_ISR, status); 1651 1652 /* 1653 * XXX check behaviour on receiver stalls. 1654 */ 1655 1656 if (status & VGE_ISR_TXDMA_STALL || 1657 status & VGE_ISR_RXDMA_STALL) 1658 vge_init(sc); 1659 1660 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1661 vge_rxeof(sc); 1662 ifp->if_ierrors++; 1663 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1664 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1665 } 1666 } 1667done: 1668 VGE_UNLOCK(sc); 1669} 1670#endif /* DEVICE_POLLING */ 1671 1672static void 1673vge_intr(arg) 1674 void *arg; 1675{ 1676 struct vge_softc *sc; 1677 struct ifnet *ifp; 1678 u_int32_t status; 1679 1680 sc = arg; 1681 1682 if (sc->suspended) { 1683 return; 1684 } 1685 1686 VGE_LOCK(sc); 1687 ifp = sc->vge_ifp; 1688 1689 if (!(ifp->if_flags & IFF_UP)) { 1690 VGE_UNLOCK(sc); 1691 return; 1692 } 1693 1694#ifdef DEVICE_POLLING 1695 if (ifp->if_flags & IFF_POLLING) 1696 goto done; 1697 if ( 1698#ifdef IFCAP_POLLING 1699 (ifp->if_capenable & IFCAP_POLLING) && 1700#endif 1701 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1702 CSR_WRITE_4(sc, VGE_IMR, 0); 1703 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1704 vge_poll(ifp, 0, 1); 1705 goto done; 1706 } 1707 1708#endif /* DEVICE_POLLING */ 1709 1710 /* Disable interrupts */ 1711 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1712 1713 for (;;) { 1714 1715 status = CSR_READ_4(sc, VGE_ISR); 1716 /* If the card has gone away the read returns 0xffff. */ 1717 if (status == 0xFFFFFFFF) 1718 break; 1719 1720 if (status) 1721 CSR_WRITE_4(sc, VGE_ISR, status); 1722 1723 if ((status & VGE_INTRS) == 0) 1724 break; 1725 1726 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1727 vge_rxeof(sc); 1728 1729 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1730 vge_rxeof(sc); 1731 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1732 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1733 } 1734 1735 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1736 vge_txeof(sc); 1737 1738 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1739 vge_init(sc); 1740 1741 if (status & VGE_ISR_LINKSTS) 1742 vge_tick(sc); 1743 } 1744 1745 /* Re-enable interrupts */ 1746 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1747 1748#ifdef DEVICE_POLLING 1749done: 1750#endif 1751 VGE_UNLOCK(sc); 1752 1753#if __FreeBSD_version < 502114 1754 if (ifp->if_snd.ifq_head != NULL) 1755#else 1756 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1757#endif 1758 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1759 1760 return; 1761} 1762 1763static int 1764vge_encap(sc, m_head, idx) 1765 struct vge_softc *sc; 1766 struct mbuf *m_head; 1767 int idx; 1768{ 1769 struct mbuf *m_new = NULL; 1770 struct vge_dmaload_arg arg; 1771 bus_dmamap_t map; 1772 int error; 1773 struct m_tag *mtag; 1774 1775 if (sc->vge_ldata.vge_tx_free <= 2) 1776 return (EFBIG); 1777 1778 arg.vge_flags = 0; 1779 1780 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1781 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1782 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1783 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1784 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1785 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1786 1787 arg.sc = sc; 1788 arg.vge_idx = idx; 1789 arg.vge_m0 = m_head; 1790 arg.vge_maxsegs = VGE_TX_FRAGS; 1791 1792 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1793 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1794 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1795 1796 if (error && error != EFBIG) { 1797 printf("vge%d: can't map mbuf (error %d)\n", 1798 sc->vge_unit, error); 1799 return (ENOBUFS); 1800 } 1801 1802 /* Too many segments to map, coalesce into a single mbuf */ 1803 1804 if (error || arg.vge_maxsegs == 0) { 1805 m_new = m_defrag(m_head, M_DONTWAIT); 1806 if (m_new == NULL) 1807 return (1); 1808 else 1809 m_head = m_new; 1810 1811 arg.sc = sc; 1812 arg.vge_m0 = m_head; 1813 arg.vge_idx = idx; 1814 arg.vge_maxsegs = 1; 1815 1816 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1817 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1818 if (error) { 1819 printf("vge%d: can't map mbuf (error %d)\n", 1820 sc->vge_unit, error); 1821 return (EFBIG); 1822 } 1823 } 1824 1825 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1826 sc->vge_ldata.vge_tx_free--; 1827 1828 /* 1829 * Set up hardware VLAN tagging. 1830 */ 1831 1832 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head); 1833 if (mtag != NULL) 1834 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1835 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1836 1837 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1838 1839 return (0); 1840} 1841 1842static void 1843vge_tx_task(arg, npending) 1844 void *arg; 1845 int npending; 1846{ 1847 struct ifnet *ifp; 1848 1849 ifp = arg; 1850 vge_start(ifp); 1851 1852 return; 1853} 1854 1855/* 1856 * Main transmit routine. 1857 */ 1858 1859static void 1860vge_start(ifp) 1861 struct ifnet *ifp; 1862{ 1863 struct vge_softc *sc; 1864 struct mbuf *m_head = NULL; 1865 int idx, pidx = 0; 1866 1867 sc = ifp->if_softc; 1868 VGE_LOCK(sc); 1869 1870 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1871 VGE_UNLOCK(sc); 1872 return; 1873 } 1874 1875#if __FreeBSD_version < 502114 1876 if (ifp->if_snd.ifq_head == NULL) { 1877#else 1878 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1879#endif 1880 VGE_UNLOCK(sc); 1881 return; 1882 } 1883 1884 idx = sc->vge_ldata.vge_tx_prodidx; 1885 1886 pidx = idx - 1; 1887 if (pidx < 0) 1888 pidx = VGE_TX_DESC_CNT - 1; 1889 1890 1891 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1892#if __FreeBSD_version < 502114 1893 IF_DEQUEUE(&ifp->if_snd, m_head); 1894#else 1895 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1896#endif 1897 if (m_head == NULL) 1898 break; 1899 1900 if (vge_encap(sc, m_head, idx)) { 1901#if __FreeBSD_version >= 502114 1902 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1903#else 1904 IF_PREPEND(&ifp->if_snd, m_head); 1905#endif 1906 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1907 break; 1908 } 1909 1910 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1911 htole16(VGE_TXDESC_Q); 1912 1913 pidx = idx; 1914 VGE_TX_DESC_INC(idx); 1915 1916 /* 1917 * If there's a BPF listener, bounce a copy of this frame 1918 * to him. 1919 */ 1920 BPF_MTAP(ifp, m_head); 1921 } 1922 1923 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1924 VGE_UNLOCK(sc); 1925 return; 1926 } 1927 1928 /* Flush the TX descriptors */ 1929 1930 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1931 sc->vge_ldata.vge_tx_list_map, 1932 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1933 1934 /* Issue a transmit command. */ 1935 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1936 1937 sc->vge_ldata.vge_tx_prodidx = idx; 1938 1939 /* 1940 * Use the countdown timer for interrupt moderation. 1941 * 'TX done' interrupts are disabled. Instead, we reset the 1942 * countdown timer, which will begin counting until it hits 1943 * the value in the SSTIMER register, and then trigger an 1944 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1945 * the timer count is reloaded. Only when the transmitter 1946 * is idle will the timer hit 0 and an interrupt fire. 1947 */ 1948 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1949 1950 VGE_UNLOCK(sc); 1951 1952 /* 1953 * Set a timeout in case the chip goes out to lunch. 1954 */ 1955 ifp->if_timer = 5; 1956 1957 return; 1958} 1959 1960static void 1961vge_init(xsc) 1962 void *xsc; 1963{ 1964 struct vge_softc *sc = xsc; 1965 struct ifnet *ifp = sc->vge_ifp; 1966 struct mii_data *mii; 1967 int i; 1968 1969 VGE_LOCK(sc); 1970 mii = device_get_softc(sc->vge_miibus); 1971 1972 /* 1973 * Cancel pending I/O and free all RX/TX buffers. 1974 */ 1975 vge_stop(sc); 1976 vge_reset(sc); 1977 1978 /* 1979 * Initialize the RX and TX descriptors and mbufs. 1980 */ 1981 1982 vge_rx_list_init(sc); 1983 vge_tx_list_init(sc); 1984 1985 /* Set our station address */ 1986 for (i = 0; i < ETHER_ADDR_LEN; i++) 1987 CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]); 1988 1989 /* 1990 * Set receive FIFO threshold. Also allow transmission and 1991 * reception of VLAN tagged frames. 1992 */ 1993 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1994 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1995 1996 /* Set DMA burst length */ 1997 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1998 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1999 2000 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2001 2002 /* Set collision backoff algorithm */ 2003 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2004 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2005 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2006 2007 /* Disable LPSEL field in priority resolution */ 2008 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2009 2010 /* 2011 * Load the addresses of the DMA queues into the chip. 2012 * Note that we only use one transmit queue. 2013 */ 2014 2015 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2016 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2017 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2018 2019 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2020 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2021 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2022 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2023 2024 /* Enable and wake up the RX descriptor queue */ 2025 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2026 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2027 2028 /* Enable the TX descriptor queue */ 2029 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2030 2031 /* Set up the receive filter -- allow large frames for VLANs. */ 2032 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2033 2034 /* If we want promiscuous mode, set the allframes bit. */ 2035 if (ifp->if_flags & IFF_PROMISC) { 2036 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2037 } 2038 2039 /* Set capture broadcast bit to capture broadcast frames. */ 2040 if (ifp->if_flags & IFF_BROADCAST) { 2041 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2042 } 2043 2044 /* Set multicast bit to capture multicast frames. */ 2045 if (ifp->if_flags & IFF_MULTICAST) { 2046 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2047 } 2048 2049 /* Init the cam filter. */ 2050 vge_cam_clear(sc); 2051 2052 /* Init the multicast filter. */ 2053 vge_setmulti(sc); 2054 2055 /* Enable flow control */ 2056 2057 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2058 2059 /* Enable jumbo frame reception (if desired) */ 2060 2061 /* Start the MAC. */ 2062 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2063 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2064 CSR_WRITE_1(sc, VGE_CRS0, 2065 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2066 2067 /* 2068 * Configure one-shot timer for microsecond 2069 * resulution and load it for 500 usecs. 2070 */ 2071 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2072 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2073 2074 /* 2075 * Configure interrupt moderation for receive. Enable 2076 * the holdoff counter and load it, and set the RX 2077 * suppression count to the number of descriptors we 2078 * want to allow before triggering an interrupt. 2079 * The holdoff timer is in units of 20 usecs. 2080 */ 2081 2082#ifdef notyet 2083 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2084 /* Select the interrupt holdoff timer page. */ 2085 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2086 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2087 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2088 2089 /* Enable use of the holdoff timer. */ 2090 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2091 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2092 2093 /* Select the RX suppression threshold page. */ 2094 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2095 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2096 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2097 2098 /* Restore the page select bits. */ 2099 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2100 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2101#endif 2102 2103#ifdef DEVICE_POLLING 2104 /* 2105 * Disable interrupts if we are polling. 2106 */ 2107 if (ifp->if_flags & IFF_POLLING) { 2108 CSR_WRITE_4(sc, VGE_IMR, 0); 2109 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2110 } else /* otherwise ... */ 2111#endif /* DEVICE_POLLING */ 2112 { 2113 /* 2114 * Enable interrupts. 2115 */ 2116 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2117 CSR_WRITE_4(sc, VGE_ISR, 0); 2118 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2119 } 2120 2121 mii_mediachg(mii); 2122 2123 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2124 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2125 2126 sc->vge_if_flags = 0; 2127 sc->vge_link = 0; 2128 2129 VGE_UNLOCK(sc); 2130 2131 return; 2132} 2133 2134/* 2135 * Set media options. 2136 */ 2137static int 2138vge_ifmedia_upd(ifp) 2139 struct ifnet *ifp; 2140{ 2141 struct vge_softc *sc; 2142 struct mii_data *mii; 2143 2144 sc = ifp->if_softc; 2145 mii = device_get_softc(sc->vge_miibus); 2146 mii_mediachg(mii); 2147 2148 return (0); 2149} 2150 2151/* 2152 * Report current media status. 2153 */ 2154static void 2155vge_ifmedia_sts(ifp, ifmr) 2156 struct ifnet *ifp; 2157 struct ifmediareq *ifmr; 2158{ 2159 struct vge_softc *sc; 2160 struct mii_data *mii; 2161 2162 sc = ifp->if_softc; 2163 mii = device_get_softc(sc->vge_miibus); 2164 2165 mii_pollstat(mii); 2166 ifmr->ifm_active = mii->mii_media_active; 2167 ifmr->ifm_status = mii->mii_media_status; 2168 2169 return; 2170} 2171 2172static void 2173vge_miibus_statchg(dev) 2174 device_t dev; 2175{ 2176 struct vge_softc *sc; 2177 struct mii_data *mii; 2178 struct ifmedia_entry *ife; 2179 2180 sc = device_get_softc(dev); 2181 mii = device_get_softc(sc->vge_miibus); 2182 ife = mii->mii_media.ifm_cur; 2183 2184 /* 2185 * If the user manually selects a media mode, we need to turn 2186 * on the forced MAC mode bit in the DIAGCTL register. If the 2187 * user happens to choose a full duplex mode, we also need to 2188 * set the 'force full duplex' bit. This applies only to 2189 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2190 * mode is disabled, and in 1000baseT mode, full duplex is 2191 * always implied, so we turn on the forced mode bit but leave 2192 * the FDX bit cleared. 2193 */ 2194 2195 switch (IFM_SUBTYPE(ife->ifm_media)) { 2196 case IFM_AUTO: 2197 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2198 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2199 break; 2200 case IFM_1000_T: 2201 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2202 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2203 break; 2204 case IFM_100_TX: 2205 case IFM_10_T: 2206 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2207 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2208 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2209 } else { 2210 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2211 } 2212 break; 2213 default: 2214 device_printf(dev, "unknown media type: %x\n", 2215 IFM_SUBTYPE(ife->ifm_media)); 2216 break; 2217 } 2218 2219 return; 2220} 2221 2222static int 2223vge_ioctl(ifp, command, data) 2224 struct ifnet *ifp; 2225 u_long command; 2226 caddr_t data; 2227{ 2228 struct vge_softc *sc = ifp->if_softc; 2229 struct ifreq *ifr = (struct ifreq *) data; 2230 struct mii_data *mii; 2231 int error = 0; 2232 2233 switch (command) { 2234 case SIOCSIFMTU: 2235 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2236 error = EINVAL; 2237 ifp->if_mtu = ifr->ifr_mtu; 2238 break; 2239 case SIOCSIFFLAGS: 2240 if (ifp->if_flags & IFF_UP) { 2241 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2242 ifp->if_flags & IFF_PROMISC && 2243 !(sc->vge_if_flags & IFF_PROMISC)) { 2244 CSR_SETBIT_1(sc, VGE_RXCTL, 2245 VGE_RXCTL_RX_PROMISC); 2246 vge_setmulti(sc); 2247 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2248 !(ifp->if_flags & IFF_PROMISC) && 2249 sc->vge_if_flags & IFF_PROMISC) { 2250 CSR_CLRBIT_1(sc, VGE_RXCTL, 2251 VGE_RXCTL_RX_PROMISC); 2252 vge_setmulti(sc); 2253 } else 2254 vge_init(sc); 2255 } else { 2256 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2257 vge_stop(sc); 2258 } 2259 sc->vge_if_flags = ifp->if_flags; 2260 break; 2261 case SIOCADDMULTI: 2262 case SIOCDELMULTI: 2263 vge_setmulti(sc); 2264 break; 2265 case SIOCGIFMEDIA: 2266 case SIOCSIFMEDIA: 2267 mii = device_get_softc(sc->vge_miibus); 2268 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2269 break; 2270 case SIOCSIFCAP: 2271#ifdef IFCAP_POLLING 2272 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2273#else 2274 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2275#endif 2276 ifp->if_capenable |= 2277#ifdef IFCAP_POLLING 2278 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2279#else 2280 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2281#endif 2282 if (ifp->if_capenable & IFCAP_TXCSUM) 2283 ifp->if_hwassist = VGE_CSUM_FEATURES; 2284 else 2285 ifp->if_hwassist = 0; 2286 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2287 vge_init(sc); 2288 break; 2289 default: 2290 error = ether_ioctl(ifp, command, data); 2291 break; 2292 } 2293 2294 return (error); 2295} 2296 2297static void 2298vge_watchdog(ifp) 2299 struct ifnet *ifp; 2300{ 2301 struct vge_softc *sc; 2302 2303 sc = ifp->if_softc; 2304 VGE_LOCK(sc); 2305 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2306 ifp->if_oerrors++; 2307 2308 vge_txeof(sc); 2309 vge_rxeof(sc); 2310 2311 vge_init(sc); 2312 2313 VGE_UNLOCK(sc); 2314 2315 return; 2316} 2317 2318/* 2319 * Stop the adapter and free any mbufs allocated to the 2320 * RX and TX lists. 2321 */ 2322static void 2323vge_stop(sc) 2324 struct vge_softc *sc; 2325{ 2326 register int i; 2327 struct ifnet *ifp; 2328 2329 VGE_LOCK(sc); 2330 ifp = sc->vge_ifp; 2331 ifp->if_timer = 0; 2332 2333 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2334#ifdef DEVICE_POLLING 2335 ether_poll_deregister(ifp); 2336#endif /* DEVICE_POLLING */ 2337 2338 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2339 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2340 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2341 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2342 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2343 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2344 2345 if (sc->vge_head != NULL) { 2346 m_freem(sc->vge_head); 2347 sc->vge_head = sc->vge_tail = NULL; 2348 } 2349 2350 /* Free the TX list buffers. */ 2351 2352 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2353 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2354 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2355 sc->vge_ldata.vge_tx_dmamap[i]); 2356 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2357 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2358 } 2359 } 2360 2361 /* Free the RX list buffers. */ 2362 2363 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2364 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2365 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2366 sc->vge_ldata.vge_rx_dmamap[i]); 2367 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2368 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2369 } 2370 } 2371 2372 VGE_UNLOCK(sc); 2373 2374 return; 2375} 2376 2377/* 2378 * Device suspend routine. Stop the interface and save some PCI 2379 * settings in case the BIOS doesn't restore them properly on 2380 * resume. 2381 */ 2382static int 2383vge_suspend(dev) 2384 device_t dev; 2385{ 2386 struct vge_softc *sc; 2387 2388 sc = device_get_softc(dev); 2389 2390 vge_stop(sc); 2391 2392 sc->suspended = 1; 2393 2394 return (0); 2395} 2396 2397/* 2398 * Device resume routine. Restore some PCI settings in case the BIOS 2399 * doesn't, re-enable busmastering, and restart the interface if 2400 * appropriate. 2401 */ 2402static int 2403vge_resume(dev) 2404 device_t dev; 2405{ 2406 struct vge_softc *sc; 2407 struct ifnet *ifp; 2408 2409 sc = device_get_softc(dev); 2410 ifp = sc->vge_ifp; 2411 2412 /* reenable busmastering */ 2413 pci_enable_busmaster(dev); 2414 pci_enable_io(dev, SYS_RES_MEMORY); 2415 2416 /* reinitialize interface if necessary */ 2417 if (ifp->if_flags & IFF_UP) 2418 vge_init(sc); 2419 2420 sc->suspended = 0; 2421 2422 return (0); 2423} 2424 2425/* 2426 * Stop all chip I/O so that the kernel's probe routines don't 2427 * get confused by errant DMAs when rebooting. 2428 */ 2429static void 2430vge_shutdown(dev) 2431 device_t dev; 2432{ 2433 struct vge_softc *sc; 2434 2435 sc = device_get_softc(dev); 2436 2437 vge_stop(sc); 2438} 2439