if_vge.c revision 145537
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 145537 2005-04-25 23:26:20Z wpaul $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#include <sys/param.h> 84#include <sys/endian.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/module.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92#include <sys/taskqueue.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_vlan_var.h> 100 101#include <net/bpf.h> 102 103#include <machine/bus_pio.h> 104#include <machine/bus_memio.h> 105#include <machine/bus.h> 106#include <machine/resource.h> 107#include <sys/bus.h> 108#include <sys/rman.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116MODULE_DEPEND(vge, pci, 1, 1, 1); 117MODULE_DEPEND(vge, ether, 1, 1, 1); 118MODULE_DEPEND(vge, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#include <dev/vge/if_vgereg.h> 124#include <dev/vge/if_vgevar.h> 125 126#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 127 128/* 129 * Various supported device vendors/types and their names. 130 */ 131static struct vge_type vge_devs[] = { 132 { VIA_VENDORID, VIA_DEVICEID_61XX, 133 "VIA Networking Gigabit Ethernet" }, 134 { 0, 0, NULL } 135}; 136 137static int vge_probe (device_t); 138static int vge_attach (device_t); 139static int vge_detach (device_t); 140 141static int vge_encap (struct vge_softc *, struct mbuf *, int); 142 143static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 144static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 145 bus_size_t, int); 146static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 147 bus_size_t, int); 148static int vge_allocmem (device_t, struct vge_softc *); 149static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 150static int vge_rx_list_init (struct vge_softc *); 151static int vge_tx_list_init (struct vge_softc *); 152#ifdef VGE_FIXUP_RX 153static __inline void vge_fixup_rx 154 (struct mbuf *); 155#endif 156static void vge_rxeof (struct vge_softc *); 157static void vge_txeof (struct vge_softc *); 158static void vge_intr (void *); 159static void vge_tick (void *); 160static void vge_tx_task (void *, int); 161static void vge_start (struct ifnet *); 162static int vge_ioctl (struct ifnet *, u_long, caddr_t); 163static void vge_init (void *); 164static void vge_stop (struct vge_softc *); 165static void vge_watchdog (struct ifnet *); 166static int vge_suspend (device_t); 167static int vge_resume (device_t); 168static void vge_shutdown (device_t); 169static int vge_ifmedia_upd (struct ifnet *); 170static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 171 172#ifdef VGE_EEPROM 173static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 174#endif 175static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 176 177static void vge_miipoll_start (struct vge_softc *); 178static void vge_miipoll_stop (struct vge_softc *); 179static int vge_miibus_readreg (device_t, int, int); 180static int vge_miibus_writereg (device_t, int, int, int); 181static void vge_miibus_statchg (device_t); 182 183static void vge_cam_clear (struct vge_softc *); 184static int vge_cam_set (struct vge_softc *, uint8_t *); 185#if __FreeBSD_version < 502113 186static uint32_t vge_mchash (uint8_t *); 187#endif 188static void vge_setmulti (struct vge_softc *); 189static void vge_reset (struct vge_softc *); 190 191#define VGE_PCI_LOIO 0x10 192#define VGE_PCI_LOMEM 0x14 193 194static device_method_t vge_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, vge_probe), 197 DEVMETHOD(device_attach, vge_attach), 198 DEVMETHOD(device_detach, vge_detach), 199 DEVMETHOD(device_suspend, vge_suspend), 200 DEVMETHOD(device_resume, vge_resume), 201 DEVMETHOD(device_shutdown, vge_shutdown), 202 203 /* bus interface */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211 212 { 0, 0 } 213}; 214 215static driver_t vge_driver = { 216 "vge", 217 vge_methods, 218 sizeof(struct vge_softc) 219}; 220 221static devclass_t vge_devclass; 222 223DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 225DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 226 227#ifdef VGE_EEPROM 228/* 229 * Read a word of data stored in the EEPROM at address 'addr.' 230 */ 231static void 232vge_eeprom_getword(sc, addr, dest) 233 struct vge_softc *sc; 234 int addr; 235 u_int16_t *dest; 236{ 237 register int i; 238 u_int16_t word = 0; 239 240 /* 241 * Enter EEPROM embedded programming mode. In order to 242 * access the EEPROM at all, we first have to set the 243 * EELOAD bit in the CHIPCFG2 register. 244 */ 245 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247 248 /* Select the address of the word we want to read */ 249 CSR_WRITE_1(sc, VGE_EEADDR, addr); 250 251 /* Issue read command */ 252 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253 254 /* Wait for the done bit to be set. */ 255 for (i = 0; i < VGE_TIMEOUT; i++) { 256 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) { 261 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 262 *dest = 0; 263 return; 264 } 265 266 /* Read the result */ 267 word = CSR_READ_2(sc, VGE_EERDDAT); 268 269 /* Turn off EEPROM access mode. */ 270 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 271 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 272 273 *dest = word; 274 275 return; 276} 277#endif 278 279/* 280 * Read a sequence of words from the EEPROM. 281 */ 282static void 283vge_read_eeprom(sc, dest, off, cnt, swap) 284 struct vge_softc *sc; 285 caddr_t dest; 286 int off; 287 int cnt; 288 int swap; 289{ 290 int i; 291#ifdef VGE_EEPROM 292 u_int16_t word = 0, *ptr; 293 294 for (i = 0; i < cnt; i++) { 295 vge_eeprom_getword(sc, off + i, &word); 296 ptr = (u_int16_t *)(dest + (i * 2)); 297 if (swap) 298 *ptr = ntohs(word); 299 else 300 *ptr = word; 301 } 302#else 303 for (i = 0; i < ETHER_ADDR_LEN; i++) 304 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 305#endif 306} 307 308static void 309vge_miipoll_stop(sc) 310 struct vge_softc *sc; 311{ 312 int i; 313 314 CSR_WRITE_1(sc, VGE_MIICMD, 0); 315 316 for (i = 0; i < VGE_TIMEOUT; i++) { 317 DELAY(1); 318 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 319 break; 320 } 321 322 if (i == VGE_TIMEOUT) 323 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 324 325 return; 326} 327 328static void 329vge_miipoll_start(sc) 330 struct vge_softc *sc; 331{ 332 int i; 333 334 /* First, make sure we're idle. */ 335 336 CSR_WRITE_1(sc, VGE_MIICMD, 0); 337 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 338 339 for (i = 0; i < VGE_TIMEOUT; i++) { 340 DELAY(1); 341 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 342 break; 343 } 344 345 if (i == VGE_TIMEOUT) { 346 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 347 return; 348 } 349 350 /* Now enable auto poll mode. */ 351 352 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 353 354 /* And make sure it started. */ 355 356 for (i = 0; i < VGE_TIMEOUT; i++) { 357 DELAY(1); 358 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 359 break; 360 } 361 362 if (i == VGE_TIMEOUT) 363 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 364 365 return; 366} 367 368static int 369vge_miibus_readreg(dev, phy, reg) 370 device_t dev; 371 int phy, reg; 372{ 373 struct vge_softc *sc; 374 int i; 375 u_int16_t rval = 0; 376 377 sc = device_get_softc(dev); 378 379 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 380 return(0); 381 382 VGE_LOCK(sc); 383 vge_miipoll_stop(sc); 384 385 /* Specify the register we want to read. */ 386 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 387 388 /* Issue read command. */ 389 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 390 391 /* Wait for the read command bit to self-clear. */ 392 for (i = 0; i < VGE_TIMEOUT; i++) { 393 DELAY(1); 394 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 395 break; 396 } 397 398 if (i == VGE_TIMEOUT) 399 device_printf(sc->vge_dev, "MII read timed out\n"); 400 else 401 rval = CSR_READ_2(sc, VGE_MIIDATA); 402 403 vge_miipoll_start(sc); 404 VGE_UNLOCK(sc); 405 406 return (rval); 407} 408 409static int 410vge_miibus_writereg(dev, phy, reg, data) 411 device_t dev; 412 int phy, reg, data; 413{ 414 struct vge_softc *sc; 415 int i, rval = 0; 416 417 sc = device_get_softc(dev); 418 419 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 420 return(0); 421 422 VGE_LOCK(sc); 423 vge_miipoll_stop(sc); 424 425 /* Specify the register we want to write. */ 426 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 427 428 /* Specify the data we want to write. */ 429 CSR_WRITE_2(sc, VGE_MIIDATA, data); 430 431 /* Issue write command. */ 432 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 433 434 /* Wait for the write command bit to self-clear. */ 435 for (i = 0; i < VGE_TIMEOUT; i++) { 436 DELAY(1); 437 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 438 break; 439 } 440 441 if (i == VGE_TIMEOUT) { 442 device_printf(sc->vge_dev, "MII write timed out\n"); 443 rval = EIO; 444 } 445 446 vge_miipoll_start(sc); 447 VGE_UNLOCK(sc); 448 449 return (rval); 450} 451 452static void 453vge_cam_clear(sc) 454 struct vge_softc *sc; 455{ 456 int i; 457 458 /* 459 * Turn off all the mask bits. This tells the chip 460 * that none of the entries in the CAM filter are valid. 461 * desired entries will be enabled as we fill the filter in. 462 */ 463 464 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 465 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 466 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 467 for (i = 0; i < 8; i++) 468 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 469 470 /* Clear the VLAN filter too. */ 471 472 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 473 for (i = 0; i < 8; i++) 474 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 475 476 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 477 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 478 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 479 480 sc->vge_camidx = 0; 481 482 return; 483} 484 485static int 486vge_cam_set(sc, addr) 487 struct vge_softc *sc; 488 uint8_t *addr; 489{ 490 int i, error = 0; 491 492 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 493 return(ENOSPC); 494 495 /* Select the CAM data page. */ 496 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 497 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 498 499 /* Set the filter entry we want to update and enable writing. */ 500 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 501 502 /* Write the address to the CAM registers */ 503 for (i = 0; i < ETHER_ADDR_LEN; i++) 504 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 505 506 /* Issue a write command. */ 507 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 508 509 /* Wake for it to clear. */ 510 for (i = 0; i < VGE_TIMEOUT; i++) { 511 DELAY(1); 512 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 513 break; 514 } 515 516 if (i == VGE_TIMEOUT) { 517 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 518 error = EIO; 519 goto fail; 520 } 521 522 /* Select the CAM mask page. */ 523 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 524 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 525 526 /* Set the mask bit that enables this filter. */ 527 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 528 1<<(sc->vge_camidx & 7)); 529 530 sc->vge_camidx++; 531 532fail: 533 /* Turn off access to CAM. */ 534 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 535 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 536 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 537 538 return (error); 539} 540 541#if __FreeBSD_version < 502113 542static uint32_t 543vge_mchash(addr) 544 uint8_t *addr; 545{ 546 uint32_t crc, carry; 547 int idx, bit; 548 uint8_t data; 549 550 /* Compute CRC for the address value. */ 551 crc = 0xFFFFFFFF; /* initial value */ 552 553 for (idx = 0; idx < 6; idx++) { 554 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 555 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 556 crc <<= 1; 557 if (carry) 558 crc = (crc ^ 0x04c11db6) | carry; 559 } 560 } 561 562 return(crc); 563} 564#endif 565 566/* 567 * Program the multicast filter. We use the 64-entry CAM filter 568 * for perfect filtering. If there's more than 64 multicast addresses, 569 * we use the hash filter insted. 570 */ 571static void 572vge_setmulti(sc) 573 struct vge_softc *sc; 574{ 575 struct ifnet *ifp; 576 int error = 0/*, h = 0*/; 577 struct ifmultiaddr *ifma; 578 u_int32_t h, hashes[2] = { 0, 0 }; 579 580 ifp = &sc->arpcom.ac_if; 581 582 /* First, zot all the multicast entries. */ 583 vge_cam_clear(sc); 584 CSR_WRITE_4(sc, VGE_MAR0, 0); 585 CSR_WRITE_4(sc, VGE_MAR1, 0); 586 587 /* 588 * If the user wants allmulti or promisc mode, enable reception 589 * of all multicast frames. 590 */ 591 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 592 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 593 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 594 return; 595 } 596 597 /* Now program new ones */ 598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 599 if (ifma->ifma_addr->sa_family != AF_LINK) 600 continue; 601 error = vge_cam_set(sc, 602 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 603 if (error) 604 break; 605 } 606 607 /* If there were too many addresses, use the hash filter. */ 608 if (error) { 609 vge_cam_clear(sc); 610 611 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 612 if (ifma->ifma_addr->sa_family != AF_LINK) 613 continue; 614#if __FreeBSD_version < 502113 615 h = vge_mchash(LLADDR((struct sockaddr_dl *) 616 ifma->ifma_addr)) >> 26; 617#else 618 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 619 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 620#endif 621 if (h < 32) 622 hashes[0] |= (1 << h); 623 else 624 hashes[1] |= (1 << (h - 32)); 625 } 626 627 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 628 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 629 } 630 631 return; 632} 633 634static void 635vge_reset(sc) 636 struct vge_softc *sc; 637{ 638 register int i; 639 640 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 641 642 for (i = 0; i < VGE_TIMEOUT; i++) { 643 DELAY(5); 644 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 645 break; 646 } 647 648 if (i == VGE_TIMEOUT) { 649 device_printf(sc->vge_dev, "soft reset timed out"); 650 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 651 DELAY(2000); 652 } 653 654 DELAY(5000); 655 656 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 657 658 for (i = 0; i < VGE_TIMEOUT; i++) { 659 DELAY(5); 660 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 661 break; 662 } 663 664 if (i == VGE_TIMEOUT) { 665 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 666 return; 667 } 668 669 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 670 671 return; 672} 673 674/* 675 * Probe for a VIA gigabit chip. Check the PCI vendor and device 676 * IDs against our list and return a device name if we find a match. 677 */ 678static int 679vge_probe(dev) 680 device_t dev; 681{ 682 struct vge_type *t; 683 struct vge_softc *sc; 684 685 t = vge_devs; 686 sc = device_get_softc(dev); 687 688 while (t->vge_name != NULL) { 689 if ((pci_get_vendor(dev) == t->vge_vid) && 690 (pci_get_device(dev) == t->vge_did)) { 691 device_set_desc(dev, t->vge_name); 692 return (BUS_PROBE_DEFAULT); 693 } 694 t++; 695 } 696 697 return (ENXIO); 698} 699 700static void 701vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 702 void *arg; 703 bus_dma_segment_t *segs; 704 int nseg; 705 bus_size_t mapsize; 706 int error; 707{ 708 709 struct vge_dmaload_arg *ctx; 710 struct vge_rx_desc *d = NULL; 711 712 if (error) 713 return; 714 715 ctx = arg; 716 717 /* Signal error to caller if there's too many segments */ 718 if (nseg > ctx->vge_maxsegs) { 719 ctx->vge_maxsegs = 0; 720 return; 721 } 722 723 /* 724 * Map the segment array into descriptors. 725 */ 726 727 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 728 729 /* If this descriptor is still owned by the chip, bail. */ 730 731 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 732 device_printf(ctx->sc->vge_dev, 733 "tried to map busy descriptor\n"); 734 ctx->vge_maxsegs = 0; 735 return; 736 } 737 738 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 739 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 740 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 741 d->vge_sts = 0; 742 d->vge_ctl = 0; 743 744 ctx->vge_maxsegs = 1; 745 746 return; 747} 748 749static void 750vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 751 void *arg; 752 bus_dma_segment_t *segs; 753 int nseg; 754 bus_size_t mapsize; 755 int error; 756{ 757 struct vge_dmaload_arg *ctx; 758 struct vge_tx_desc *d = NULL; 759 struct vge_tx_frag *f; 760 int i = 0; 761 762 if (error) 763 return; 764 765 ctx = arg; 766 767 /* Signal error to caller if there's too many segments */ 768 if (nseg > ctx->vge_maxsegs) { 769 ctx->vge_maxsegs = 0; 770 return; 771 } 772 773 /* Map the segment array into descriptors. */ 774 775 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 776 777 /* If this descriptor is still owned by the chip, bail. */ 778 779 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 780 ctx->vge_maxsegs = 0; 781 return; 782 } 783 784 for (i = 0; i < nseg; i++) { 785 f = &d->vge_frag[i]; 786 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 787 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 788 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 789 } 790 791 /* Argh. This chip does not autopad short frames */ 792 793 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 794 f = &d->vge_frag[i]; 795 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 796 ctx->vge_m0->m_pkthdr.len)); 797 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 798 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 799 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 800 i++; 801 } 802 803 /* 804 * When telling the chip how many segments there are, we 805 * must use nsegs + 1 instead of just nsegs. Darned if I 806 * know why. 807 */ 808 i++; 809 810 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 811 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 812 813 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 814 d->vge_ctl |= VGE_TDCTL_JUMBO; 815 816 ctx->vge_maxsegs = nseg; 817 818 return; 819} 820 821/* 822 * Map a single buffer address. 823 */ 824 825static void 826vge_dma_map_addr(arg, segs, nseg, error) 827 void *arg; 828 bus_dma_segment_t *segs; 829 int nseg; 830 int error; 831{ 832 bus_addr_t *addr; 833 834 if (error) 835 return; 836 837 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 838 addr = arg; 839 *addr = segs->ds_addr; 840 841 return; 842} 843 844static int 845vge_allocmem(dev, sc) 846 device_t dev; 847 struct vge_softc *sc; 848{ 849 int error; 850 int nseg; 851 int i; 852 853 /* 854 * Allocate map for RX mbufs. 855 */ 856 nseg = 32; 857 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 858 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 859 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 860 NULL, NULL, &sc->vge_ldata.vge_mtag); 861 if (error) { 862 device_printf(dev, "could not allocate dma tag\n"); 863 return (ENOMEM); 864 } 865 866 /* 867 * Allocate map for TX descriptor list. 868 */ 869 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 870 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 871 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 872 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 873 if (error) { 874 device_printf(dev, "could not allocate dma tag\n"); 875 return (ENOMEM); 876 } 877 878 /* Allocate DMA'able memory for the TX ring */ 879 880 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 881 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 882 &sc->vge_ldata.vge_tx_list_map); 883 if (error) 884 return (ENOMEM); 885 886 /* Load the map for the TX ring. */ 887 888 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 889 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 890 VGE_TX_LIST_SZ, vge_dma_map_addr, 891 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 892 893 /* Create DMA maps for TX buffers */ 894 895 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 896 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 897 &sc->vge_ldata.vge_tx_dmamap[i]); 898 if (error) { 899 device_printf(dev, "can't create DMA map for TX\n"); 900 return (ENOMEM); 901 } 902 } 903 904 /* 905 * Allocate map for RX descriptor list. 906 */ 907 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 908 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 909 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 910 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 911 if (error) { 912 device_printf(dev, "could not allocate dma tag\n"); 913 return (ENOMEM); 914 } 915 916 /* Allocate DMA'able memory for the RX ring */ 917 918 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 919 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 920 &sc->vge_ldata.vge_rx_list_map); 921 if (error) 922 return (ENOMEM); 923 924 /* Load the map for the RX ring. */ 925 926 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 927 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 928 VGE_TX_LIST_SZ, vge_dma_map_addr, 929 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 930 931 /* Create DMA maps for RX buffers */ 932 933 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 934 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 935 &sc->vge_ldata.vge_rx_dmamap[i]); 936 if (error) { 937 device_printf(dev, "can't create DMA map for RX\n"); 938 return (ENOMEM); 939 } 940 } 941 942 return (0); 943} 944 945/* 946 * Attach the interface. Allocate softc structures, do ifmedia 947 * setup and ethernet/BPF attach. 948 */ 949static int 950vge_attach(dev) 951 device_t dev; 952{ 953 u_char eaddr[ETHER_ADDR_LEN]; 954 struct vge_softc *sc; 955 struct ifnet *ifp; 956 int unit, error = 0, rid; 957 958 sc = device_get_softc(dev); 959 unit = device_get_unit(dev); 960 sc->vge_dev = dev; 961 962 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 963 MTX_DEF | MTX_RECURSE); 964 /* 965 * Map control/status registers. 966 */ 967 pci_enable_busmaster(dev); 968 969 rid = VGE_PCI_LOMEM; 970 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 971 0, ~0, 1, RF_ACTIVE); 972 973 if (sc->vge_res == NULL) { 974 printf ("vge%d: couldn't map ports/memory\n", unit); 975 error = ENXIO; 976 goto fail; 977 } 978 979 sc->vge_btag = rman_get_bustag(sc->vge_res); 980 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 981 982 /* Allocate interrupt */ 983 rid = 0; 984 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 985 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 986 987 if (sc->vge_irq == NULL) { 988 printf("vge%d: couldn't map interrupt\n", unit); 989 error = ENXIO; 990 goto fail; 991 } 992 993 /* Reset the adapter. */ 994 vge_reset(sc); 995 996 /* 997 * Get station address from the EEPROM. 998 */ 999 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1000 1001 sc->vge_unit = unit; 1002 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1003 1004#if __FreeBSD_version < 502113 1005 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1006#endif 1007 1008 /* 1009 * Allocate the parent bus DMA tag appropriate for PCI. 1010 */ 1011#define VGE_NSEG_NEW 32 1012 error = bus_dma_tag_create(NULL, /* parent */ 1013 1, 0, /* alignment, boundary */ 1014 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1015 BUS_SPACE_MAXADDR, /* highaddr */ 1016 NULL, NULL, /* filter, filterarg */ 1017 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1018 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1019 BUS_DMA_ALLOCNOW, /* flags */ 1020 NULL, NULL, /* lockfunc, lockarg */ 1021 &sc->vge_parent_tag); 1022 if (error) 1023 goto fail; 1024 1025 error = vge_allocmem(dev, sc); 1026 1027 if (error) 1028 goto fail; 1029 1030 /* Do MII setup */ 1031 if (mii_phy_probe(dev, &sc->vge_miibus, 1032 vge_ifmedia_upd, vge_ifmedia_sts)) { 1033 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1034 error = ENXIO; 1035 goto fail; 1036 } 1037 1038 ifp = &sc->arpcom.ac_if; 1039 ifp->if_softc = sc; 1040 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1041 ifp->if_mtu = ETHERMTU; 1042 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1043 ifp->if_ioctl = vge_ioctl; 1044 ifp->if_capabilities = IFCAP_VLAN_MTU; 1045 ifp->if_start = vge_start; 1046 ifp->if_hwassist = VGE_CSUM_FEATURES; 1047 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1048#ifdef DEVICE_POLLING 1049#ifdef IFCAP_POLLING 1050 ifp->if_capabilities |= IFCAP_POLLING; 1051#endif 1052#endif 1053 ifp->if_watchdog = vge_watchdog; 1054 ifp->if_init = vge_init; 1055 ifp->if_baudrate = 1000000000; 1056 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1057 ifp->if_capenable = ifp->if_capabilities; 1058 1059 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1060 1061 /* 1062 * Call MI attach routine. 1063 */ 1064 ether_ifattach(ifp, eaddr); 1065 1066 /* Hook interrupt last to avoid having to lock softc */ 1067 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1068 vge_intr, sc, &sc->vge_intrhand); 1069 1070 if (error) { 1071 printf("vge%d: couldn't set up irq\n", unit); 1072 ether_ifdetach(ifp); 1073 goto fail; 1074 } 1075 1076fail: 1077 if (error) 1078 vge_detach(dev); 1079 1080 return (error); 1081} 1082 1083/* 1084 * Shutdown hardware and free up resources. This can be called any 1085 * time after the mutex has been initialized. It is called in both 1086 * the error case in attach and the normal detach case so it needs 1087 * to be careful about only freeing resources that have actually been 1088 * allocated. 1089 */ 1090static int 1091vge_detach(dev) 1092 device_t dev; 1093{ 1094 struct vge_softc *sc; 1095 struct ifnet *ifp; 1096 int i; 1097 1098 sc = device_get_softc(dev); 1099 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1100 ifp = &sc->arpcom.ac_if; 1101 1102 /* These should only be active if attach succeeded */ 1103 if (device_is_attached(dev)) { 1104 vge_stop(sc); 1105 /* 1106 * Force off the IFF_UP flag here, in case someone 1107 * still had a BPF descriptor attached to this 1108 * interface. If they do, ether_ifattach() will cause 1109 * the BPF code to try and clear the promisc mode 1110 * flag, which will bubble down to vge_ioctl(), 1111 * which will try to call vge_init() again. This will 1112 * turn the NIC back on and restart the MII ticker, 1113 * which will panic the system when the kernel tries 1114 * to invoke the vge_tick() function that isn't there 1115 * anymore. 1116 */ 1117 ifp->if_flags &= ~IFF_UP; 1118 ether_ifdetach(ifp); 1119 } 1120 if (sc->vge_miibus) 1121 device_delete_child(dev, sc->vge_miibus); 1122 bus_generic_detach(dev); 1123 1124 if (sc->vge_intrhand) 1125 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1126 if (sc->vge_irq) 1127 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1128 if (sc->vge_res) 1129 bus_release_resource(dev, SYS_RES_MEMORY, 1130 VGE_PCI_LOMEM, sc->vge_res); 1131 1132 /* Unload and free the RX DMA ring memory and map */ 1133 1134 if (sc->vge_ldata.vge_rx_list_tag) { 1135 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1136 sc->vge_ldata.vge_rx_list_map); 1137 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1138 sc->vge_ldata.vge_rx_list, 1139 sc->vge_ldata.vge_rx_list_map); 1140 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1141 } 1142 1143 /* Unload and free the TX DMA ring memory and map */ 1144 1145 if (sc->vge_ldata.vge_tx_list_tag) { 1146 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1147 sc->vge_ldata.vge_tx_list_map); 1148 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1149 sc->vge_ldata.vge_tx_list, 1150 sc->vge_ldata.vge_tx_list_map); 1151 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1152 } 1153 1154 /* Destroy all the RX and TX buffer maps */ 1155 1156 if (sc->vge_ldata.vge_mtag) { 1157 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1158 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1159 sc->vge_ldata.vge_tx_dmamap[i]); 1160 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1161 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1162 sc->vge_ldata.vge_rx_dmamap[i]); 1163 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1164 } 1165 1166 if (sc->vge_parent_tag) 1167 bus_dma_tag_destroy(sc->vge_parent_tag); 1168 1169 mtx_destroy(&sc->vge_mtx); 1170 1171 return (0); 1172} 1173 1174static int 1175vge_newbuf(sc, idx, m) 1176 struct vge_softc *sc; 1177 int idx; 1178 struct mbuf *m; 1179{ 1180 struct vge_dmaload_arg arg; 1181 struct mbuf *n = NULL; 1182 int i, error; 1183 1184 if (m == NULL) { 1185 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1186 if (n == NULL) 1187 return (ENOBUFS); 1188 m = n; 1189 } else 1190 m->m_data = m->m_ext.ext_buf; 1191 1192 1193#ifdef VGE_FIXUP_RX 1194 /* 1195 * This is part of an evil trick to deal with non-x86 platforms. 1196 * The VIA chip requires RX buffers to be aligned on 32-bit 1197 * boundaries, but that will hose non-x86 machines. To get around 1198 * this, we leave some empty space at the start of each buffer 1199 * and for non-x86 hosts, we copy the buffer back two bytes 1200 * to achieve word alignment. This is slightly more efficient 1201 * than allocating a new buffer, copying the contents, and 1202 * discarding the old buffer. 1203 */ 1204 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1205 m_adj(m, VGE_ETHER_ALIGN); 1206#else 1207 m->m_len = m->m_pkthdr.len = MCLBYTES; 1208#endif 1209 1210 arg.sc = sc; 1211 arg.vge_idx = idx; 1212 arg.vge_maxsegs = 1; 1213 arg.vge_flags = 0; 1214 1215 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1216 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1217 &arg, BUS_DMA_NOWAIT); 1218 if (error || arg.vge_maxsegs != 1) { 1219 if (n != NULL) 1220 m_freem(n); 1221 return (ENOMEM); 1222 } 1223 1224 /* 1225 * Note: the manual fails to document the fact that for 1226 * proper opration, the driver needs to replentish the RX 1227 * DMA ring 4 descriptors at a time (rather than one at a 1228 * time, like most chips). We can allocate the new buffers 1229 * but we should not set the OWN bits until we're ready 1230 * to hand back 4 of them in one shot. 1231 */ 1232 1233#define VGE_RXCHUNK 4 1234 sc->vge_rx_consumed++; 1235 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1236 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1237 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1238 htole32(VGE_RDSTS_OWN); 1239 sc->vge_rx_consumed = 0; 1240 } 1241 1242 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1243 1244 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1245 sc->vge_ldata.vge_rx_dmamap[idx], 1246 BUS_DMASYNC_PREREAD); 1247 1248 return (0); 1249} 1250 1251static int 1252vge_tx_list_init(sc) 1253 struct vge_softc *sc; 1254{ 1255 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1256 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1257 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1258 1259 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1260 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1261 sc->vge_ldata.vge_tx_prodidx = 0; 1262 sc->vge_ldata.vge_tx_considx = 0; 1263 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1264 1265 return (0); 1266} 1267 1268static int 1269vge_rx_list_init(sc) 1270 struct vge_softc *sc; 1271{ 1272 int i; 1273 1274 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1275 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1276 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1277 1278 sc->vge_rx_consumed = 0; 1279 1280 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1281 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1282 return (ENOBUFS); 1283 } 1284 1285 /* Flush the RX descriptors */ 1286 1287 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1288 sc->vge_ldata.vge_rx_list_map, 1289 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1290 1291 sc->vge_ldata.vge_rx_prodidx = 0; 1292 sc->vge_rx_consumed = 0; 1293 sc->vge_head = sc->vge_tail = NULL; 1294 1295 return (0); 1296} 1297 1298#ifdef VGE_FIXUP_RX 1299static __inline void 1300vge_fixup_rx(m) 1301 struct mbuf *m; 1302{ 1303 int i; 1304 uint16_t *src, *dst; 1305 1306 src = mtod(m, uint16_t *); 1307 dst = src - 1; 1308 1309 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1310 *dst++ = *src++; 1311 1312 m->m_data -= ETHER_ALIGN; 1313 1314 return; 1315} 1316#endif 1317 1318/* 1319 * RX handler. We support the reception of jumbo frames that have 1320 * been fragmented across multiple 2K mbuf cluster buffers. 1321 */ 1322static void 1323vge_rxeof(sc) 1324 struct vge_softc *sc; 1325{ 1326 struct mbuf *m; 1327 struct ifnet *ifp; 1328 int i, total_len; 1329 int lim = 0; 1330 struct vge_rx_desc *cur_rx; 1331 u_int32_t rxstat, rxctl; 1332 1333 VGE_LOCK_ASSERT(sc); 1334 ifp = &sc->arpcom.ac_if; 1335 i = sc->vge_ldata.vge_rx_prodidx; 1336 1337 /* Invalidate the descriptor memory */ 1338 1339 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1340 sc->vge_ldata.vge_rx_list_map, 1341 BUS_DMASYNC_POSTREAD); 1342 1343 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1344 1345#ifdef DEVICE_POLLING 1346 if (ifp->if_flags & IFF_POLLING) { 1347 if (sc->rxcycles <= 0) 1348 break; 1349 sc->rxcycles--; 1350 } 1351#endif /* DEVICE_POLLING */ 1352 1353 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1354 m = sc->vge_ldata.vge_rx_mbuf[i]; 1355 total_len = VGE_RXBYTES(cur_rx); 1356 rxstat = le32toh(cur_rx->vge_sts); 1357 rxctl = le32toh(cur_rx->vge_ctl); 1358 1359 /* Invalidate the RX mbuf and unload its map */ 1360 1361 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1362 sc->vge_ldata.vge_rx_dmamap[i], 1363 BUS_DMASYNC_POSTWRITE); 1364 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1365 sc->vge_ldata.vge_rx_dmamap[i]); 1366 1367 /* 1368 * If the 'start of frame' bit is set, this indicates 1369 * either the first fragment in a multi-fragment receive, 1370 * or an intermediate fragment. Either way, we want to 1371 * accumulate the buffers. 1372 */ 1373 if (rxstat & VGE_RXPKT_SOF) { 1374 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1375 if (sc->vge_head == NULL) 1376 sc->vge_head = sc->vge_tail = m; 1377 else { 1378 m->m_flags &= ~M_PKTHDR; 1379 sc->vge_tail->m_next = m; 1380 sc->vge_tail = m; 1381 } 1382 vge_newbuf(sc, i, NULL); 1383 VGE_RX_DESC_INC(i); 1384 continue; 1385 } 1386 1387 /* 1388 * Bad/error frames will have the RXOK bit cleared. 1389 * However, there's one error case we want to allow: 1390 * if a VLAN tagged frame arrives and the chip can't 1391 * match it against the CAM filter, it considers this 1392 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1393 * We don't want to drop the frame though: our VLAN 1394 * filtering is done in software. 1395 */ 1396 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1397 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1398 ifp->if_ierrors++; 1399 /* 1400 * If this is part of a multi-fragment packet, 1401 * discard all the pieces. 1402 */ 1403 if (sc->vge_head != NULL) { 1404 m_freem(sc->vge_head); 1405 sc->vge_head = sc->vge_tail = NULL; 1406 } 1407 vge_newbuf(sc, i, m); 1408 VGE_RX_DESC_INC(i); 1409 continue; 1410 } 1411 1412 /* 1413 * If allocating a replacement mbuf fails, 1414 * reload the current one. 1415 */ 1416 1417 if (vge_newbuf(sc, i, NULL)) { 1418 ifp->if_ierrors++; 1419 if (sc->vge_head != NULL) { 1420 m_freem(sc->vge_head); 1421 sc->vge_head = sc->vge_tail = NULL; 1422 } 1423 vge_newbuf(sc, i, m); 1424 VGE_RX_DESC_INC(i); 1425 continue; 1426 } 1427 1428 VGE_RX_DESC_INC(i); 1429 1430 if (sc->vge_head != NULL) { 1431 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1432 /* 1433 * Special case: if there's 4 bytes or less 1434 * in this buffer, the mbuf can be discarded: 1435 * the last 4 bytes is the CRC, which we don't 1436 * care about anyway. 1437 */ 1438 if (m->m_len <= ETHER_CRC_LEN) { 1439 sc->vge_tail->m_len -= 1440 (ETHER_CRC_LEN - m->m_len); 1441 m_freem(m); 1442 } else { 1443 m->m_len -= ETHER_CRC_LEN; 1444 m->m_flags &= ~M_PKTHDR; 1445 sc->vge_tail->m_next = m; 1446 } 1447 m = sc->vge_head; 1448 sc->vge_head = sc->vge_tail = NULL; 1449 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1450 } else 1451 m->m_pkthdr.len = m->m_len = 1452 (total_len - ETHER_CRC_LEN); 1453 1454#ifdef VGE_FIXUP_RX 1455 vge_fixup_rx(m); 1456#endif 1457 ifp->if_ipackets++; 1458 m->m_pkthdr.rcvif = ifp; 1459 1460 /* Do RX checksumming if enabled */ 1461 if (ifp->if_capenable & IFCAP_RXCSUM) { 1462 1463 /* Check IP header checksum */ 1464 if (rxctl & VGE_RDCTL_IPPKT) 1465 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1466 if (rxctl & VGE_RDCTL_IPCSUMOK) 1467 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1468 1469 /* Check TCP/UDP checksum */ 1470 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1471 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1472 m->m_pkthdr.csum_flags |= 1473 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1474 m->m_pkthdr.csum_data = 0xffff; 1475 } 1476 } 1477 1478 if (rxstat & VGE_RDSTS_VTAG) 1479 VLAN_INPUT_TAG(ifp, m, 1480 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1481 1482 VGE_UNLOCK(sc); 1483 (*ifp->if_input)(ifp, m); 1484 VGE_LOCK(sc); 1485 1486 lim++; 1487 if (lim == VGE_RX_DESC_CNT) 1488 break; 1489 1490 } 1491 1492 /* Flush the RX DMA ring */ 1493 1494 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1495 sc->vge_ldata.vge_rx_list_map, 1496 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1497 1498 sc->vge_ldata.vge_rx_prodidx = i; 1499 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1500 1501 1502 return; 1503} 1504 1505static void 1506vge_txeof(sc) 1507 struct vge_softc *sc; 1508{ 1509 struct ifnet *ifp; 1510 u_int32_t txstat; 1511 int idx; 1512 1513 ifp = &sc->arpcom.ac_if; 1514 idx = sc->vge_ldata.vge_tx_considx; 1515 1516 /* Invalidate the TX descriptor list */ 1517 1518 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1519 sc->vge_ldata.vge_tx_list_map, 1520 BUS_DMASYNC_POSTREAD); 1521 1522 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1523 1524 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1525 if (txstat & VGE_TDSTS_OWN) 1526 break; 1527 1528 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1529 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1530 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1531 sc->vge_ldata.vge_tx_dmamap[idx]); 1532 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1533 ifp->if_collisions++; 1534 if (txstat & VGE_TDSTS_TXERR) 1535 ifp->if_oerrors++; 1536 else 1537 ifp->if_opackets++; 1538 1539 sc->vge_ldata.vge_tx_free++; 1540 VGE_TX_DESC_INC(idx); 1541 } 1542 1543 /* No changes made to the TX ring, so no flush needed */ 1544 1545 if (idx != sc->vge_ldata.vge_tx_considx) { 1546 sc->vge_ldata.vge_tx_considx = idx; 1547 ifp->if_flags &= ~IFF_OACTIVE; 1548 ifp->if_timer = 0; 1549 } 1550 1551 /* 1552 * If not all descriptors have been released reaped yet, 1553 * reload the timer so that we will eventually get another 1554 * interrupt that will cause us to re-enter this routine. 1555 * This is done in case the transmitter has gone idle. 1556 */ 1557 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1558 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1559 } 1560 1561 return; 1562} 1563 1564static void 1565vge_tick(xsc) 1566 void *xsc; 1567{ 1568 struct vge_softc *sc; 1569 struct ifnet *ifp; 1570 struct mii_data *mii; 1571 1572 sc = xsc; 1573 ifp = &sc->arpcom.ac_if; 1574 VGE_LOCK(sc); 1575 mii = device_get_softc(sc->vge_miibus); 1576 1577 mii_tick(mii); 1578 if (sc->vge_link) { 1579 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1580 sc->vge_link = 0; 1581 if_link_state_change(&sc->arpcom.ac_if, 1582 LINK_STATE_DOWN); 1583 } 1584 } else { 1585 if (mii->mii_media_status & IFM_ACTIVE && 1586 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1587 sc->vge_link = 1; 1588 if_link_state_change(&sc->arpcom.ac_if, 1589 LINK_STATE_UP); 1590#if __FreeBSD_version < 502114 1591 if (ifp->if_snd.ifq_head != NULL) 1592#else 1593 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1594#endif 1595 taskqueue_enqueue(taskqueue_swi, 1596 &sc->vge_txtask); 1597 } 1598 } 1599 1600 VGE_UNLOCK(sc); 1601 1602 return; 1603} 1604 1605#ifdef DEVICE_POLLING 1606static void 1607vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1608{ 1609 struct vge_softc *sc = ifp->if_softc; 1610 1611 VGE_LOCK(sc); 1612#ifdef IFCAP_POLLING 1613 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1614 ether_poll_deregister(ifp); 1615 cmd = POLL_DEREGISTER; 1616 } 1617#endif 1618 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1619 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1620 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1621 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1622 goto done; 1623 } 1624 1625 sc->rxcycles = count; 1626 vge_rxeof(sc); 1627 vge_txeof(sc); 1628 1629#if __FreeBSD_version < 502114 1630 if (ifp->if_snd.ifq_head != NULL) 1631#else 1632 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1633#endif 1634 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1635 1636 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1637 u_int32_t status; 1638 status = CSR_READ_4(sc, VGE_ISR); 1639 if (status == 0xFFFFFFFF) 1640 goto done; 1641 if (status) 1642 CSR_WRITE_4(sc, VGE_ISR, status); 1643 1644 /* 1645 * XXX check behaviour on receiver stalls. 1646 */ 1647 1648 if (status & VGE_ISR_TXDMA_STALL || 1649 status & VGE_ISR_RXDMA_STALL) 1650 vge_init(sc); 1651 1652 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1653 vge_rxeof(sc); 1654 ifp->if_ierrors++; 1655 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1656 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1657 } 1658 } 1659done: 1660 VGE_UNLOCK(sc); 1661} 1662#endif /* DEVICE_POLLING */ 1663 1664static void 1665vge_intr(arg) 1666 void *arg; 1667{ 1668 struct vge_softc *sc; 1669 struct ifnet *ifp; 1670 u_int32_t status; 1671 1672 sc = arg; 1673 1674 if (sc->suspended) { 1675 return; 1676 } 1677 1678 VGE_LOCK(sc); 1679 ifp = &sc->arpcom.ac_if; 1680 1681 if (!(ifp->if_flags & IFF_UP)) { 1682 VGE_UNLOCK(sc); 1683 return; 1684 } 1685 1686#ifdef DEVICE_POLLING 1687 if (ifp->if_flags & IFF_POLLING) 1688 goto done; 1689 if ( 1690#ifdef IFCAP_POLLING 1691 (ifp->if_capenable & IFCAP_POLLING) && 1692#endif 1693 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1694 CSR_WRITE_4(sc, VGE_IMR, 0); 1695 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1696 vge_poll(ifp, 0, 1); 1697 goto done; 1698 } 1699 1700#endif /* DEVICE_POLLING */ 1701 1702 /* Disable interrupts */ 1703 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1704 1705 for (;;) { 1706 1707 status = CSR_READ_4(sc, VGE_ISR); 1708 /* If the card has gone away the read returns 0xffff. */ 1709 if (status == 0xFFFFFFFF) 1710 break; 1711 1712 if (status) 1713 CSR_WRITE_4(sc, VGE_ISR, status); 1714 1715 if ((status & VGE_INTRS) == 0) 1716 break; 1717 1718 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1719 vge_rxeof(sc); 1720 1721 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1722 vge_rxeof(sc); 1723 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1724 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1725 } 1726 1727 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1728 vge_txeof(sc); 1729 1730 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1731 vge_init(sc); 1732 1733 if (status & VGE_ISR_LINKSTS) 1734 vge_tick(sc); 1735 } 1736 1737 /* Re-enable interrupts */ 1738 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1739 1740#ifdef DEVICE_POLLING 1741done: 1742#endif 1743 VGE_UNLOCK(sc); 1744 1745#if __FreeBSD_version < 502114 1746 if (ifp->if_snd.ifq_head != NULL) 1747#else 1748 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1749#endif 1750 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1751 1752 return; 1753} 1754 1755static int 1756vge_encap(sc, m_head, idx) 1757 struct vge_softc *sc; 1758 struct mbuf *m_head; 1759 int idx; 1760{ 1761 struct mbuf *m_new = NULL; 1762 struct vge_dmaload_arg arg; 1763 bus_dmamap_t map; 1764 int error; 1765 struct m_tag *mtag; 1766 1767 if (sc->vge_ldata.vge_tx_free <= 2) 1768 return (EFBIG); 1769 1770 arg.vge_flags = 0; 1771 1772 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1773 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1774 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1775 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1776 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1777 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1778 1779 arg.sc = sc; 1780 arg.vge_idx = idx; 1781 arg.vge_m0 = m_head; 1782 arg.vge_maxsegs = VGE_TX_FRAGS; 1783 1784 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1785 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1786 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1787 1788 if (error && error != EFBIG) { 1789 printf("vge%d: can't map mbuf (error %d)\n", 1790 sc->vge_unit, error); 1791 return (ENOBUFS); 1792 } 1793 1794 /* Too many segments to map, coalesce into a single mbuf */ 1795 1796 if (error || arg.vge_maxsegs == 0) { 1797 m_new = m_defrag(m_head, M_DONTWAIT); 1798 if (m_new == NULL) 1799 return (1); 1800 else 1801 m_head = m_new; 1802 1803 arg.sc = sc; 1804 arg.vge_m0 = m_head; 1805 arg.vge_idx = idx; 1806 arg.vge_maxsegs = 1; 1807 1808 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1809 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1810 if (error) { 1811 printf("vge%d: can't map mbuf (error %d)\n", 1812 sc->vge_unit, error); 1813 return (EFBIG); 1814 } 1815 } 1816 1817 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1818 sc->vge_ldata.vge_tx_free--; 1819 1820 /* 1821 * Set up hardware VLAN tagging. 1822 */ 1823 1824 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1825 if (mtag != NULL) 1826 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1827 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1828 1829 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1830 1831 return (0); 1832} 1833 1834static void 1835vge_tx_task(arg, npending) 1836 void *arg; 1837 int npending; 1838{ 1839 struct ifnet *ifp; 1840 1841 ifp = arg; 1842 vge_start(ifp); 1843 1844 return; 1845} 1846 1847/* 1848 * Main transmit routine. 1849 */ 1850 1851static void 1852vge_start(ifp) 1853 struct ifnet *ifp; 1854{ 1855 struct vge_softc *sc; 1856 struct mbuf *m_head = NULL; 1857 int idx, pidx = 0; 1858 1859 sc = ifp->if_softc; 1860 VGE_LOCK(sc); 1861 1862 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1863 VGE_UNLOCK(sc); 1864 return; 1865 } 1866 1867#if __FreeBSD_version < 502114 1868 if (ifp->if_snd.ifq_head == NULL) { 1869#else 1870 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1871#endif 1872 VGE_UNLOCK(sc); 1873 return; 1874 } 1875 1876 idx = sc->vge_ldata.vge_tx_prodidx; 1877 1878 pidx = idx - 1; 1879 if (pidx < 0) 1880 pidx = VGE_TX_DESC_CNT - 1; 1881 1882 1883 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1884#if __FreeBSD_version < 502114 1885 IF_DEQUEUE(&ifp->if_snd, m_head); 1886#else 1887 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1888#endif 1889 if (m_head == NULL) 1890 break; 1891 1892 if (vge_encap(sc, m_head, idx)) { 1893#if __FreeBSD_version >= 502114 1894 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1895#else 1896 IF_PREPEND(&ifp->if_snd, m_head); 1897#endif 1898 ifp->if_flags |= IFF_OACTIVE; 1899 break; 1900 } 1901 1902 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1903 htole16(VGE_TXDESC_Q); 1904 1905 pidx = idx; 1906 VGE_TX_DESC_INC(idx); 1907 1908 /* 1909 * If there's a BPF listener, bounce a copy of this frame 1910 * to him. 1911 */ 1912 BPF_MTAP(ifp, m_head); 1913 } 1914 1915 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1916 VGE_UNLOCK(sc); 1917 return; 1918 } 1919 1920 /* Flush the TX descriptors */ 1921 1922 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1923 sc->vge_ldata.vge_tx_list_map, 1924 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1925 1926 /* Issue a transmit command. */ 1927 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1928 1929 sc->vge_ldata.vge_tx_prodidx = idx; 1930 1931 /* 1932 * Use the countdown timer for interrupt moderation. 1933 * 'TX done' interrupts are disabled. Instead, we reset the 1934 * countdown timer, which will begin counting until it hits 1935 * the value in the SSTIMER register, and then trigger an 1936 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1937 * the timer count is reloaded. Only when the transmitter 1938 * is idle will the timer hit 0 and an interrupt fire. 1939 */ 1940 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1941 1942 VGE_UNLOCK(sc); 1943 1944 /* 1945 * Set a timeout in case the chip goes out to lunch. 1946 */ 1947 ifp->if_timer = 5; 1948 1949 return; 1950} 1951 1952static void 1953vge_init(xsc) 1954 void *xsc; 1955{ 1956 struct vge_softc *sc = xsc; 1957 struct ifnet *ifp = &sc->arpcom.ac_if; 1958 struct mii_data *mii; 1959 int i; 1960 1961 VGE_LOCK(sc); 1962 mii = device_get_softc(sc->vge_miibus); 1963 1964 /* 1965 * Cancel pending I/O and free all RX/TX buffers. 1966 */ 1967 vge_stop(sc); 1968 vge_reset(sc); 1969 1970 /* 1971 * Initialize the RX and TX descriptors and mbufs. 1972 */ 1973 1974 vge_rx_list_init(sc); 1975 vge_tx_list_init(sc); 1976 1977 /* Set our station address */ 1978 for (i = 0; i < ETHER_ADDR_LEN; i++) 1979 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1980 1981 /* 1982 * Set receive FIFO threshold. Also allow transmission and 1983 * reception of VLAN tagged frames. 1984 */ 1985 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1986 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1987 1988 /* Set DMA burst length */ 1989 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1990 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1991 1992 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1993 1994 /* Set collision backoff algorithm */ 1995 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1996 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1997 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1998 1999 /* Disable LPSEL field in priority resolution */ 2000 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2001 2002 /* 2003 * Load the addresses of the DMA queues into the chip. 2004 * Note that we only use one transmit queue. 2005 */ 2006 2007 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2008 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2009 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2010 2011 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2012 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2013 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2014 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2015 2016 /* Enable and wake up the RX descriptor queue */ 2017 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2018 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2019 2020 /* Enable the TX descriptor queue */ 2021 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2022 2023 /* Set up the receive filter -- allow large frames for VLANs. */ 2024 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2025 2026 /* If we want promiscuous mode, set the allframes bit. */ 2027 if (ifp->if_flags & IFF_PROMISC) { 2028 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2029 } 2030 2031 /* Set capture broadcast bit to capture broadcast frames. */ 2032 if (ifp->if_flags & IFF_BROADCAST) { 2033 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2034 } 2035 2036 /* Set multicast bit to capture multicast frames. */ 2037 if (ifp->if_flags & IFF_MULTICAST) { 2038 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2039 } 2040 2041 /* Init the cam filter. */ 2042 vge_cam_clear(sc); 2043 2044 /* Init the multicast filter. */ 2045 vge_setmulti(sc); 2046 2047 /* Enable flow control */ 2048 2049 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2050 2051 /* Enable jumbo frame reception (if desired) */ 2052 2053 /* Start the MAC. */ 2054 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2055 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2056 CSR_WRITE_1(sc, VGE_CRS0, 2057 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2058 2059 /* 2060 * Configure one-shot timer for microsecond 2061 * resulution and load it for 500 usecs. 2062 */ 2063 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2064 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2065 2066 /* 2067 * Configure interrupt moderation for receive. Enable 2068 * the holdoff counter and load it, and set the RX 2069 * suppression count to the number of descriptors we 2070 * want to allow before triggering an interrupt. 2071 * The holdoff timer is in units of 20 usecs. 2072 */ 2073 2074#ifdef notyet 2075 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2076 /* Select the interrupt holdoff timer page. */ 2077 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2078 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2079 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2080 2081 /* Enable use of the holdoff timer. */ 2082 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2083 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2084 2085 /* Select the RX suppression threshold page. */ 2086 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2087 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2088 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2089 2090 /* Restore the page select bits. */ 2091 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2092 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2093#endif 2094 2095#ifdef DEVICE_POLLING 2096 /* 2097 * Disable interrupts if we are polling. 2098 */ 2099 if (ifp->if_flags & IFF_POLLING) { 2100 CSR_WRITE_4(sc, VGE_IMR, 0); 2101 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2102 } else /* otherwise ... */ 2103#endif /* DEVICE_POLLING */ 2104 { 2105 /* 2106 * Enable interrupts. 2107 */ 2108 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2109 CSR_WRITE_4(sc, VGE_ISR, 0); 2110 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2111 } 2112 2113 mii_mediachg(mii); 2114 2115 ifp->if_flags |= IFF_RUNNING; 2116 ifp->if_flags &= ~IFF_OACTIVE; 2117 2118 sc->vge_if_flags = 0; 2119 sc->vge_link = 0; 2120 2121 VGE_UNLOCK(sc); 2122 2123 return; 2124} 2125 2126/* 2127 * Set media options. 2128 */ 2129static int 2130vge_ifmedia_upd(ifp) 2131 struct ifnet *ifp; 2132{ 2133 struct vge_softc *sc; 2134 struct mii_data *mii; 2135 2136 sc = ifp->if_softc; 2137 mii = device_get_softc(sc->vge_miibus); 2138 mii_mediachg(mii); 2139 2140 return (0); 2141} 2142 2143/* 2144 * Report current media status. 2145 */ 2146static void 2147vge_ifmedia_sts(ifp, ifmr) 2148 struct ifnet *ifp; 2149 struct ifmediareq *ifmr; 2150{ 2151 struct vge_softc *sc; 2152 struct mii_data *mii; 2153 2154 sc = ifp->if_softc; 2155 mii = device_get_softc(sc->vge_miibus); 2156 2157 mii_pollstat(mii); 2158 ifmr->ifm_active = mii->mii_media_active; 2159 ifmr->ifm_status = mii->mii_media_status; 2160 2161 return; 2162} 2163 2164static void 2165vge_miibus_statchg(dev) 2166 device_t dev; 2167{ 2168 struct vge_softc *sc; 2169 struct mii_data *mii; 2170 struct ifmedia_entry *ife; 2171 2172 sc = device_get_softc(dev); 2173 mii = device_get_softc(sc->vge_miibus); 2174 ife = mii->mii_media.ifm_cur; 2175 2176 /* 2177 * If the user manually selects a media mode, we need to turn 2178 * on the forced MAC mode bit in the DIAGCTL register. If the 2179 * user happens to choose a full duplex mode, we also need to 2180 * set the 'force full duplex' bit. This applies only to 2181 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2182 * mode is disabled, and in 1000baseT mode, full duplex is 2183 * always implied, so we turn on the forced mode bit but leave 2184 * the FDX bit cleared. 2185 */ 2186 2187 switch (IFM_SUBTYPE(ife->ifm_media)) { 2188 case IFM_AUTO: 2189 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2190 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2191 break; 2192 case IFM_1000_T: 2193 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2194 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2195 break; 2196 case IFM_100_TX: 2197 case IFM_10_T: 2198 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2199 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2200 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2201 } else { 2202 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2203 } 2204 break; 2205 default: 2206 device_printf(dev, "unknown media type: %x\n", 2207 IFM_SUBTYPE(ife->ifm_media)); 2208 break; 2209 } 2210 2211 return; 2212} 2213 2214static int 2215vge_ioctl(ifp, command, data) 2216 struct ifnet *ifp; 2217 u_long command; 2218 caddr_t data; 2219{ 2220 struct vge_softc *sc = ifp->if_softc; 2221 struct ifreq *ifr = (struct ifreq *) data; 2222 struct mii_data *mii; 2223 int error = 0; 2224 2225 switch (command) { 2226 case SIOCSIFMTU: 2227 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2228 error = EINVAL; 2229 ifp->if_mtu = ifr->ifr_mtu; 2230 break; 2231 case SIOCSIFFLAGS: 2232 if (ifp->if_flags & IFF_UP) { 2233 if (ifp->if_flags & IFF_RUNNING && 2234 ifp->if_flags & IFF_PROMISC && 2235 !(sc->vge_if_flags & IFF_PROMISC)) { 2236 CSR_SETBIT_1(sc, VGE_RXCTL, 2237 VGE_RXCTL_RX_PROMISC); 2238 vge_setmulti(sc); 2239 } else if (ifp->if_flags & IFF_RUNNING && 2240 !(ifp->if_flags & IFF_PROMISC) && 2241 sc->vge_if_flags & IFF_PROMISC) { 2242 CSR_CLRBIT_1(sc, VGE_RXCTL, 2243 VGE_RXCTL_RX_PROMISC); 2244 vge_setmulti(sc); 2245 } else 2246 vge_init(sc); 2247 } else { 2248 if (ifp->if_flags & IFF_RUNNING) 2249 vge_stop(sc); 2250 } 2251 sc->vge_if_flags = ifp->if_flags; 2252 break; 2253 case SIOCADDMULTI: 2254 case SIOCDELMULTI: 2255 vge_setmulti(sc); 2256 break; 2257 case SIOCGIFMEDIA: 2258 case SIOCSIFMEDIA: 2259 mii = device_get_softc(sc->vge_miibus); 2260 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2261 break; 2262 case SIOCSIFCAP: 2263#ifdef IFCAP_POLLING 2264 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2265#else 2266 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2267#endif 2268 ifp->if_capenable |= 2269#ifdef IFCAP_POLLING 2270 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2271#else 2272 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2273#endif 2274 if (ifp->if_capenable & IFCAP_TXCSUM) 2275 ifp->if_hwassist = VGE_CSUM_FEATURES; 2276 else 2277 ifp->if_hwassist = 0; 2278 if (ifp->if_flags & IFF_RUNNING) 2279 vge_init(sc); 2280 break; 2281 default: 2282 error = ether_ioctl(ifp, command, data); 2283 break; 2284 } 2285 2286 return (error); 2287} 2288 2289static void 2290vge_watchdog(ifp) 2291 struct ifnet *ifp; 2292{ 2293 struct vge_softc *sc; 2294 2295 sc = ifp->if_softc; 2296 VGE_LOCK(sc); 2297 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2298 ifp->if_oerrors++; 2299 2300 vge_txeof(sc); 2301 vge_rxeof(sc); 2302 2303 vge_init(sc); 2304 2305 VGE_UNLOCK(sc); 2306 2307 return; 2308} 2309 2310/* 2311 * Stop the adapter and free any mbufs allocated to the 2312 * RX and TX lists. 2313 */ 2314static void 2315vge_stop(sc) 2316 struct vge_softc *sc; 2317{ 2318 register int i; 2319 struct ifnet *ifp; 2320 2321 VGE_LOCK(sc); 2322 ifp = &sc->arpcom.ac_if; 2323 ifp->if_timer = 0; 2324 2325 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2326#ifdef DEVICE_POLLING 2327 ether_poll_deregister(ifp); 2328#endif /* DEVICE_POLLING */ 2329 2330 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2331 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2332 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2333 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2334 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2335 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2336 2337 if (sc->vge_head != NULL) { 2338 m_freem(sc->vge_head); 2339 sc->vge_head = sc->vge_tail = NULL; 2340 } 2341 2342 /* Free the TX list buffers. */ 2343 2344 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2345 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2346 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2347 sc->vge_ldata.vge_tx_dmamap[i]); 2348 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2349 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2350 } 2351 } 2352 2353 /* Free the RX list buffers. */ 2354 2355 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2356 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2357 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2358 sc->vge_ldata.vge_rx_dmamap[i]); 2359 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2360 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2361 } 2362 } 2363 2364 VGE_UNLOCK(sc); 2365 2366 return; 2367} 2368 2369/* 2370 * Device suspend routine. Stop the interface and save some PCI 2371 * settings in case the BIOS doesn't restore them properly on 2372 * resume. 2373 */ 2374static int 2375vge_suspend(dev) 2376 device_t dev; 2377{ 2378 struct vge_softc *sc; 2379 int i; 2380 2381 sc = device_get_softc(dev); 2382 2383 vge_stop(sc); 2384 2385 for (i = 0; i < 5; i++) 2386 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2387 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2388 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2389 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2390 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2391 2392 sc->suspended = 1; 2393 2394 return (0); 2395} 2396 2397/* 2398 * Device resume routine. Restore some PCI settings in case the BIOS 2399 * doesn't, re-enable busmastering, and restart the interface if 2400 * appropriate. 2401 */ 2402static int 2403vge_resume(dev) 2404 device_t dev; 2405{ 2406 struct vge_softc *sc; 2407 struct ifnet *ifp; 2408 int i; 2409 2410 sc = device_get_softc(dev); 2411 ifp = &sc->arpcom.ac_if; 2412 2413 /* better way to do this? */ 2414 for (i = 0; i < 5; i++) 2415 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2416 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2417 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2418 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2419 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2420 2421 /* reenable busmastering */ 2422 pci_enable_busmaster(dev); 2423 pci_enable_io(dev, SYS_RES_MEMORY); 2424 2425 /* reinitialize interface if necessary */ 2426 if (ifp->if_flags & IFF_UP) 2427 vge_init(sc); 2428 2429 sc->suspended = 0; 2430 2431 return (0); 2432} 2433 2434/* 2435 * Stop all chip I/O so that the kernel's probe routines don't 2436 * get confused by errant DMAs when rebooting. 2437 */ 2438static void 2439vge_shutdown(dev) 2440 device_t dev; 2441{ 2442 struct vge_softc *sc; 2443 2444 sc = device_get_softc(dev); 2445 2446 vge_stop(sc); 2447} 2448