if_vge.c revision 145520
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 145520 2005-04-25 18:29:42Z wpaul $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#include <sys/param.h> 84#include <sys/endian.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/module.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92#include <sys/taskqueue.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_vlan_var.h> 100 101#include <net/bpf.h> 102 103#include <machine/bus_pio.h> 104#include <machine/bus_memio.h> 105#include <machine/bus.h> 106#include <machine/resource.h> 107#include <sys/bus.h> 108#include <sys/rman.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <dev/pci/pcireg.h> 114#include <dev/pci/pcivar.h> 115 116MODULE_DEPEND(vge, pci, 1, 1, 1); 117MODULE_DEPEND(vge, ether, 1, 1, 1); 118MODULE_DEPEND(vge, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#include <dev/vge/if_vgereg.h> 124#include <dev/vge/if_vgevar.h> 125 126#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 127 128/* 129 * Various supported device vendors/types and their names. 130 */ 131static struct vge_type vge_devs[] = { 132 { VIA_VENDORID, VIA_DEVICEID_61XX, 133 "VIA Networking Gigabit Ethernet" }, 134 { 0, 0, NULL } 135}; 136 137static int vge_probe (device_t); 138static int vge_attach (device_t); 139static int vge_detach (device_t); 140 141static int vge_encap (struct vge_softc *, struct mbuf *, int); 142 143static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 144static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 145 bus_size_t, int); 146static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 147 bus_size_t, int); 148static int vge_allocmem (device_t, struct vge_softc *); 149static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 150static int vge_rx_list_init (struct vge_softc *); 151static int vge_tx_list_init (struct vge_softc *); 152#ifdef VGE_FIXUP_RX 153static __inline void vge_fixup_rx 154 (struct mbuf *); 155#endif 156static void vge_rxeof (struct vge_softc *); 157static void vge_txeof (struct vge_softc *); 158static void vge_intr (void *); 159static void vge_tick (void *); 160static void vge_tx_task (void *, int); 161static void vge_start (struct ifnet *); 162static int vge_ioctl (struct ifnet *, u_long, caddr_t); 163static void vge_init (void *); 164static void vge_stop (struct vge_softc *); 165static void vge_watchdog (struct ifnet *); 166static int vge_suspend (device_t); 167static int vge_resume (device_t); 168static void vge_shutdown (device_t); 169static int vge_ifmedia_upd (struct ifnet *); 170static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 171 172#ifdef VGE_EEPROM 173static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 174#endif 175static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 176 177static void vge_miipoll_start (struct vge_softc *); 178static void vge_miipoll_stop (struct vge_softc *); 179static int vge_miibus_readreg (device_t, int, int); 180static int vge_miibus_writereg (device_t, int, int, int); 181static void vge_miibus_statchg (device_t); 182 183static void vge_cam_clear (struct vge_softc *); 184static int vge_cam_set (struct vge_softc *, uint8_t *); 185#if __FreeBSD_version < 502113 186static uint32_t vge_mchash (uint8_t *); 187#endif 188static void vge_setmulti (struct vge_softc *); 189static void vge_reset (struct vge_softc *); 190 191#define VGE_PCI_LOIO 0x10 192#define VGE_PCI_LOMEM 0x14 193 194static device_method_t vge_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, vge_probe), 197 DEVMETHOD(device_attach, vge_attach), 198 DEVMETHOD(device_detach, vge_detach), 199 DEVMETHOD(device_suspend, vge_suspend), 200 DEVMETHOD(device_resume, vge_resume), 201 DEVMETHOD(device_shutdown, vge_shutdown), 202 203 /* bus interface */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211 212 { 0, 0 } 213}; 214 215static driver_t vge_driver = { 216 "vge", 217 vge_methods, 218 sizeof(struct vge_softc) 219}; 220 221static devclass_t vge_devclass; 222 223DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 225DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 226 227#ifdef VGE_EEPROM 228/* 229 * Read a word of data stored in the EEPROM at address 'addr.' 230 */ 231static void 232vge_eeprom_getword(sc, addr, dest) 233 struct vge_softc *sc; 234 int addr; 235 u_int16_t *dest; 236{ 237 register int i; 238 u_int16_t word = 0; 239 240 /* 241 * Enter EEPROM embedded programming mode. In order to 242 * access the EEPROM at all, we first have to set the 243 * EELOAD bit in the CHIPCFG2 register. 244 */ 245 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247 248 /* Select the address of the word we want to read */ 249 CSR_WRITE_1(sc, VGE_EEADDR, addr); 250 251 /* Issue read command */ 252 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253 254 /* Wait for the done bit to be set. */ 255 for (i = 0; i < VGE_TIMEOUT; i++) { 256 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) { 261 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 262 *dest = 0; 263 return; 264 } 265 266 /* Read the result */ 267 word = CSR_READ_2(sc, VGE_EERDDAT); 268 269 /* Turn off EEPROM access mode. */ 270 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 271 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 272 273 *dest = word; 274 275 return; 276} 277#endif 278 279/* 280 * Read a sequence of words from the EEPROM. 281 */ 282static void 283vge_read_eeprom(sc, dest, off, cnt, swap) 284 struct vge_softc *sc; 285 caddr_t dest; 286 int off; 287 int cnt; 288 int swap; 289{ 290 int i; 291#ifdef VGE_EEPROM 292 u_int16_t word = 0, *ptr; 293 294 for (i = 0; i < cnt; i++) { 295 vge_eeprom_getword(sc, off + i, &word); 296 ptr = (u_int16_t *)(dest + (i * 2)); 297 if (swap) 298 *ptr = ntohs(word); 299 else 300 *ptr = word; 301 } 302#else 303 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 304 DELAY(500); 305 for (i = 0; i < ETHER_ADDR_LEN; i++) 306 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 307#endif 308} 309 310static void 311vge_miipoll_stop(sc) 312 struct vge_softc *sc; 313{ 314 int i; 315 316 CSR_WRITE_1(sc, VGE_MIICMD, 0); 317 318 for (i = 0; i < VGE_TIMEOUT; i++) { 319 DELAY(1); 320 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 321 break; 322 } 323 324 if (i == VGE_TIMEOUT) 325 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 326 327 return; 328} 329 330static void 331vge_miipoll_start(sc) 332 struct vge_softc *sc; 333{ 334 int i; 335 336 /* First, make sure we're idle. */ 337 338 CSR_WRITE_1(sc, VGE_MIICMD, 0); 339 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 340 341 for (i = 0; i < VGE_TIMEOUT; i++) { 342 DELAY(1); 343 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 344 break; 345 } 346 347 if (i == VGE_TIMEOUT) { 348 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 349 return; 350 } 351 352 /* Now enable auto poll mode. */ 353 354 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 355 356 /* And make sure it started. */ 357 358 for (i = 0; i < VGE_TIMEOUT; i++) { 359 DELAY(1); 360 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 361 break; 362 } 363 364 if (i == VGE_TIMEOUT) 365 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 366 367 return; 368} 369 370static int 371vge_miibus_readreg(dev, phy, reg) 372 device_t dev; 373 int phy, reg; 374{ 375 struct vge_softc *sc; 376 int i; 377 u_int16_t rval = 0; 378 379 sc = device_get_softc(dev); 380 381 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 382 return(0); 383 384 VGE_LOCK(sc); 385 vge_miipoll_stop(sc); 386 387 /* Specify the register we want to read. */ 388 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 389 390 /* Issue read command. */ 391 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 392 393 /* Wait for the read command bit to self-clear. */ 394 for (i = 0; i < VGE_TIMEOUT; i++) { 395 DELAY(1); 396 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 397 break; 398 } 399 400 if (i == VGE_TIMEOUT) 401 device_printf(sc->vge_dev, "MII read timed out\n"); 402 else 403 rval = CSR_READ_2(sc, VGE_MIIDATA); 404 405 vge_miipoll_start(sc); 406 VGE_UNLOCK(sc); 407 408 return (rval); 409} 410 411static int 412vge_miibus_writereg(dev, phy, reg, data) 413 device_t dev; 414 int phy, reg, data; 415{ 416 struct vge_softc *sc; 417 int i, rval = 0; 418 419 sc = device_get_softc(dev); 420 421 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 422 return(0); 423 424 VGE_LOCK(sc); 425 vge_miipoll_stop(sc); 426 427 /* Specify the register we want to write. */ 428 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 429 430 /* Specify the data we want to write. */ 431 CSR_WRITE_2(sc, VGE_MIIDATA, data); 432 433 /* Issue write command. */ 434 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 435 436 /* Wait for the write command bit to self-clear. */ 437 for (i = 0; i < VGE_TIMEOUT; i++) { 438 DELAY(1); 439 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 440 break; 441 } 442 443 if (i == VGE_TIMEOUT) { 444 device_printf(sc->vge_dev, "MII write timed out\n"); 445 rval = EIO; 446 } 447 448 vge_miipoll_start(sc); 449 VGE_UNLOCK(sc); 450 451 return (rval); 452} 453 454static void 455vge_cam_clear(sc) 456 struct vge_softc *sc; 457{ 458 int i; 459 460 /* 461 * Turn off all the mask bits. This tells the chip 462 * that none of the entries in the CAM filter are valid. 463 * desired entries will be enabled as we fill the filter in. 464 */ 465 466 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 467 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 468 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 469 for (i = 0; i < 8; i++) 470 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 471 472 /* Clear the VLAN filter too. */ 473 474 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 475 for (i = 0; i < 8; i++) 476 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 477 478 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 479 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 480 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 481 482 sc->vge_camidx = 0; 483 484 return; 485} 486 487static int 488vge_cam_set(sc, addr) 489 struct vge_softc *sc; 490 uint8_t *addr; 491{ 492 int i, error = 0; 493 494 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 495 return(ENOSPC); 496 497 /* Select the CAM data page. */ 498 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 499 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 500 501 /* Set the filter entry we want to update and enable writing. */ 502 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 503 504 /* Write the address to the CAM registers */ 505 for (i = 0; i < ETHER_ADDR_LEN; i++) 506 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 507 508 /* Issue a write command. */ 509 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 510 511 /* Wake for it to clear. */ 512 for (i = 0; i < VGE_TIMEOUT; i++) { 513 DELAY(1); 514 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 515 break; 516 } 517 518 if (i == VGE_TIMEOUT) { 519 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 520 error = EIO; 521 goto fail; 522 } 523 524 /* Select the CAM mask page. */ 525 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 526 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 527 528 /* Set the mask bit that enables this filter. */ 529 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 530 1<<(sc->vge_camidx & 7)); 531 532 sc->vge_camidx++; 533 534fail: 535 /* Turn off access to CAM. */ 536 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 537 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 538 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 539 540 return (error); 541} 542 543#if __FreeBSD_version < 502113 544static uint32_t 545vge_mchash(addr) 546 uint8_t *addr; 547{ 548 uint32_t crc, carry; 549 int idx, bit; 550 uint8_t data; 551 552 /* Compute CRC for the address value. */ 553 crc = 0xFFFFFFFF; /* initial value */ 554 555 for (idx = 0; idx < 6; idx++) { 556 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 557 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 558 crc <<= 1; 559 if (carry) 560 crc = (crc ^ 0x04c11db6) | carry; 561 } 562 } 563 564 return(crc); 565} 566#endif 567 568/* 569 * Program the multicast filter. We use the 64-entry CAM filter 570 * for perfect filtering. If there's more than 64 multicast addresses, 571 * we use the hash filter insted. 572 */ 573static void 574vge_setmulti(sc) 575 struct vge_softc *sc; 576{ 577 struct ifnet *ifp; 578 int error = 0/*, h = 0*/; 579 struct ifmultiaddr *ifma; 580 u_int32_t h, hashes[2] = { 0, 0 }; 581 582 ifp = &sc->arpcom.ac_if; 583 584 /* First, zot all the multicast entries. */ 585 vge_cam_clear(sc); 586 CSR_WRITE_4(sc, VGE_MAR0, 0); 587 CSR_WRITE_4(sc, VGE_MAR1, 0); 588 589 /* 590 * If the user wants allmulti or promisc mode, enable reception 591 * of all multicast frames. 592 */ 593 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 594 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 595 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 596 return; 597 } 598 599 /* Now program new ones */ 600 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 601 if (ifma->ifma_addr->sa_family != AF_LINK) 602 continue; 603 error = vge_cam_set(sc, 604 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 605 if (error) 606 break; 607 } 608 609 /* If there were too many addresses, use the hash filter. */ 610 if (error) { 611 vge_cam_clear(sc); 612 613 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 614 if (ifma->ifma_addr->sa_family != AF_LINK) 615 continue; 616#if __FreeBSD_version < 502113 617 h = vge_mchash(LLADDR((struct sockaddr_dl *) 618 ifma->ifma_addr)) >> 26; 619#else 620 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 621 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 622#endif 623 if (h < 32) 624 hashes[0] |= (1 << h); 625 else 626 hashes[1] |= (1 << (h - 32)); 627 } 628 629 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 630 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 631 } 632 633 return; 634} 635 636static void 637vge_reset(sc) 638 struct vge_softc *sc; 639{ 640 register int i; 641 642 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 643 644 for (i = 0; i < VGE_TIMEOUT; i++) { 645 DELAY(5); 646 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 647 break; 648 } 649 650 if (i == VGE_TIMEOUT) { 651 device_printf(sc->vge_dev, "soft reset timed out"); 652 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 653 DELAY(2000); 654 } 655 656 DELAY(5000); 657 658 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 659 660 for (i = 0; i < VGE_TIMEOUT; i++) { 661 DELAY(5); 662 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 663 break; 664 } 665 666 if (i == VGE_TIMEOUT) { 667 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 668 return; 669 } 670 671 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 672 673 return; 674} 675 676/* 677 * Probe for a VIA gigabit chip. Check the PCI vendor and device 678 * IDs against our list and return a device name if we find a match. 679 */ 680static int 681vge_probe(dev) 682 device_t dev; 683{ 684 struct vge_type *t; 685 struct vge_softc *sc; 686 687 t = vge_devs; 688 sc = device_get_softc(dev); 689 690 while (t->vge_name != NULL) { 691 if ((pci_get_vendor(dev) == t->vge_vid) && 692 (pci_get_device(dev) == t->vge_did)) { 693 device_set_desc(dev, t->vge_name); 694 return (BUS_PROBE_DEFAULT); 695 } 696 t++; 697 } 698 699 return (ENXIO); 700} 701 702static void 703vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 704 void *arg; 705 bus_dma_segment_t *segs; 706 int nseg; 707 bus_size_t mapsize; 708 int error; 709{ 710 711 struct vge_dmaload_arg *ctx; 712 struct vge_rx_desc *d = NULL; 713 714 if (error) 715 return; 716 717 ctx = arg; 718 719 /* Signal error to caller if there's too many segments */ 720 if (nseg > ctx->vge_maxsegs) { 721 ctx->vge_maxsegs = 0; 722 return; 723 } 724 725 /* 726 * Map the segment array into descriptors. 727 */ 728 729 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 730 731 /* If this descriptor is still owned by the chip, bail. */ 732 733 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 734 device_printf(ctx->sc->vge_dev, 735 "tried to map busy descriptor\n"); 736 ctx->vge_maxsegs = 0; 737 return; 738 } 739 740 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 741 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 742 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 743 d->vge_sts = 0; 744 d->vge_ctl = 0; 745 746 ctx->vge_maxsegs = 1; 747 748 return; 749} 750 751static void 752vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 753 void *arg; 754 bus_dma_segment_t *segs; 755 int nseg; 756 bus_size_t mapsize; 757 int error; 758{ 759 struct vge_dmaload_arg *ctx; 760 struct vge_tx_desc *d = NULL; 761 struct vge_tx_frag *f; 762 int i = 0; 763 764 if (error) 765 return; 766 767 ctx = arg; 768 769 /* Signal error to caller if there's too many segments */ 770 if (nseg > ctx->vge_maxsegs) { 771 ctx->vge_maxsegs = 0; 772 return; 773 } 774 775 /* Map the segment array into descriptors. */ 776 777 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 778 779 /* If this descriptor is still owned by the chip, bail. */ 780 781 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 782 ctx->vge_maxsegs = 0; 783 return; 784 } 785 786 for (i = 0; i < nseg; i++) { 787 f = &d->vge_frag[i]; 788 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 789 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 790 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 791 } 792 793 /* Argh. This chip does not autopad short frames */ 794 795 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 796 f = &d->vge_frag[i]; 797 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 798 ctx->vge_m0->m_pkthdr.len)); 799 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 800 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 801 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 802 i++; 803 } 804 805 /* 806 * When telling the chip how many segments there are, we 807 * must use nsegs + 1 instead of just nsegs. Darned if I 808 * know why. 809 */ 810 i++; 811 812 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 813 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 814 815 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 816 d->vge_ctl |= VGE_TDCTL_JUMBO; 817 818 ctx->vge_maxsegs = nseg; 819 820 return; 821} 822 823/* 824 * Map a single buffer address. 825 */ 826 827static void 828vge_dma_map_addr(arg, segs, nseg, error) 829 void *arg; 830 bus_dma_segment_t *segs; 831 int nseg; 832 int error; 833{ 834 bus_addr_t *addr; 835 836 if (error) 837 return; 838 839 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 840 addr = arg; 841 *addr = segs->ds_addr; 842 843 return; 844} 845 846static int 847vge_allocmem(dev, sc) 848 device_t dev; 849 struct vge_softc *sc; 850{ 851 int error; 852 int nseg; 853 int i; 854 855 /* 856 * Allocate map for RX mbufs. 857 */ 858 nseg = 32; 859 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 860 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 861 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 862 NULL, NULL, &sc->vge_ldata.vge_mtag); 863 if (error) { 864 device_printf(dev, "could not allocate dma tag\n"); 865 return (ENOMEM); 866 } 867 868 /* 869 * Allocate map for TX descriptor list. 870 */ 871 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 872 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 873 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 874 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 875 if (error) { 876 device_printf(dev, "could not allocate dma tag\n"); 877 return (ENOMEM); 878 } 879 880 /* Allocate DMA'able memory for the TX ring */ 881 882 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 883 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 884 &sc->vge_ldata.vge_tx_list_map); 885 if (error) 886 return (ENOMEM); 887 888 /* Load the map for the TX ring. */ 889 890 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 891 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 892 VGE_TX_LIST_SZ, vge_dma_map_addr, 893 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 894 895 /* Create DMA maps for TX buffers */ 896 897 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 898 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 899 &sc->vge_ldata.vge_tx_dmamap[i]); 900 if (error) { 901 device_printf(dev, "can't create DMA map for TX\n"); 902 return (ENOMEM); 903 } 904 } 905 906 /* 907 * Allocate map for RX descriptor list. 908 */ 909 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 910 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 911 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 912 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 913 if (error) { 914 device_printf(dev, "could not allocate dma tag\n"); 915 return (ENOMEM); 916 } 917 918 /* Allocate DMA'able memory for the RX ring */ 919 920 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 921 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 922 &sc->vge_ldata.vge_rx_list_map); 923 if (error) 924 return (ENOMEM); 925 926 /* Load the map for the RX ring. */ 927 928 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 929 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 930 VGE_TX_LIST_SZ, vge_dma_map_addr, 931 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 932 933 /* Create DMA maps for RX buffers */ 934 935 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 936 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 937 &sc->vge_ldata.vge_rx_dmamap[i]); 938 if (error) { 939 device_printf(dev, "can't create DMA map for RX\n"); 940 return (ENOMEM); 941 } 942 } 943 944 return (0); 945} 946 947/* 948 * Attach the interface. Allocate softc structures, do ifmedia 949 * setup and ethernet/BPF attach. 950 */ 951static int 952vge_attach(dev) 953 device_t dev; 954{ 955 u_char eaddr[ETHER_ADDR_LEN]; 956 struct vge_softc *sc; 957 struct ifnet *ifp; 958 int unit, error = 0, rid; 959 960 sc = device_get_softc(dev); 961 unit = device_get_unit(dev); 962 sc->vge_dev = dev; 963 964 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 965 MTX_DEF | MTX_RECURSE); 966 /* 967 * Map control/status registers. 968 */ 969 pci_enable_busmaster(dev); 970 971 rid = VGE_PCI_LOMEM; 972 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 973 0, ~0, 1, RF_ACTIVE); 974 975 if (sc->vge_res == NULL) { 976 printf ("vge%d: couldn't map ports/memory\n", unit); 977 error = ENXIO; 978 goto fail; 979 } 980 981 sc->vge_btag = rman_get_bustag(sc->vge_res); 982 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 983 984 /* Allocate interrupt */ 985 rid = 0; 986 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 987 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 988 989 if (sc->vge_irq == NULL) { 990 printf("vge%d: couldn't map interrupt\n", unit); 991 error = ENXIO; 992 goto fail; 993 } 994 995 /* Reset the adapter. */ 996 vge_reset(sc); 997 998 /* 999 * Get station address from the EEPROM. 1000 */ 1001 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1002 1003 sc->vge_unit = unit; 1004 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1005 1006#if __FreeBSD_version < 502113 1007 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1008#endif 1009 1010 /* 1011 * Allocate the parent bus DMA tag appropriate for PCI. 1012 */ 1013#define VGE_NSEG_NEW 32 1014 error = bus_dma_tag_create(NULL, /* parent */ 1015 1, 0, /* alignment, boundary */ 1016 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1017 BUS_SPACE_MAXADDR, /* highaddr */ 1018 NULL, NULL, /* filter, filterarg */ 1019 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1020 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1021 BUS_DMA_ALLOCNOW, /* flags */ 1022 NULL, NULL, /* lockfunc, lockarg */ 1023 &sc->vge_parent_tag); 1024 if (error) 1025 goto fail; 1026 1027 error = vge_allocmem(dev, sc); 1028 1029 if (error) 1030 goto fail; 1031 1032 /* Do MII setup */ 1033 if (mii_phy_probe(dev, &sc->vge_miibus, 1034 vge_ifmedia_upd, vge_ifmedia_sts)) { 1035 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1036 error = ENXIO; 1037 goto fail; 1038 } 1039 1040 ifp = &sc->arpcom.ac_if; 1041 ifp->if_softc = sc; 1042 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1043 ifp->if_mtu = ETHERMTU; 1044 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1045 ifp->if_ioctl = vge_ioctl; 1046 ifp->if_capabilities = IFCAP_VLAN_MTU; 1047 ifp->if_start = vge_start; 1048 ifp->if_hwassist = VGE_CSUM_FEATURES; 1049 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1050#ifdef DEVICE_POLLING 1051#ifdef IFCAP_POLLING 1052 ifp->if_capabilities |= IFCAP_POLLING; 1053#endif 1054#endif 1055 ifp->if_watchdog = vge_watchdog; 1056 ifp->if_init = vge_init; 1057 ifp->if_baudrate = 1000000000; 1058 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1059 ifp->if_capenable = ifp->if_capabilities; 1060 1061 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1062 1063 /* 1064 * Call MI attach routine. 1065 */ 1066 ether_ifattach(ifp, eaddr); 1067 1068 /* Hook interrupt last to avoid having to lock softc */ 1069 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1070 vge_intr, sc, &sc->vge_intrhand); 1071 1072 if (error) { 1073 printf("vge%d: couldn't set up irq\n", unit); 1074 ether_ifdetach(ifp); 1075 goto fail; 1076 } 1077 1078fail: 1079 if (error) 1080 vge_detach(dev); 1081 1082 return (error); 1083} 1084 1085/* 1086 * Shutdown hardware and free up resources. This can be called any 1087 * time after the mutex has been initialized. It is called in both 1088 * the error case in attach and the normal detach case so it needs 1089 * to be careful about only freeing resources that have actually been 1090 * allocated. 1091 */ 1092static int 1093vge_detach(dev) 1094 device_t dev; 1095{ 1096 struct vge_softc *sc; 1097 struct ifnet *ifp; 1098 int i; 1099 1100 sc = device_get_softc(dev); 1101 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1102 ifp = &sc->arpcom.ac_if; 1103 1104 /* These should only be active if attach succeeded */ 1105 if (device_is_attached(dev)) { 1106 vge_stop(sc); 1107 /* 1108 * Force off the IFF_UP flag here, in case someone 1109 * still had a BPF descriptor attached to this 1110 * interface. If they do, ether_ifattach() will cause 1111 * the BPF code to try and clear the promisc mode 1112 * flag, which will bubble down to vge_ioctl(), 1113 * which will try to call vge_init() again. This will 1114 * turn the NIC back on and restart the MII ticker, 1115 * which will panic the system when the kernel tries 1116 * to invoke the vge_tick() function that isn't there 1117 * anymore. 1118 */ 1119 ifp->if_flags &= ~IFF_UP; 1120 ether_ifdetach(ifp); 1121 } 1122 if (sc->vge_miibus) 1123 device_delete_child(dev, sc->vge_miibus); 1124 bus_generic_detach(dev); 1125 1126 if (sc->vge_intrhand) 1127 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1128 if (sc->vge_irq) 1129 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1130 if (sc->vge_res) 1131 bus_release_resource(dev, SYS_RES_MEMORY, 1132 VGE_PCI_LOMEM, sc->vge_res); 1133 1134 /* Unload and free the RX DMA ring memory and map */ 1135 1136 if (sc->vge_ldata.vge_rx_list_tag) { 1137 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1138 sc->vge_ldata.vge_rx_list_map); 1139 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1140 sc->vge_ldata.vge_rx_list, 1141 sc->vge_ldata.vge_rx_list_map); 1142 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1143 } 1144 1145 /* Unload and free the TX DMA ring memory and map */ 1146 1147 if (sc->vge_ldata.vge_tx_list_tag) { 1148 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1149 sc->vge_ldata.vge_tx_list_map); 1150 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1151 sc->vge_ldata.vge_tx_list, 1152 sc->vge_ldata.vge_tx_list_map); 1153 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1154 } 1155 1156 /* Destroy all the RX and TX buffer maps */ 1157 1158 if (sc->vge_ldata.vge_mtag) { 1159 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1160 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1161 sc->vge_ldata.vge_tx_dmamap[i]); 1162 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1163 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1164 sc->vge_ldata.vge_rx_dmamap[i]); 1165 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1166 } 1167 1168 if (sc->vge_parent_tag) 1169 bus_dma_tag_destroy(sc->vge_parent_tag); 1170 1171 mtx_destroy(&sc->vge_mtx); 1172 1173 return (0); 1174} 1175 1176static int 1177vge_newbuf(sc, idx, m) 1178 struct vge_softc *sc; 1179 int idx; 1180 struct mbuf *m; 1181{ 1182 struct vge_dmaload_arg arg; 1183 struct mbuf *n = NULL; 1184 int i, error; 1185 1186 if (m == NULL) { 1187 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1188 if (n == NULL) 1189 return (ENOBUFS); 1190 m = n; 1191 } else 1192 m->m_data = m->m_ext.ext_buf; 1193 1194 1195#ifdef VGE_FIXUP_RX 1196 /* 1197 * This is part of an evil trick to deal with non-x86 platforms. 1198 * The VIA chip requires RX buffers to be aligned on 32-bit 1199 * boundaries, but that will hose non-x86 machines. To get around 1200 * this, we leave some empty space at the start of each buffer 1201 * and for non-x86 hosts, we copy the buffer back two bytes 1202 * to achieve word alignment. This is slightly more efficient 1203 * than allocating a new buffer, copying the contents, and 1204 * discarding the old buffer. 1205 */ 1206 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1207 m_adj(m, VGE_ETHER_ALIGN); 1208#else 1209 m->m_len = m->m_pkthdr.len = MCLBYTES; 1210#endif 1211 1212 arg.sc = sc; 1213 arg.vge_idx = idx; 1214 arg.vge_maxsegs = 1; 1215 arg.vge_flags = 0; 1216 1217 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1218 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1219 &arg, BUS_DMA_NOWAIT); 1220 if (error || arg.vge_maxsegs != 1) { 1221 if (n != NULL) 1222 m_freem(n); 1223 return (ENOMEM); 1224 } 1225 1226 /* 1227 * Note: the manual fails to document the fact that for 1228 * proper opration, the driver needs to replentish the RX 1229 * DMA ring 4 descriptors at a time (rather than one at a 1230 * time, like most chips). We can allocate the new buffers 1231 * but we should not set the OWN bits until we're ready 1232 * to hand back 4 of them in one shot. 1233 */ 1234 1235#define VGE_RXCHUNK 4 1236 sc->vge_rx_consumed++; 1237 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1238 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1239 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1240 htole32(VGE_RDSTS_OWN); 1241 sc->vge_rx_consumed = 0; 1242 } 1243 1244 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1245 1246 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1247 sc->vge_ldata.vge_rx_dmamap[idx], 1248 BUS_DMASYNC_PREREAD); 1249 1250 return (0); 1251} 1252 1253static int 1254vge_tx_list_init(sc) 1255 struct vge_softc *sc; 1256{ 1257 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1258 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1259 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1260 1261 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1262 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1263 sc->vge_ldata.vge_tx_prodidx = 0; 1264 sc->vge_ldata.vge_tx_considx = 0; 1265 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1266 1267 return (0); 1268} 1269 1270static int 1271vge_rx_list_init(sc) 1272 struct vge_softc *sc; 1273{ 1274 int i; 1275 1276 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1277 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1278 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1279 1280 sc->vge_rx_consumed = 0; 1281 1282 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1283 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1284 return (ENOBUFS); 1285 } 1286 1287 /* Flush the RX descriptors */ 1288 1289 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1290 sc->vge_ldata.vge_rx_list_map, 1291 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1292 1293 sc->vge_ldata.vge_rx_prodidx = 0; 1294 sc->vge_rx_consumed = 0; 1295 sc->vge_head = sc->vge_tail = NULL; 1296 1297 return (0); 1298} 1299 1300#ifdef VGE_FIXUP_RX 1301static __inline void 1302vge_fixup_rx(m) 1303 struct mbuf *m; 1304{ 1305 int i; 1306 uint16_t *src, *dst; 1307 1308 src = mtod(m, uint16_t *); 1309 dst = src - 1; 1310 1311 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1312 *dst++ = *src++; 1313 1314 m->m_data -= ETHER_ALIGN; 1315 1316 return; 1317} 1318#endif 1319 1320/* 1321 * RX handler. We support the reception of jumbo frames that have 1322 * been fragmented across multiple 2K mbuf cluster buffers. 1323 */ 1324static void 1325vge_rxeof(sc) 1326 struct vge_softc *sc; 1327{ 1328 struct mbuf *m; 1329 struct ifnet *ifp; 1330 int i, total_len; 1331 int lim = 0; 1332 struct vge_rx_desc *cur_rx; 1333 u_int32_t rxstat, rxctl; 1334 1335 VGE_LOCK_ASSERT(sc); 1336 ifp = &sc->arpcom.ac_if; 1337 i = sc->vge_ldata.vge_rx_prodidx; 1338 1339 /* Invalidate the descriptor memory */ 1340 1341 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1342 sc->vge_ldata.vge_rx_list_map, 1343 BUS_DMASYNC_POSTREAD); 1344 1345 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1346 1347#ifdef DEVICE_POLLING 1348 if (ifp->if_flags & IFF_POLLING) { 1349 if (sc->rxcycles <= 0) 1350 break; 1351 sc->rxcycles--; 1352 } 1353#endif /* DEVICE_POLLING */ 1354 1355 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1356 m = sc->vge_ldata.vge_rx_mbuf[i]; 1357 total_len = VGE_RXBYTES(cur_rx); 1358 rxstat = le32toh(cur_rx->vge_sts); 1359 rxctl = le32toh(cur_rx->vge_ctl); 1360 1361 /* Invalidate the RX mbuf and unload its map */ 1362 1363 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1364 sc->vge_ldata.vge_rx_dmamap[i], 1365 BUS_DMASYNC_POSTWRITE); 1366 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1367 sc->vge_ldata.vge_rx_dmamap[i]); 1368 1369 /* 1370 * If the 'start of frame' bit is set, this indicates 1371 * either the first fragment in a multi-fragment receive, 1372 * or an intermediate fragment. Either way, we want to 1373 * accumulate the buffers. 1374 */ 1375 if (rxstat & VGE_RXPKT_SOF) { 1376 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1377 if (sc->vge_head == NULL) 1378 sc->vge_head = sc->vge_tail = m; 1379 else { 1380 m->m_flags &= ~M_PKTHDR; 1381 sc->vge_tail->m_next = m; 1382 sc->vge_tail = m; 1383 } 1384 vge_newbuf(sc, i, NULL); 1385 VGE_RX_DESC_INC(i); 1386 continue; 1387 } 1388 1389 /* 1390 * Bad/error frames will have the RXOK bit cleared. 1391 * However, there's one error case we want to allow: 1392 * if a VLAN tagged frame arrives and the chip can't 1393 * match it against the CAM filter, it considers this 1394 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1395 * We don't want to drop the frame though: our VLAN 1396 * filtering is done in software. 1397 */ 1398 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1399 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1400 ifp->if_ierrors++; 1401 /* 1402 * If this is part of a multi-fragment packet, 1403 * discard all the pieces. 1404 */ 1405 if (sc->vge_head != NULL) { 1406 m_freem(sc->vge_head); 1407 sc->vge_head = sc->vge_tail = NULL; 1408 } 1409 vge_newbuf(sc, i, m); 1410 VGE_RX_DESC_INC(i); 1411 continue; 1412 } 1413 1414 /* 1415 * If allocating a replacement mbuf fails, 1416 * reload the current one. 1417 */ 1418 1419 if (vge_newbuf(sc, i, NULL)) { 1420 ifp->if_ierrors++; 1421 if (sc->vge_head != NULL) { 1422 m_freem(sc->vge_head); 1423 sc->vge_head = sc->vge_tail = NULL; 1424 } 1425 vge_newbuf(sc, i, m); 1426 VGE_RX_DESC_INC(i); 1427 continue; 1428 } 1429 1430 VGE_RX_DESC_INC(i); 1431 1432 if (sc->vge_head != NULL) { 1433 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1434 /* 1435 * Special case: if there's 4 bytes or less 1436 * in this buffer, the mbuf can be discarded: 1437 * the last 4 bytes is the CRC, which we don't 1438 * care about anyway. 1439 */ 1440 if (m->m_len <= ETHER_CRC_LEN) { 1441 sc->vge_tail->m_len -= 1442 (ETHER_CRC_LEN - m->m_len); 1443 m_freem(m); 1444 } else { 1445 m->m_len -= ETHER_CRC_LEN; 1446 m->m_flags &= ~M_PKTHDR; 1447 sc->vge_tail->m_next = m; 1448 } 1449 m = sc->vge_head; 1450 sc->vge_head = sc->vge_tail = NULL; 1451 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1452 } else 1453 m->m_pkthdr.len = m->m_len = 1454 (total_len - ETHER_CRC_LEN); 1455 1456#ifdef VGE_FIXUP_RX 1457 vge_fixup_rx(m); 1458#endif 1459 ifp->if_ipackets++; 1460 m->m_pkthdr.rcvif = ifp; 1461 1462 /* Do RX checksumming if enabled */ 1463 if (ifp->if_capenable & IFCAP_RXCSUM) { 1464 1465 /* Check IP header checksum */ 1466 if (rxctl & VGE_RDCTL_IPPKT) 1467 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1468 if (rxctl & VGE_RDCTL_IPCSUMOK) 1469 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1470 1471 /* Check TCP/UDP checksum */ 1472 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1473 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1474 m->m_pkthdr.csum_flags |= 1475 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1476 m->m_pkthdr.csum_data = 0xffff; 1477 } 1478 } 1479 1480 if (rxstat & VGE_RDSTS_VTAG) 1481 VLAN_INPUT_TAG(ifp, m, 1482 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1483 1484 VGE_UNLOCK(sc); 1485 (*ifp->if_input)(ifp, m); 1486 VGE_LOCK(sc); 1487 1488 lim++; 1489 if (lim == VGE_RX_DESC_CNT) 1490 break; 1491 1492 } 1493 1494 /* Flush the RX DMA ring */ 1495 1496 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1497 sc->vge_ldata.vge_rx_list_map, 1498 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1499 1500 sc->vge_ldata.vge_rx_prodidx = i; 1501 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1502 1503 1504 return; 1505} 1506 1507static void 1508vge_txeof(sc) 1509 struct vge_softc *sc; 1510{ 1511 struct ifnet *ifp; 1512 u_int32_t txstat; 1513 int idx; 1514 1515 ifp = &sc->arpcom.ac_if; 1516 idx = sc->vge_ldata.vge_tx_considx; 1517 1518 /* Invalidate the TX descriptor list */ 1519 1520 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1521 sc->vge_ldata.vge_tx_list_map, 1522 BUS_DMASYNC_POSTREAD); 1523 1524 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1525 1526 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1527 if (txstat & VGE_TDSTS_OWN) 1528 break; 1529 1530 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1531 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1532 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1533 sc->vge_ldata.vge_tx_dmamap[idx]); 1534 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1535 ifp->if_collisions++; 1536 if (txstat & VGE_TDSTS_TXERR) 1537 ifp->if_oerrors++; 1538 else 1539 ifp->if_opackets++; 1540 1541 sc->vge_ldata.vge_tx_free++; 1542 VGE_TX_DESC_INC(idx); 1543 } 1544 1545 /* No changes made to the TX ring, so no flush needed */ 1546 1547 if (idx != sc->vge_ldata.vge_tx_considx) { 1548 sc->vge_ldata.vge_tx_considx = idx; 1549 ifp->if_flags &= ~IFF_OACTIVE; 1550 ifp->if_timer = 0; 1551 } 1552 1553 /* 1554 * If not all descriptors have been released reaped yet, 1555 * reload the timer so that we will eventually get another 1556 * interrupt that will cause us to re-enter this routine. 1557 * This is done in case the transmitter has gone idle. 1558 */ 1559 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1560 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1561 } 1562 1563 return; 1564} 1565 1566static void 1567vge_tick(xsc) 1568 void *xsc; 1569{ 1570 struct vge_softc *sc; 1571 struct ifnet *ifp; 1572 struct mii_data *mii; 1573 1574 sc = xsc; 1575 ifp = &sc->arpcom.ac_if; 1576 VGE_LOCK(sc); 1577 mii = device_get_softc(sc->vge_miibus); 1578 1579 mii_tick(mii); 1580 if (sc->vge_link) { 1581 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1582 sc->vge_link = 0; 1583 if_link_state_change(&sc->arpcom.ac_if, 1584 LINK_STATE_UP); 1585 } 1586 } else { 1587 if (mii->mii_media_status & IFM_ACTIVE && 1588 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1589 sc->vge_link = 1; 1590 if_link_state_change(&sc->arpcom.ac_if, 1591 LINK_STATE_DOWN); 1592#if __FreeBSD_version < 502114 1593 if (ifp->if_snd.ifq_head != NULL) 1594#else 1595 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1596#endif 1597 taskqueue_enqueue(taskqueue_swi, 1598 &sc->vge_txtask); 1599 } 1600 } 1601 1602 VGE_UNLOCK(sc); 1603 1604 return; 1605} 1606 1607#ifdef DEVICE_POLLING 1608static void 1609vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1610{ 1611 struct vge_softc *sc = ifp->if_softc; 1612 1613 VGE_LOCK(sc); 1614#ifdef IFCAP_POLLING 1615 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1616 ether_poll_deregister(ifp); 1617 cmd = POLL_DEREGISTER; 1618 } 1619#endif 1620 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1621 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1622 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1623 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1624 goto done; 1625 } 1626 1627 sc->rxcycles = count; 1628 vge_rxeof(sc); 1629 vge_txeof(sc); 1630 1631#if __FreeBSD_version < 502114 1632 if (ifp->if_snd.ifq_head != NULL) 1633#else 1634 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1635#endif 1636 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1637 1638 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1639 u_int32_t status; 1640 status = CSR_READ_4(sc, VGE_ISR); 1641 if (status == 0xFFFFFFFF) 1642 goto done; 1643 if (status) 1644 CSR_WRITE_4(sc, VGE_ISR, status); 1645 1646 /* 1647 * XXX check behaviour on receiver stalls. 1648 */ 1649 1650 if (status & VGE_ISR_TXDMA_STALL || 1651 status & VGE_ISR_RXDMA_STALL) 1652 vge_init(sc); 1653 1654 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1655 vge_rxeof(sc); 1656 ifp->if_ierrors++; 1657 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1658 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1659 } 1660 } 1661done: 1662 VGE_UNLOCK(sc); 1663} 1664#endif /* DEVICE_POLLING */ 1665 1666static void 1667vge_intr(arg) 1668 void *arg; 1669{ 1670 struct vge_softc *sc; 1671 struct ifnet *ifp; 1672 u_int32_t status; 1673 1674 sc = arg; 1675 1676 if (sc->suspended) { 1677 return; 1678 } 1679 1680 VGE_LOCK(sc); 1681 ifp = &sc->arpcom.ac_if; 1682 1683 if (!(ifp->if_flags & IFF_UP)) { 1684 VGE_UNLOCK(sc); 1685 return; 1686 } 1687 1688#ifdef DEVICE_POLLING 1689 if (ifp->if_flags & IFF_POLLING) 1690 goto done; 1691 if ( 1692#ifdef IFCAP_POLLING 1693 (ifp->if_capenable & IFCAP_POLLING) && 1694#endif 1695 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1696 CSR_WRITE_4(sc, VGE_IMR, 0); 1697 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1698 vge_poll(ifp, 0, 1); 1699 goto done; 1700 } 1701 1702#endif /* DEVICE_POLLING */ 1703 1704 /* Disable interrupts */ 1705 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1706 1707 for (;;) { 1708 1709 status = CSR_READ_4(sc, VGE_ISR); 1710 /* If the card has gone away the read returns 0xffff. */ 1711 if (status == 0xFFFFFFFF) 1712 break; 1713 1714 if (status) 1715 CSR_WRITE_4(sc, VGE_ISR, status); 1716 1717 if ((status & VGE_INTRS) == 0) 1718 break; 1719 1720 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1721 vge_rxeof(sc); 1722 1723 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1724 vge_rxeof(sc); 1725 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1726 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1727 } 1728 1729 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1730 vge_txeof(sc); 1731 1732 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1733 vge_init(sc); 1734 1735 if (status & VGE_ISR_LINKSTS) 1736 vge_tick(sc); 1737 } 1738 1739 /* Re-enable interrupts */ 1740 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1741 1742#ifdef DEVICE_POLLING 1743done: 1744#endif 1745 VGE_UNLOCK(sc); 1746 1747#if __FreeBSD_version < 502114 1748 if (ifp->if_snd.ifq_head != NULL) 1749#else 1750 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1751#endif 1752 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1753 1754 return; 1755} 1756 1757static int 1758vge_encap(sc, m_head, idx) 1759 struct vge_softc *sc; 1760 struct mbuf *m_head; 1761 int idx; 1762{ 1763 struct mbuf *m_new = NULL; 1764 struct vge_dmaload_arg arg; 1765 bus_dmamap_t map; 1766 int error; 1767 struct m_tag *mtag; 1768 1769 if (sc->vge_ldata.vge_tx_free <= 2) 1770 return (EFBIG); 1771 1772 arg.vge_flags = 0; 1773 1774 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1775 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1776 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1777 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1778 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1779 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1780 1781 arg.sc = sc; 1782 arg.vge_idx = idx; 1783 arg.vge_m0 = m_head; 1784 arg.vge_maxsegs = VGE_TX_FRAGS; 1785 1786 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1787 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1788 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1789 1790 if (error && error != EFBIG) { 1791 printf("vge%d: can't map mbuf (error %d)\n", 1792 sc->vge_unit, error); 1793 return (ENOBUFS); 1794 } 1795 1796 /* Too many segments to map, coalesce into a single mbuf */ 1797 1798 if (error || arg.vge_maxsegs == 0) { 1799 m_new = m_defrag(m_head, M_DONTWAIT); 1800 if (m_new == NULL) 1801 return (1); 1802 else 1803 m_head = m_new; 1804 1805 arg.sc = sc; 1806 arg.vge_m0 = m_head; 1807 arg.vge_idx = idx; 1808 arg.vge_maxsegs = 1; 1809 1810 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1811 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1812 if (error) { 1813 printf("vge%d: can't map mbuf (error %d)\n", 1814 sc->vge_unit, error); 1815 return (EFBIG); 1816 } 1817 } 1818 1819 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1820 sc->vge_ldata.vge_tx_free--; 1821 1822 /* 1823 * Set up hardware VLAN tagging. 1824 */ 1825 1826 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1827 if (mtag != NULL) 1828 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1829 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1830 1831 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1832 1833 return (0); 1834} 1835 1836static void 1837vge_tx_task(arg, npending) 1838 void *arg; 1839 int npending; 1840{ 1841 struct ifnet *ifp; 1842 1843 ifp = arg; 1844 vge_start(ifp); 1845 1846 return; 1847} 1848 1849/* 1850 * Main transmit routine. 1851 */ 1852 1853static void 1854vge_start(ifp) 1855 struct ifnet *ifp; 1856{ 1857 struct vge_softc *sc; 1858 struct mbuf *m_head = NULL; 1859 int idx, pidx = 0; 1860 1861 sc = ifp->if_softc; 1862 VGE_LOCK(sc); 1863 1864 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1865 VGE_UNLOCK(sc); 1866 return; 1867 } 1868 1869#if __FreeBSD_version < 502114 1870 if (ifp->if_snd.ifq_head == NULL) { 1871#else 1872 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1873#endif 1874 VGE_UNLOCK(sc); 1875 return; 1876 } 1877 1878 idx = sc->vge_ldata.vge_tx_prodidx; 1879 1880 pidx = idx - 1; 1881 if (pidx < 0) 1882 pidx = VGE_TX_DESC_CNT - 1; 1883 1884 1885 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1886#if __FreeBSD_version < 502114 1887 IF_DEQUEUE(&ifp->if_snd, m_head); 1888#else 1889 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1890#endif 1891 if (m_head == NULL) 1892 break; 1893 1894 if (vge_encap(sc, m_head, idx)) { 1895#if __FreeBSD_version >= 502114 1896 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1897#else 1898 IF_PREPEND(&ifp->if_snd, m_head); 1899#endif 1900 ifp->if_flags |= IFF_OACTIVE; 1901 break; 1902 } 1903 1904 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1905 htole16(VGE_TXDESC_Q); 1906 1907 pidx = idx; 1908 VGE_TX_DESC_INC(idx); 1909 1910 /* 1911 * If there's a BPF listener, bounce a copy of this frame 1912 * to him. 1913 */ 1914 BPF_MTAP(ifp, m_head); 1915 } 1916 1917 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1918 VGE_UNLOCK(sc); 1919 return; 1920 } 1921 1922 /* Flush the TX descriptors */ 1923 1924 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1925 sc->vge_ldata.vge_tx_list_map, 1926 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1927 1928 /* Issue a transmit command. */ 1929 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1930 1931 sc->vge_ldata.vge_tx_prodidx = idx; 1932 1933 /* 1934 * Use the countdown timer for interrupt moderation. 1935 * 'TX done' interrupts are disabled. Instead, we reset the 1936 * countdown timer, which will begin counting until it hits 1937 * the value in the SSTIMER register, and then trigger an 1938 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1939 * the timer count is reloaded. Only when the transmitter 1940 * is idle will the timer hit 0 and an interrupt fire. 1941 */ 1942 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1943 1944 VGE_UNLOCK(sc); 1945 1946 /* 1947 * Set a timeout in case the chip goes out to lunch. 1948 */ 1949 ifp->if_timer = 5; 1950 1951 return; 1952} 1953 1954static void 1955vge_init(xsc) 1956 void *xsc; 1957{ 1958 struct vge_softc *sc = xsc; 1959 struct ifnet *ifp = &sc->arpcom.ac_if; 1960 struct mii_data *mii; 1961 int i; 1962 1963 VGE_LOCK(sc); 1964 mii = device_get_softc(sc->vge_miibus); 1965 1966 /* 1967 * Cancel pending I/O and free all RX/TX buffers. 1968 */ 1969 vge_stop(sc); 1970 vge_reset(sc); 1971 1972 /* 1973 * Initialize the RX and TX descriptors and mbufs. 1974 */ 1975 1976 vge_rx_list_init(sc); 1977 vge_tx_list_init(sc); 1978 1979 /* Set our station address */ 1980 for (i = 0; i < ETHER_ADDR_LEN; i++) 1981 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1982 1983 /* 1984 * Set receive FIFO threshold. Also allow transmission and 1985 * reception of VLAN tagged frames. 1986 */ 1987 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1988 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1989 1990 /* Set DMA burst length */ 1991 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1992 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1993 1994 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1995 1996 /* Set collision backoff algorithm */ 1997 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1998 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1999 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2000 2001 /* Disable LPSEL field in priority resolution */ 2002 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2003 2004 /* 2005 * Load the addresses of the DMA queues into the chip. 2006 * Note that we only use one transmit queue. 2007 */ 2008 2009 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2010 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2011 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2012 2013 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2014 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2015 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2016 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2017 2018 /* Enable and wake up the RX descriptor queue */ 2019 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2020 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2021 2022 /* Enable the TX descriptor queue */ 2023 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2024 2025 /* Set up the receive filter -- allow large frames for VLANs. */ 2026 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2027 2028 /* If we want promiscuous mode, set the allframes bit. */ 2029 if (ifp->if_flags & IFF_PROMISC) { 2030 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2031 } 2032 2033 /* Set capture broadcast bit to capture broadcast frames. */ 2034 if (ifp->if_flags & IFF_BROADCAST) { 2035 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2036 } 2037 2038 /* Set multicast bit to capture multicast frames. */ 2039 if (ifp->if_flags & IFF_MULTICAST) { 2040 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2041 } 2042 2043 /* Init the cam filter. */ 2044 vge_cam_clear(sc); 2045 2046 /* Init the multicast filter. */ 2047 vge_setmulti(sc); 2048 2049 /* Enable flow control */ 2050 2051 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2052 2053 /* Enable jumbo frame reception (if desired) */ 2054 2055 /* Start the MAC. */ 2056 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2057 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2058 CSR_WRITE_1(sc, VGE_CRS0, 2059 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2060 2061 /* 2062 * Configure one-shot timer for microsecond 2063 * resulution and load it for 500 usecs. 2064 */ 2065 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2066 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2067 2068 /* 2069 * Configure interrupt moderation for receive. Enable 2070 * the holdoff counter and load it, and set the RX 2071 * suppression count to the number of descriptors we 2072 * want to allow before triggering an interrupt. 2073 * The holdoff timer is in units of 20 usecs. 2074 */ 2075 2076#ifdef notyet 2077 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2078 /* Select the interrupt holdoff timer page. */ 2079 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2080 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2081 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2082 2083 /* Enable use of the holdoff timer. */ 2084 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2085 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2086 2087 /* Select the RX suppression threshold page. */ 2088 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2089 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2090 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2091 2092 /* Restore the page select bits. */ 2093 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2094 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2095#endif 2096 2097#ifdef DEVICE_POLLING 2098 /* 2099 * Disable interrupts if we are polling. 2100 */ 2101 if (ifp->if_flags & IFF_POLLING) { 2102 CSR_WRITE_4(sc, VGE_IMR, 0); 2103 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2104 } else /* otherwise ... */ 2105#endif /* DEVICE_POLLING */ 2106 { 2107 /* 2108 * Enable interrupts. 2109 */ 2110 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2111 CSR_WRITE_4(sc, VGE_ISR, 0); 2112 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2113 } 2114 2115 mii_mediachg(mii); 2116 2117 ifp->if_flags |= IFF_RUNNING; 2118 ifp->if_flags &= ~IFF_OACTIVE; 2119 2120 sc->vge_if_flags = 0; 2121 sc->vge_link = 0; 2122 2123 VGE_UNLOCK(sc); 2124 2125 return; 2126} 2127 2128/* 2129 * Set media options. 2130 */ 2131static int 2132vge_ifmedia_upd(ifp) 2133 struct ifnet *ifp; 2134{ 2135 struct vge_softc *sc; 2136 struct mii_data *mii; 2137 2138 sc = ifp->if_softc; 2139 mii = device_get_softc(sc->vge_miibus); 2140 mii_mediachg(mii); 2141 2142 return (0); 2143} 2144 2145/* 2146 * Report current media status. 2147 */ 2148static void 2149vge_ifmedia_sts(ifp, ifmr) 2150 struct ifnet *ifp; 2151 struct ifmediareq *ifmr; 2152{ 2153 struct vge_softc *sc; 2154 struct mii_data *mii; 2155 2156 sc = ifp->if_softc; 2157 mii = device_get_softc(sc->vge_miibus); 2158 2159 mii_pollstat(mii); 2160 ifmr->ifm_active = mii->mii_media_active; 2161 ifmr->ifm_status = mii->mii_media_status; 2162 2163 return; 2164} 2165 2166static void 2167vge_miibus_statchg(dev) 2168 device_t dev; 2169{ 2170 struct vge_softc *sc; 2171 struct mii_data *mii; 2172 struct ifmedia_entry *ife; 2173 2174 sc = device_get_softc(dev); 2175 mii = device_get_softc(sc->vge_miibus); 2176 ife = mii->mii_media.ifm_cur; 2177 2178 /* 2179 * If the user manually selects a media mode, we need to turn 2180 * on the forced MAC mode bit in the DIAGCTL register. If the 2181 * user happens to choose a full duplex mode, we also need to 2182 * set the 'force full duplex' bit. This applies only to 2183 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2184 * mode is disabled, and in 1000baseT mode, full duplex is 2185 * always implied, so we turn on the forced mode bit but leave 2186 * the FDX bit cleared. 2187 */ 2188 2189 switch (IFM_SUBTYPE(ife->ifm_media)) { 2190 case IFM_AUTO: 2191 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2192 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2193 break; 2194 case IFM_1000_T: 2195 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2196 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2197 break; 2198 case IFM_100_TX: 2199 case IFM_10_T: 2200 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2201 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2202 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2203 } else { 2204 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2205 } 2206 break; 2207 default: 2208 device_printf(dev, "unknown media type: %x\n", 2209 IFM_SUBTYPE(ife->ifm_media)); 2210 break; 2211 } 2212 2213 return; 2214} 2215 2216static int 2217vge_ioctl(ifp, command, data) 2218 struct ifnet *ifp; 2219 u_long command; 2220 caddr_t data; 2221{ 2222 struct vge_softc *sc = ifp->if_softc; 2223 struct ifreq *ifr = (struct ifreq *) data; 2224 struct mii_data *mii; 2225 int error = 0; 2226 2227 switch (command) { 2228 case SIOCSIFMTU: 2229 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2230 error = EINVAL; 2231 ifp->if_mtu = ifr->ifr_mtu; 2232 break; 2233 case SIOCSIFFLAGS: 2234 if (ifp->if_flags & IFF_UP) { 2235 if (ifp->if_flags & IFF_RUNNING && 2236 ifp->if_flags & IFF_PROMISC && 2237 !(sc->vge_if_flags & IFF_PROMISC)) { 2238 CSR_SETBIT_1(sc, VGE_RXCTL, 2239 VGE_RXCTL_RX_PROMISC); 2240 vge_setmulti(sc); 2241 } else if (ifp->if_flags & IFF_RUNNING && 2242 !(ifp->if_flags & IFF_PROMISC) && 2243 sc->vge_if_flags & IFF_PROMISC) { 2244 CSR_CLRBIT_1(sc, VGE_RXCTL, 2245 VGE_RXCTL_RX_PROMISC); 2246 vge_setmulti(sc); 2247 } else 2248 vge_init(sc); 2249 } else { 2250 if (ifp->if_flags & IFF_RUNNING) 2251 vge_stop(sc); 2252 } 2253 sc->vge_if_flags = ifp->if_flags; 2254 break; 2255 case SIOCADDMULTI: 2256 case SIOCDELMULTI: 2257 vge_setmulti(sc); 2258 break; 2259 case SIOCGIFMEDIA: 2260 case SIOCSIFMEDIA: 2261 mii = device_get_softc(sc->vge_miibus); 2262 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2263 break; 2264 case SIOCSIFCAP: 2265#ifdef IFCAP_POLLING 2266 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2267#else 2268 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2269#endif 2270 ifp->if_capenable |= 2271#ifdef IFCAP_POLLING 2272 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2273#else 2274 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2275#endif 2276 if (ifp->if_capenable & IFCAP_TXCSUM) 2277 ifp->if_hwassist = VGE_CSUM_FEATURES; 2278 else 2279 ifp->if_hwassist = 0; 2280 if (ifp->if_flags & IFF_RUNNING) 2281 vge_init(sc); 2282 break; 2283 default: 2284 error = ether_ioctl(ifp, command, data); 2285 break; 2286 } 2287 2288 return (error); 2289} 2290 2291static void 2292vge_watchdog(ifp) 2293 struct ifnet *ifp; 2294{ 2295 struct vge_softc *sc; 2296 2297 sc = ifp->if_softc; 2298 VGE_LOCK(sc); 2299 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2300 ifp->if_oerrors++; 2301 2302 vge_txeof(sc); 2303 vge_rxeof(sc); 2304 2305 vge_init(sc); 2306 2307 VGE_UNLOCK(sc); 2308 2309 return; 2310} 2311 2312/* 2313 * Stop the adapter and free any mbufs allocated to the 2314 * RX and TX lists. 2315 */ 2316static void 2317vge_stop(sc) 2318 struct vge_softc *sc; 2319{ 2320 register int i; 2321 struct ifnet *ifp; 2322 2323 VGE_LOCK(sc); 2324 ifp = &sc->arpcom.ac_if; 2325 ifp->if_timer = 0; 2326 2327 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2328#ifdef DEVICE_POLLING 2329 ether_poll_deregister(ifp); 2330#endif /* DEVICE_POLLING */ 2331 2332 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2333 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2334 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2335 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2336 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2337 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2338 2339 if (sc->vge_head != NULL) { 2340 m_freem(sc->vge_head); 2341 sc->vge_head = sc->vge_tail = NULL; 2342 } 2343 2344 /* Free the TX list buffers. */ 2345 2346 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2347 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2348 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2349 sc->vge_ldata.vge_tx_dmamap[i]); 2350 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2351 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2352 } 2353 } 2354 2355 /* Free the RX list buffers. */ 2356 2357 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2358 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2359 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2360 sc->vge_ldata.vge_rx_dmamap[i]); 2361 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2362 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2363 } 2364 } 2365 2366 VGE_UNLOCK(sc); 2367 2368 return; 2369} 2370 2371/* 2372 * Device suspend routine. Stop the interface and save some PCI 2373 * settings in case the BIOS doesn't restore them properly on 2374 * resume. 2375 */ 2376static int 2377vge_suspend(dev) 2378 device_t dev; 2379{ 2380 struct vge_softc *sc; 2381 int i; 2382 2383 sc = device_get_softc(dev); 2384 2385 vge_stop(sc); 2386 2387 for (i = 0; i < 5; i++) 2388 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2389 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2390 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2391 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2392 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2393 2394 sc->suspended = 1; 2395 2396 return (0); 2397} 2398 2399/* 2400 * Device resume routine. Restore some PCI settings in case the BIOS 2401 * doesn't, re-enable busmastering, and restart the interface if 2402 * appropriate. 2403 */ 2404static int 2405vge_resume(dev) 2406 device_t dev; 2407{ 2408 struct vge_softc *sc; 2409 struct ifnet *ifp; 2410 int i; 2411 2412 sc = device_get_softc(dev); 2413 ifp = &sc->arpcom.ac_if; 2414 2415 /* better way to do this? */ 2416 for (i = 0; i < 5; i++) 2417 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2418 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2419 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2420 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2421 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2422 2423 /* reenable busmastering */ 2424 pci_enable_busmaster(dev); 2425 pci_enable_io(dev, SYS_RES_MEMORY); 2426 2427 /* reinitialize interface if necessary */ 2428 if (ifp->if_flags & IFF_UP) 2429 vge_init(sc); 2430 2431 sc->suspended = 0; 2432 2433 return (0); 2434} 2435 2436/* 2437 * Stop all chip I/O so that the kernel's probe routines don't 2438 * get confused by errant DMAs when rebooting. 2439 */ 2440static void 2441vge_shutdown(dev) 2442 device_t dev; 2443{ 2444 struct vge_softc *sc; 2445 2446 sc = device_get_softc(dev); 2447 2448 vge_stop(sc); 2449} 2450