if_vge.c revision 135062
1/* 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 135062 2004-09-11 01:07:39Z wpaul $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#include <sys/param.h> 84#include <sys/endian.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/module.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92#include <sys/taskqueue.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_vlan_var.h> 100#include <net/route.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117MODULE_DEPEND(vge, pci, 1, 1, 1); 118MODULE_DEPEND(vge, ether, 1, 1, 1); 119MODULE_DEPEND(vge, miibus, 1, 1, 1); 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124#include <dev/vge/if_vgereg.h> 125#include <dev/vge/if_vgevar.h> 126 127#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 128 129/* 130 * Various supported device vendors/types and their names. 131 */ 132static struct vge_type vge_devs[] = { 133 { VIA_VENDORID, VIA_DEVICEID_61XX, 134 "VIA Networking Gigabit Ethernet" }, 135 { 0, 0, NULL } 136}; 137 138static int vge_probe (device_t); 139static int vge_attach (device_t); 140static int vge_detach (device_t); 141 142static int vge_encap (struct vge_softc *, struct mbuf *, int); 143 144static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 145static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 146 bus_size_t, int); 147static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 148 bus_size_t, int); 149static int vge_allocmem (device_t, struct vge_softc *); 150static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 151static int vge_rx_list_init (struct vge_softc *); 152static int vge_tx_list_init (struct vge_softc *); 153#ifdef VGE_FIXUP_RX 154static __inline void vge_fixup_rx 155 (struct mbuf *); 156#endif 157static void vge_rxeof (struct vge_softc *); 158static void vge_txeof (struct vge_softc *); 159static void vge_intr (void *); 160static void vge_tick (void *); 161static void vge_tx_task (void *, int); 162static void vge_start (struct ifnet *); 163static int vge_ioctl (struct ifnet *, u_long, caddr_t); 164static void vge_init (void *); 165static void vge_stop (struct vge_softc *); 166static void vge_watchdog (struct ifnet *); 167static int vge_suspend (device_t); 168static int vge_resume (device_t); 169static void vge_shutdown (device_t); 170static int vge_ifmedia_upd (struct ifnet *); 171static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 172 173static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 174static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 175 176static void vge_miipoll_start (struct vge_softc *); 177static void vge_miipoll_stop (struct vge_softc *); 178static int vge_miibus_readreg (device_t, int, int); 179static int vge_miibus_writereg (device_t, int, int, int); 180static void vge_miibus_statchg (device_t); 181 182static void vge_cam_clear (struct vge_softc *); 183static int vge_cam_set (struct vge_softc *, uint8_t *); 184#if __FreeBSD_version < 502113 185static uint32_t vge_mchash (uint8_t *); 186#endif 187static void vge_setmulti (struct vge_softc *); 188static void vge_reset (struct vge_softc *); 189 190#define VGE_PCI_LOIO 0x10 191#define VGE_PCI_LOMEM 0x14 192 193static device_method_t vge_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, vge_probe), 196 DEVMETHOD(device_attach, vge_attach), 197 DEVMETHOD(device_detach, vge_detach), 198 DEVMETHOD(device_suspend, vge_suspend), 199 DEVMETHOD(device_resume, vge_resume), 200 DEVMETHOD(device_shutdown, vge_shutdown), 201 202 /* bus interface */ 203 DEVMETHOD(bus_print_child, bus_generic_print_child), 204 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 205 206 /* MII interface */ 207 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 208 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 209 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 210 211 { 0, 0 } 212}; 213 214static driver_t vge_driver = { 215 "vge", 216 vge_methods, 217 sizeof(struct vge_softc) 218}; 219 220static devclass_t vge_devclass; 221 222DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 223DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226/* 227 * Read a word of data stored in the EEPROM at address 'addr.' 228 */ 229static void 230vge_eeprom_getword(sc, addr, dest) 231 struct vge_softc *sc; 232 int addr; 233 u_int16_t *dest; 234{ 235 register int i; 236 u_int16_t word = 0; 237 238 /* 239 * Enter EEPROM embedded programming mode. In order to 240 * access the EEPROM at all, we first have to set the 241 * EELOAD bit in the CHIPCFG2 register. 242 */ 243 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 244 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 245 246 /* Select the address of the word we want to read */ 247 CSR_WRITE_1(sc, VGE_EEADDR, addr); 248 249 /* Issue read command */ 250 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 251 252 /* Wait for the done bit to be set. */ 253 for (i = 0; i < VGE_TIMEOUT; i++) { 254 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 255 break; 256 } 257 258 if (i == VGE_TIMEOUT) { 259 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 260 *dest = 0; 261 return; 262 } 263 264 /* Read the result */ 265 word = CSR_READ_2(sc, VGE_EERDDAT); 266 267 /* Turn off EEPROM access mode. */ 268 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 269 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 270 271 *dest = word; 272 273 return; 274} 275 276/* 277 * Read a sequence of words from the EEPROM. 278 */ 279static void 280vge_read_eeprom(sc, dest, off, cnt, swap) 281 struct vge_softc *sc; 282 caddr_t dest; 283 int off; 284 int cnt; 285 int swap; 286{ 287 int i; 288 u_int16_t word = 0, *ptr; 289 290 for (i = 0; i < cnt; i++) { 291 vge_eeprom_getword(sc, off + i, &word); 292 ptr = (u_int16_t *)(dest + (i * 2)); 293 if (swap) 294 *ptr = ntohs(word); 295 else 296 *ptr = word; 297 } 298} 299 300static void 301vge_miipoll_stop(sc) 302 struct vge_softc *sc; 303{ 304 int i; 305 306 CSR_WRITE_1(sc, VGE_MIICMD, 0); 307 308 for (i = 0; i < VGE_TIMEOUT; i++) { 309 DELAY(1); 310 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 311 break; 312 } 313 314 if (i == VGE_TIMEOUT) 315 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 316 317 return; 318} 319 320static void 321vge_miipoll_start(sc) 322 struct vge_softc *sc; 323{ 324 int i; 325 326 /* First, make sure we're idle. */ 327 328 CSR_WRITE_1(sc, VGE_MIICMD, 0); 329 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 330 331 for (i = 0; i < VGE_TIMEOUT; i++) { 332 DELAY(1); 333 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 334 break; 335 } 336 337 if (i == VGE_TIMEOUT) { 338 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 339 return; 340 } 341 342 /* Now enable auto poll mode. */ 343 344 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 345 346 /* And make sure it started. */ 347 348 for (i = 0; i < VGE_TIMEOUT; i++) { 349 DELAY(1); 350 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 351 break; 352 } 353 354 if (i == VGE_TIMEOUT) 355 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 356 357 return; 358} 359 360static int 361vge_miibus_readreg(dev, phy, reg) 362 device_t dev; 363 int phy, reg; 364{ 365 struct vge_softc *sc; 366 int i; 367 u_int16_t rval = 0; 368 369 sc = device_get_softc(dev); 370 371 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 372 return(0); 373 374 VGE_LOCK(sc); 375 vge_miipoll_stop(sc); 376 377 /* Specify the register we want to read. */ 378 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 379 380 /* Issue read command. */ 381 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 382 383 /* Wait for the read command bit to self-clear. */ 384 for (i = 0; i < VGE_TIMEOUT; i++) { 385 DELAY(1); 386 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 387 break; 388 } 389 390 if (i == VGE_TIMEOUT) 391 device_printf(sc->vge_dev, "MII read timed out\n"); 392 else 393 rval = CSR_READ_2(sc, VGE_MIIDATA); 394 395 vge_miipoll_start(sc); 396 VGE_UNLOCK(sc); 397 398 return (rval); 399} 400 401static int 402vge_miibus_writereg(dev, phy, reg, data) 403 device_t dev; 404 int phy, reg, data; 405{ 406 struct vge_softc *sc; 407 int i, rval = 0; 408 409 sc = device_get_softc(dev); 410 411 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 412 return(0); 413 414 VGE_LOCK(sc); 415 vge_miipoll_stop(sc); 416 417 /* Specify the register we want to write. */ 418 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 419 420 /* Specify the data we want to write. */ 421 CSR_WRITE_2(sc, VGE_MIIDATA, data); 422 423 /* Issue write command. */ 424 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 425 426 /* Wait for the write command bit to self-clear. */ 427 for (i = 0; i < VGE_TIMEOUT; i++) { 428 DELAY(1); 429 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 430 break; 431 } 432 433 if (i == VGE_TIMEOUT) { 434 device_printf(sc->vge_dev, "MII write timed out\n"); 435 rval = EIO; 436 } 437 438 vge_miipoll_start(sc); 439 VGE_UNLOCK(sc); 440 441 return (rval); 442} 443 444static void 445vge_cam_clear(sc) 446 struct vge_softc *sc; 447{ 448 int i; 449 450 /* 451 * Turn off all the mask bits. This tells the chip 452 * that none of the entries in the CAM filter are valid. 453 * desired entries will be enabled as we fill the filter in. 454 */ 455 456 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 457 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 458 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 459 for (i = 0; i < 8; i++) 460 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 461 462 /* Clear the VLAN filter too. */ 463 464 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 465 for (i = 0; i < 8; i++) 466 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 467 468 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 469 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 470 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 471 472 sc->vge_camidx = 0; 473 474 return; 475} 476 477static int 478vge_cam_set(sc, addr) 479 struct vge_softc *sc; 480 uint8_t *addr; 481{ 482 int i, error = 0; 483 484 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 485 return(ENOSPC); 486 487 /* Select the CAM data page. */ 488 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 489 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 490 491 /* Set the filter entry we want to update and enable writing. */ 492 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 493 494 /* Write the address to the CAM registers */ 495 for (i = 0; i < ETHER_ADDR_LEN; i++) 496 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 497 498 /* Issue a write command. */ 499 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 500 501 /* Wake for it to clear. */ 502 for (i = 0; i < VGE_TIMEOUT; i++) { 503 DELAY(1); 504 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 505 break; 506 } 507 508 if (i == VGE_TIMEOUT) { 509 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 510 error = EIO; 511 goto fail; 512 } 513 514 /* Select the CAM mask page. */ 515 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 516 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 517 518 /* Set the mask bit that enables this filter. */ 519 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 520 1<<(sc->vge_camidx & 7)); 521 522 sc->vge_camidx++; 523 524fail: 525 /* Turn off access to CAM. */ 526 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 527 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 528 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 529 530 return (error); 531} 532 533#if __FreeBSD_version < 502113 534static uint32_t 535vge_mchash(addr) 536 uint8_t *addr; 537{ 538 uint32_t crc, carry; 539 int idx, bit; 540 uint8_t data; 541 542 /* Compute CRC for the address value. */ 543 crc = 0xFFFFFFFF; /* initial value */ 544 545 for (idx = 0; idx < 6; idx++) { 546 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 547 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 548 crc <<= 1; 549 if (carry) 550 crc = (crc ^ 0x04c11db6) | carry; 551 } 552 } 553 554 return(crc); 555} 556#endif 557 558/* 559 * Program the multicast filter. We use the 64-entry CAM filter 560 * for perfect filtering. If there's more than 64 multicast addresses, 561 * we use the hash filter insted. 562 */ 563static void 564vge_setmulti(sc) 565 struct vge_softc *sc; 566{ 567 struct ifnet *ifp; 568 int error = 0/*, h = 0*/; 569 struct ifmultiaddr *ifma; 570 u_int32_t h, hashes[2] = { 0, 0 }; 571 572 ifp = &sc->arpcom.ac_if; 573 574 /* First, zot all the multicast entries. */ 575 vge_cam_clear(sc); 576 CSR_WRITE_4(sc, VGE_MAR0, 0); 577 CSR_WRITE_4(sc, VGE_MAR1, 0); 578 579 /* 580 * If the user wants allmulti or promisc mode, enable reception 581 * of all multicast frames. 582 */ 583 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 584 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 585 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 586 return; 587 } 588 589 /* Now program new ones */ 590 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 591 if (ifma->ifma_addr->sa_family != AF_LINK) 592 continue; 593 error = vge_cam_set(sc, 594 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 595 if (error) 596 break; 597 } 598 599 /* If there were too many addresses, use the hash filter. */ 600 if (error) { 601 vge_cam_clear(sc); 602 603 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 604 if (ifma->ifma_addr->sa_family != AF_LINK) 605 continue; 606#if __FreeBSD_version < 502113 607 h = vge_mchash(LLADDR((struct sockaddr_dl *) 608 ifma->ifma_addr)) >> 26; 609#else 610 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 611 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 612#endif 613 if (h < 32) 614 hashes[0] |= (1 << h); 615 else 616 hashes[1] |= (1 << (h - 32)); 617 } 618 619 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 620 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 621 } 622 623 return; 624} 625 626static void 627vge_reset(sc) 628 struct vge_softc *sc; 629{ 630 register int i; 631 632 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 633 634 for (i = 0; i < VGE_TIMEOUT; i++) { 635 DELAY(5); 636 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 637 break; 638 } 639 640 if (i == VGE_TIMEOUT) { 641 device_printf(sc->vge_dev, "soft reset timed out"); 642 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 643 DELAY(2000); 644 } 645 646 DELAY(5000); 647 648 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 649 650 for (i = 0; i < VGE_TIMEOUT; i++) { 651 DELAY(5); 652 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 653 break; 654 } 655 656 if (i == VGE_TIMEOUT) { 657 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 658 return; 659 } 660 661 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 662 663 return; 664} 665 666/* 667 * Probe for a VIA gigabit chip. Check the PCI vendor and device 668 * IDs against our list and return a device name if we find a match. 669 */ 670static int 671vge_probe(dev) 672 device_t dev; 673{ 674 struct vge_type *t; 675 struct vge_softc *sc; 676 677 t = vge_devs; 678 sc = device_get_softc(dev); 679 680 while (t->vge_name != NULL) { 681 if ((pci_get_vendor(dev) == t->vge_vid) && 682 (pci_get_device(dev) == t->vge_did)) { 683 device_set_desc(dev, t->vge_name); 684 return (0); 685 } 686 t++; 687 } 688 689 return (ENXIO); 690} 691 692static void 693vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 694 void *arg; 695 bus_dma_segment_t *segs; 696 int nseg; 697 bus_size_t mapsize; 698 int error; 699{ 700 701 struct vge_dmaload_arg *ctx; 702 struct vge_rx_desc *d = NULL; 703 704 if (error) 705 return; 706 707 ctx = arg; 708 709 /* Signal error to caller if there's too many segments */ 710 if (nseg > ctx->vge_maxsegs) { 711 ctx->vge_maxsegs = 0; 712 return; 713 } 714 715 /* 716 * Map the segment array into descriptors. 717 */ 718 719 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 720 721 /* If this descriptor is still owned by the chip, bail. */ 722 723 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 724 device_printf(ctx->sc->vge_dev, 725 "tried to map busy descriptor\n"); 726 ctx->vge_maxsegs = 0; 727 return; 728 } 729 730 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 731 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 732 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 733 d->vge_sts = 0; 734 d->vge_ctl = 0; 735 736 ctx->vge_maxsegs = 1; 737 738 return; 739} 740 741static void 742vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 743 void *arg; 744 bus_dma_segment_t *segs; 745 int nseg; 746 bus_size_t mapsize; 747 int error; 748{ 749 struct vge_dmaload_arg *ctx; 750 struct vge_tx_desc *d = NULL; 751 struct vge_tx_frag *f; 752 int i = 0; 753 754 if (error) 755 return; 756 757 ctx = arg; 758 759 /* Signal error to caller if there's too many segments */ 760 if (nseg > ctx->vge_maxsegs) { 761 ctx->vge_maxsegs = 0; 762 return; 763 } 764 765 /* Map the segment array into descriptors. */ 766 767 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 768 769 /* If this descriptor is still owned by the chip, bail. */ 770 771 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 772 ctx->vge_maxsegs = 0; 773 return; 774 } 775 776 for (i = 0; i < nseg; i++) { 777 f = &d->vge_frag[i]; 778 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 779 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 780 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 781 } 782 783 /* Argh. This chip does not autopad short frames */ 784 785 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 786 f = &d->vge_frag[i]; 787 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 788 ctx->vge_m0->m_pkthdr.len)); 789 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 790 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 791 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 792 i++; 793 } 794 795 /* 796 * When telling the chip how many segments there are, we 797 * must use nsegs + 1 instead of just nsegs. Darned if I 798 * know why. 799 */ 800 i++; 801 802 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 803 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 804 805 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 806 d->vge_ctl |= VGE_TDCTL_JUMBO; 807 808 ctx->vge_maxsegs = nseg; 809 810 return; 811} 812 813/* 814 * Map a single buffer address. 815 */ 816 817static void 818vge_dma_map_addr(arg, segs, nseg, error) 819 void *arg; 820 bus_dma_segment_t *segs; 821 int nseg; 822 int error; 823{ 824 bus_addr_t *addr; 825 826 if (error) 827 return; 828 829 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 830 addr = arg; 831 *addr = segs->ds_addr; 832 833 return; 834} 835 836static int 837vge_allocmem(dev, sc) 838 device_t dev; 839 struct vge_softc *sc; 840{ 841 int error; 842 int nseg; 843 int i; 844 845 /* 846 * Allocate map for RX mbufs. 847 */ 848 nseg = 32; 849 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 850 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 851 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 852 NULL, NULL, &sc->vge_ldata.vge_mtag); 853 if (error) { 854 device_printf(dev, "could not allocate dma tag\n"); 855 return (ENOMEM); 856 } 857 858 /* 859 * Allocate map for TX descriptor list. 860 */ 861 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 862 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 863 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 864 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 865 if (error) { 866 device_printf(dev, "could not allocate dma tag\n"); 867 return (ENOMEM); 868 } 869 870 /* Allocate DMA'able memory for the TX ring */ 871 872 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 873 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 874 &sc->vge_ldata.vge_tx_list_map); 875 if (error) 876 return (ENOMEM); 877 878 /* Load the map for the TX ring. */ 879 880 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 881 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 882 VGE_TX_LIST_SZ, vge_dma_map_addr, 883 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 884 885 /* Create DMA maps for TX buffers */ 886 887 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 888 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 889 &sc->vge_ldata.vge_tx_dmamap[i]); 890 if (error) { 891 device_printf(dev, "can't create DMA map for TX\n"); 892 return (ENOMEM); 893 } 894 } 895 896 /* 897 * Allocate map for RX descriptor list. 898 */ 899 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 900 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 901 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 902 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 903 if (error) { 904 device_printf(dev, "could not allocate dma tag\n"); 905 return (ENOMEM); 906 } 907 908 /* Allocate DMA'able memory for the RX ring */ 909 910 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 911 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 912 &sc->vge_ldata.vge_rx_list_map); 913 if (error) 914 return (ENOMEM); 915 916 /* Load the map for the RX ring. */ 917 918 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 919 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 920 VGE_TX_LIST_SZ, vge_dma_map_addr, 921 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 922 923 /* Create DMA maps for RX buffers */ 924 925 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 926 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 927 &sc->vge_ldata.vge_rx_dmamap[i]); 928 if (error) { 929 device_printf(dev, "can't create DMA map for RX\n"); 930 return (ENOMEM); 931 } 932 } 933 934 return (0); 935} 936 937/* 938 * Attach the interface. Allocate softc structures, do ifmedia 939 * setup and ethernet/BPF attach. 940 */ 941static int 942vge_attach(dev) 943 device_t dev; 944{ 945 u_char eaddr[ETHER_ADDR_LEN]; 946 struct vge_softc *sc; 947 struct ifnet *ifp; 948 int unit, error = 0, rid; 949 950 sc = device_get_softc(dev); 951 unit = device_get_unit(dev); 952 sc->vge_dev = dev; 953 954 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 955 MTX_DEF | MTX_RECURSE); 956 /* 957 * Map control/status registers. 958 */ 959 pci_enable_busmaster(dev); 960 961 rid = VGE_PCI_LOMEM; 962 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 963 0, ~0, 1, RF_ACTIVE); 964 965 if (sc->vge_res == NULL) { 966 printf ("vge%d: couldn't map ports/memory\n", unit); 967 error = ENXIO; 968 goto fail; 969 } 970 971 sc->vge_btag = rman_get_bustag(sc->vge_res); 972 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 973 974 /* Allocate interrupt */ 975 rid = 0; 976 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 977 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 978 979 if (sc->vge_irq == NULL) { 980 printf("vge%d: couldn't map interrupt\n", unit); 981 error = ENXIO; 982 goto fail; 983 } 984 985 /* Reset the adapter. */ 986 vge_reset(sc); 987 988 /* 989 * Get station address from the EEPROM. 990 */ 991 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 992 993 sc->vge_unit = unit; 994 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 995 996#if __FreeBSD_version < 502113 997 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 998#endif 999 1000 /* 1001 * Allocate the parent bus DMA tag appropriate for PCI. 1002 */ 1003#define VGE_NSEG_NEW 32 1004 error = bus_dma_tag_create(NULL, /* parent */ 1005 1, 0, /* alignment, boundary */ 1006 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1007 BUS_SPACE_MAXADDR, /* highaddr */ 1008 NULL, NULL, /* filter, filterarg */ 1009 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1010 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1011 BUS_DMA_ALLOCNOW, /* flags */ 1012 NULL, NULL, /* lockfunc, lockarg */ 1013 &sc->vge_parent_tag); 1014 if (error) 1015 goto fail; 1016 1017 error = vge_allocmem(dev, sc); 1018 1019 if (error) 1020 goto fail; 1021 1022 /* Do MII setup */ 1023 if (mii_phy_probe(dev, &sc->vge_miibus, 1024 vge_ifmedia_upd, vge_ifmedia_sts)) { 1025 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1026 error = ENXIO; 1027 goto fail; 1028 } 1029 1030 ifp = &sc->arpcom.ac_if; 1031 ifp->if_softc = sc; 1032 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1033 ifp->if_mtu = ETHERMTU; 1034 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1035 ifp->if_ioctl = vge_ioctl; 1036 ifp->if_capabilities = IFCAP_VLAN_MTU; 1037 ifp->if_start = vge_start; 1038 ifp->if_hwassist = VGE_CSUM_FEATURES; 1039 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1040#ifdef DEVICE_POLLING 1041#ifdef IFCAP_POLLING 1042 ifp->if_capabilities |= IFCAP_POLLING; 1043#endif 1044#endif 1045 ifp->if_watchdog = vge_watchdog; 1046 ifp->if_init = vge_init; 1047 ifp->if_baudrate = 1000000000; 1048 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1049 ifp->if_capenable = ifp->if_capabilities; 1050 1051 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1052 1053 /* 1054 * Call MI attach routine. 1055 */ 1056 ether_ifattach(ifp, eaddr); 1057 1058 /* Hook interrupt last to avoid having to lock softc */ 1059 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1060 vge_intr, sc, &sc->vge_intrhand); 1061 1062 if (error) { 1063 printf("vge%d: couldn't set up irq\n", unit); 1064 ether_ifdetach(ifp); 1065 goto fail; 1066 } 1067 1068fail: 1069 if (error) 1070 vge_detach(dev); 1071 1072 return (error); 1073} 1074 1075/* 1076 * Shutdown hardware and free up resources. This can be called any 1077 * time after the mutex has been initialized. It is called in both 1078 * the error case in attach and the normal detach case so it needs 1079 * to be careful about only freeing resources that have actually been 1080 * allocated. 1081 */ 1082static int 1083vge_detach(dev) 1084 device_t dev; 1085{ 1086 struct vge_softc *sc; 1087 struct ifnet *ifp; 1088 int i; 1089 1090 sc = device_get_softc(dev); 1091 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1092 ifp = &sc->arpcom.ac_if; 1093 1094 /* These should only be active if attach succeeded */ 1095 if (device_is_attached(dev)) { 1096 vge_stop(sc); 1097 /* 1098 * Force off the IFF_UP flag here, in case someone 1099 * still had a BPF descriptor attached to this 1100 * interface. If they do, ether_ifattach() will cause 1101 * the BPF code to try and clear the promisc mode 1102 * flag, which will bubble down to vge_ioctl(), 1103 * which will try to call vge_init() again. This will 1104 * turn the NIC back on and restart the MII ticker, 1105 * which will panic the system when the kernel tries 1106 * to invoke the vge_tick() function that isn't there 1107 * anymore. 1108 */ 1109 ifp->if_flags &= ~IFF_UP; 1110 ether_ifdetach(ifp); 1111 } 1112 if (sc->vge_miibus) 1113 device_delete_child(dev, sc->vge_miibus); 1114 bus_generic_detach(dev); 1115 1116 if (sc->vge_intrhand) 1117 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1118 if (sc->vge_irq) 1119 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1120 if (sc->vge_res) 1121 bus_release_resource(dev, SYS_RES_MEMORY, 1122 VGE_PCI_LOMEM, sc->vge_res); 1123 1124 /* Unload and free the RX DMA ring memory and map */ 1125 1126 if (sc->vge_ldata.vge_rx_list_tag) { 1127 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1128 sc->vge_ldata.vge_rx_list_map); 1129 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1130 sc->vge_ldata.vge_rx_list, 1131 sc->vge_ldata.vge_rx_list_map); 1132 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1133 } 1134 1135 /* Unload and free the TX DMA ring memory and map */ 1136 1137 if (sc->vge_ldata.vge_tx_list_tag) { 1138 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1139 sc->vge_ldata.vge_tx_list_map); 1140 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1141 sc->vge_ldata.vge_tx_list, 1142 sc->vge_ldata.vge_tx_list_map); 1143 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1144 } 1145 1146 /* Destroy all the RX and TX buffer maps */ 1147 1148 if (sc->vge_ldata.vge_mtag) { 1149 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1150 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1151 sc->vge_ldata.vge_tx_dmamap[i]); 1152 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1153 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1154 sc->vge_ldata.vge_rx_dmamap[i]); 1155 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1156 } 1157 1158 if (sc->vge_parent_tag) 1159 bus_dma_tag_destroy(sc->vge_parent_tag); 1160 1161 mtx_destroy(&sc->vge_mtx); 1162 1163 return (0); 1164} 1165 1166static int 1167vge_newbuf(sc, idx, m) 1168 struct vge_softc *sc; 1169 int idx; 1170 struct mbuf *m; 1171{ 1172 struct vge_dmaload_arg arg; 1173 struct mbuf *n = NULL; 1174 int i, error; 1175 1176 if (m == NULL) { 1177 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1178 if (n == NULL) 1179 return (ENOBUFS); 1180 m = n; 1181 } else 1182 m->m_data = m->m_ext.ext_buf; 1183 1184 1185#ifdef VGE_FIXUP_RX 1186 /* 1187 * This is part of an evil trick to deal with non-x86 platforms. 1188 * The VIA chip requires RX buffers to be aligned on 32-bit 1189 * boundaries, but that will hose non-x86 machines. To get around 1190 * this, we leave some empty space at the start of each buffer 1191 * and for non-x86 hosts, we copy the buffer back two bytes 1192 * to achieve word alignment. This is slightly more efficient 1193 * than allocating a new buffer, copying the contents, and 1194 * discarding the old buffer. 1195 */ 1196 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1197 m_adj(m, VGE_ETHER_ALIGN); 1198#else 1199 m->m_len = m->m_pkthdr.len = MCLBYTES; 1200#endif 1201 1202 arg.sc = sc; 1203 arg.vge_idx = idx; 1204 arg.vge_maxsegs = 1; 1205 arg.vge_flags = 0; 1206 1207 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1208 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1209 &arg, BUS_DMA_NOWAIT); 1210 if (error || arg.vge_maxsegs != 1) { 1211 if (n != NULL) 1212 m_freem(n); 1213 return (ENOMEM); 1214 } 1215 1216 /* 1217 * Note: the manual fails to document the fact that for 1218 * proper opration, the driver needs to replentish the RX 1219 * DMA ring 4 descriptors at a time (rather than one at a 1220 * time, like most chips). We can allocate the new buffers 1221 * but we should not set the OWN bits until we're ready 1222 * to hand back 4 of them in one shot. 1223 */ 1224 1225#define VGE_RXCHUNK 4 1226 sc->vge_rx_consumed++; 1227 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1228 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1229 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1230 htole32(VGE_RDSTS_OWN); 1231 sc->vge_rx_consumed = 0; 1232 } 1233 1234 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1235 1236 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1237 sc->vge_ldata.vge_rx_dmamap[idx], 1238 BUS_DMASYNC_PREREAD); 1239 1240 return (0); 1241} 1242 1243static int 1244vge_tx_list_init(sc) 1245 struct vge_softc *sc; 1246{ 1247 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1248 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1249 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1250 1251 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1252 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1253 sc->vge_ldata.vge_tx_prodidx = 0; 1254 sc->vge_ldata.vge_tx_considx = 0; 1255 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1256 1257 return (0); 1258} 1259 1260static int 1261vge_rx_list_init(sc) 1262 struct vge_softc *sc; 1263{ 1264 int i; 1265 1266 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1267 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1268 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1269 1270 sc->vge_rx_consumed = 0; 1271 1272 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1273 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1274 return (ENOBUFS); 1275 } 1276 1277 /* Flush the RX descriptors */ 1278 1279 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1280 sc->vge_ldata.vge_rx_list_map, 1281 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1282 1283 sc->vge_ldata.vge_rx_prodidx = 0; 1284 sc->vge_rx_consumed = 0; 1285 sc->vge_head = sc->vge_tail = NULL; 1286 1287 return (0); 1288} 1289 1290#ifdef VGE_FIXUP_RX 1291static __inline void 1292vge_fixup_rx(m) 1293 struct mbuf *m; 1294{ 1295 int i; 1296 uint16_t *src, *dst; 1297 1298 src = mtod(m, uint16_t *); 1299 dst = src - 1; 1300 1301 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1302 *dst++ = *src++; 1303 1304 m->m_data -= ETHER_ALIGN; 1305 1306 return; 1307} 1308#endif 1309 1310/* 1311 * RX handler. We support the reception of jumbo frames that have 1312 * been fragmented across multiple 2K mbuf cluster buffers. 1313 */ 1314static void 1315vge_rxeof(sc) 1316 struct vge_softc *sc; 1317{ 1318 struct mbuf *m; 1319 struct ifnet *ifp; 1320 int i, total_len; 1321 int lim = 0; 1322 struct vge_rx_desc *cur_rx; 1323 u_int32_t rxstat, rxctl; 1324 1325 VGE_LOCK_ASSERT(sc); 1326 ifp = &sc->arpcom.ac_if; 1327 i = sc->vge_ldata.vge_rx_prodidx; 1328 1329 /* Invalidate the descriptor memory */ 1330 1331 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1332 sc->vge_ldata.vge_rx_list_map, 1333 BUS_DMASYNC_POSTREAD); 1334 1335 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1336 1337#ifdef DEVICE_POLLING 1338 if (ifp->if_flags & IFF_POLLING) { 1339 if (sc->rxcycles <= 0) 1340 break; 1341 sc->rxcycles--; 1342 } 1343#endif /* DEVICE_POLLING */ 1344 1345 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1346 m = sc->vge_ldata.vge_rx_mbuf[i]; 1347 total_len = VGE_RXBYTES(cur_rx); 1348 rxstat = le32toh(cur_rx->vge_sts); 1349 rxctl = le32toh(cur_rx->vge_ctl); 1350 1351 /* Invalidate the RX mbuf and unload its map */ 1352 1353 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1354 sc->vge_ldata.vge_rx_dmamap[i], 1355 BUS_DMASYNC_POSTWRITE); 1356 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1357 sc->vge_ldata.vge_rx_dmamap[i]); 1358 1359 /* 1360 * If the 'start of frame' bit is set, this indicates 1361 * either the first fragment in a multi-fragment receive, 1362 * or an intermediate fragment. Either way, we want to 1363 * accumulate the buffers. 1364 */ 1365 if (rxstat & VGE_RXPKT_SOF) { 1366 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1367 if (sc->vge_head == NULL) 1368 sc->vge_head = sc->vge_tail = m; 1369 else { 1370 m->m_flags &= ~M_PKTHDR; 1371 sc->vge_tail->m_next = m; 1372 sc->vge_tail = m; 1373 } 1374 vge_newbuf(sc, i, NULL); 1375 VGE_RX_DESC_INC(i); 1376 continue; 1377 } 1378 1379 /* 1380 * Bad/error frames will have the RXOK bit cleared. 1381 * However, there's one error case we want to allow: 1382 * if a VLAN tagged frame arrives and the chip can't 1383 * match it against the CAM filter, it considers this 1384 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1385 * We don't want to drop the frame though: our VLAN 1386 * filtering is done in software. 1387 */ 1388 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1389 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1390 ifp->if_ierrors++; 1391 /* 1392 * If this is part of a multi-fragment packet, 1393 * discard all the pieces. 1394 */ 1395 if (sc->vge_head != NULL) { 1396 m_freem(sc->vge_head); 1397 sc->vge_head = sc->vge_tail = NULL; 1398 } 1399 vge_newbuf(sc, i, m); 1400 VGE_RX_DESC_INC(i); 1401 continue; 1402 } 1403 1404 /* 1405 * If allocating a replacement mbuf fails, 1406 * reload the current one. 1407 */ 1408 1409 if (vge_newbuf(sc, i, NULL)) { 1410 ifp->if_ierrors++; 1411 if (sc->vge_head != NULL) { 1412 m_freem(sc->vge_head); 1413 sc->vge_head = sc->vge_tail = NULL; 1414 } 1415 vge_newbuf(sc, i, m); 1416 VGE_RX_DESC_INC(i); 1417 continue; 1418 } 1419 1420 VGE_RX_DESC_INC(i); 1421 1422 if (sc->vge_head != NULL) { 1423 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1424 /* 1425 * Special case: if there's 4 bytes or less 1426 * in this buffer, the mbuf can be discarded: 1427 * the last 4 bytes is the CRC, which we don't 1428 * care about anyway. 1429 */ 1430 if (m->m_len <= ETHER_CRC_LEN) { 1431 sc->vge_tail->m_len -= 1432 (ETHER_CRC_LEN - m->m_len); 1433 m_freem(m); 1434 } else { 1435 m->m_len -= ETHER_CRC_LEN; 1436 m->m_flags &= ~M_PKTHDR; 1437 sc->vge_tail->m_next = m; 1438 } 1439 m = sc->vge_head; 1440 sc->vge_head = sc->vge_tail = NULL; 1441 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1442 } else 1443 m->m_pkthdr.len = m->m_len = 1444 (total_len - ETHER_CRC_LEN); 1445 1446#ifdef VGE_FIXUP_RX 1447 vge_fixup_rx(m); 1448#endif 1449 ifp->if_ipackets++; 1450 m->m_pkthdr.rcvif = ifp; 1451 1452 /* Do RX checksumming if enabled */ 1453 if (ifp->if_capenable & IFCAP_RXCSUM) { 1454 1455 /* Check IP header checksum */ 1456 if (rxctl & VGE_RDCTL_IPPKT) 1457 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1458 if (rxctl & VGE_RDCTL_IPCSUMOK) 1459 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1460 1461 /* Check TCP/UDP checksum */ 1462 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1463 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1464 m->m_pkthdr.csum_flags |= 1465 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1466 m->m_pkthdr.csum_data = 0xffff; 1467 } 1468 } 1469 1470 if (rxstat & VGE_RDSTS_VTAG) 1471 VLAN_INPUT_TAG(ifp, m, 1472 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1473 1474 VGE_UNLOCK(sc); 1475 (*ifp->if_input)(ifp, m); 1476 VGE_LOCK(sc); 1477 1478 lim++; 1479 if (lim == VGE_RX_DESC_CNT) 1480 break; 1481 1482 } 1483 1484 /* Flush the RX DMA ring */ 1485 1486 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1487 sc->vge_ldata.vge_rx_list_map, 1488 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1489 1490 sc->vge_ldata.vge_rx_prodidx = i; 1491 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1492 1493 1494 return; 1495} 1496 1497static void 1498vge_txeof(sc) 1499 struct vge_softc *sc; 1500{ 1501 struct ifnet *ifp; 1502 u_int32_t txstat; 1503 int idx; 1504 1505 ifp = &sc->arpcom.ac_if; 1506 idx = sc->vge_ldata.vge_tx_considx; 1507 1508 /* Invalidate the TX descriptor list */ 1509 1510 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1511 sc->vge_ldata.vge_tx_list_map, 1512 BUS_DMASYNC_POSTREAD); 1513 1514 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1515 1516 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1517 if (txstat & VGE_TDSTS_OWN) 1518 break; 1519 1520 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1521 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1522 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1523 sc->vge_ldata.vge_tx_dmamap[idx]); 1524 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1525 ifp->if_collisions++; 1526 if (txstat & VGE_TDSTS_TXERR) 1527 ifp->if_oerrors++; 1528 else 1529 ifp->if_opackets++; 1530 1531 sc->vge_ldata.vge_tx_free++; 1532 VGE_TX_DESC_INC(idx); 1533 } 1534 1535 /* No changes made to the TX ring, so no flush needed */ 1536 1537 if (idx != sc->vge_ldata.vge_tx_considx) { 1538 sc->vge_ldata.vge_tx_considx = idx; 1539 ifp->if_flags &= ~IFF_OACTIVE; 1540 ifp->if_timer = 0; 1541 } 1542 1543 /* 1544 * If not all descriptors have been released reaped yet, 1545 * reload the timer so that we will eventually get another 1546 * interrupt that will cause us to re-enter this routine. 1547 * This is done in case the transmitter has gone idle. 1548 */ 1549 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1550 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1551 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1552 } 1553 1554 return; 1555} 1556 1557static void 1558vge_tick(xsc) 1559 void *xsc; 1560{ 1561 struct vge_softc *sc; 1562 struct ifnet *ifp; 1563 struct mii_data *mii; 1564 1565 sc = xsc; 1566 ifp = &sc->arpcom.ac_if; 1567 VGE_LOCK(sc); 1568 mii = device_get_softc(sc->vge_miibus); 1569 1570 mii_tick(mii); 1571 if (sc->vge_link) { 1572 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1573 sc->vge_link = 0; 1574#ifdef LINK_STATE_UP 1575 sc->arpcom.ac_if.if_link_state = LINK_STATE_UP; 1576 rt_ifmsg(&(sc->arpcom.ac_if)); 1577#endif /* LINK_STATE_UP */ 1578 } 1579 } else { 1580 if (mii->mii_media_status & IFM_ACTIVE && 1581 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1582 sc->vge_link = 1; 1583#ifdef LINK_STATE_DOWN 1584 sc->arpcom.ac_if.if_link_state = LINK_STATE_DOWN; 1585 rt_ifmsg(&(sc->arpcom.ac_if)); 1586#endif /* LINK_STATE_DOWN */ 1587#if __FreeBSD_version < 502114 1588 if (ifp->if_snd.ifq_head != NULL) 1589#else 1590 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1591#endif 1592 taskqueue_enqueue(taskqueue_swi, 1593 &sc->vge_txtask); 1594 } 1595 } 1596 1597 VGE_UNLOCK(sc); 1598 1599 return; 1600} 1601 1602#ifdef DEVICE_POLLING 1603static void 1604vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1605{ 1606 struct vge_softc *sc = ifp->if_softc; 1607 1608 VGE_LOCK(sc); 1609#ifdef IFCAP_POLLING 1610 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1611 ether_poll_deregister(ifp); 1612 cmd = POLL_DEREGISTER; 1613 } 1614#endif 1615 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1616 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1617 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1618 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1619 goto done; 1620 } 1621 1622 sc->rxcycles = count; 1623 vge_rxeof(sc); 1624 vge_txeof(sc); 1625 1626#if __FreeBSD_version < 502114 1627 if (ifp->if_snd.ifq_head != NULL) 1628#else 1629 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1630#endif 1631 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1632 1633 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1634 u_int32_t status; 1635 status = CSR_READ_4(sc, VGE_ISR); 1636 if (status == 0xFFFFFFFF) 1637 goto done; 1638 if (status) 1639 CSR_WRITE_4(sc, VGE_ISR, status); 1640 1641 /* 1642 * XXX check behaviour on receiver stalls. 1643 */ 1644 1645 if (status & VGE_ISR_TXDMA_STALL || 1646 status & VGE_ISR_RXDMA_STALL) 1647 vge_init(sc); 1648 1649 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1650 vge_rxeof(sc); 1651 ifp->if_ierrors++; 1652 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1653 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1654 } 1655 } 1656done: 1657 VGE_UNLOCK(sc); 1658} 1659#endif /* DEVICE_POLLING */ 1660 1661static void 1662vge_intr(arg) 1663 void *arg; 1664{ 1665 struct vge_softc *sc; 1666 struct ifnet *ifp; 1667 u_int32_t status; 1668 1669 sc = arg; 1670 1671 if (sc->suspended) { 1672 return; 1673 } 1674 1675 VGE_LOCK(sc); 1676 ifp = &sc->arpcom.ac_if; 1677 1678 if (!(ifp->if_flags & IFF_UP)) { 1679 VGE_UNLOCK(sc); 1680 return; 1681 } 1682 1683#ifdef DEVICE_POLLING 1684 if (ifp->if_flags & IFF_POLLING) 1685 goto done; 1686 if ( 1687#ifdef IFCAP_POLLING 1688 (ifp->if_capenable & IFCAP_POLLING) && 1689#endif 1690 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1691 CSR_WRITE_4(sc, VGE_IMR, 0); 1692 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1693 vge_poll(ifp, 0, 1); 1694 goto done; 1695 } 1696 1697#endif /* DEVICE_POLLING */ 1698 1699 /* Disable interrupts */ 1700 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1701 1702 for (;;) { 1703 1704 status = CSR_READ_4(sc, VGE_ISR); 1705 /* If the card has gone away the read returns 0xffff. */ 1706 if (status == 0xFFFFFFFF) 1707 break; 1708 1709 if (status) 1710 CSR_WRITE_4(sc, VGE_ISR, status); 1711 1712 if ((status & VGE_INTRS) == 0) 1713 break; 1714 1715 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1716 vge_rxeof(sc); 1717 1718 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1719 vge_rxeof(sc); 1720 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1721 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1722 } 1723 1724 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1725 vge_txeof(sc); 1726 1727 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1728 vge_init(sc); 1729 1730 if (status & VGE_ISR_LINKSTS) 1731 vge_tick(sc); 1732 } 1733 1734 /* Re-enable interrupts */ 1735 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1736 1737#ifdef DEVICE_POLLING 1738done: 1739#endif 1740 VGE_UNLOCK(sc); 1741 1742#if __FreeBSD_version < 502114 1743 if (ifp->if_snd.ifq_head != NULL) 1744#else 1745 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1746#endif 1747 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1748 1749 return; 1750} 1751 1752static int 1753vge_encap(sc, m_head, idx) 1754 struct vge_softc *sc; 1755 struct mbuf *m_head; 1756 int idx; 1757{ 1758 struct mbuf *m_new = NULL; 1759 struct vge_dmaload_arg arg; 1760 bus_dmamap_t map; 1761 int error; 1762 struct m_tag *mtag; 1763 1764 if (sc->vge_ldata.vge_tx_free <= 2) 1765 return (EFBIG); 1766 1767 arg.vge_flags = 0; 1768 1769 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1770 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1771 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1772 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1773 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1774 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1775 1776 arg.sc = sc; 1777 arg.vge_idx = idx; 1778 arg.vge_m0 = m_head; 1779 arg.vge_maxsegs = VGE_TX_FRAGS; 1780 1781 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1782 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1783 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1784 1785 if (error && error != EFBIG) { 1786 printf("vge%d: can't map mbuf (error %d)\n", 1787 sc->vge_unit, error); 1788 return (ENOBUFS); 1789 } 1790 1791 /* Too many segments to map, coalesce into a single mbuf */ 1792 1793 if (error || arg.vge_maxsegs == 0) { 1794 m_new = m_defrag(m_head, M_DONTWAIT); 1795 if (m_new == NULL) 1796 return (1); 1797 else 1798 m_head = m_new; 1799 1800 arg.sc = sc; 1801 arg.vge_m0 = m_head; 1802 arg.vge_idx = idx; 1803 arg.vge_maxsegs = 1; 1804 1805 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1806 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1807 if (error) { 1808 printf("vge%d: can't map mbuf (error %d)\n", 1809 sc->vge_unit, error); 1810 return (EFBIG); 1811 } 1812 } 1813 1814 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1815 sc->vge_ldata.vge_tx_free--; 1816 1817 /* 1818 * Set up hardware VLAN tagging. 1819 */ 1820 1821 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1822 if (mtag != NULL) 1823 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1824 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1825 1826 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1827 1828 return (0); 1829} 1830 1831static void 1832vge_tx_task(arg, npending) 1833 void *arg; 1834 int npending; 1835{ 1836 struct ifnet *ifp; 1837 1838 ifp = arg; 1839 vge_start(ifp); 1840 1841 return; 1842} 1843 1844/* 1845 * Main transmit routine. 1846 */ 1847 1848static void 1849vge_start(ifp) 1850 struct ifnet *ifp; 1851{ 1852 struct vge_softc *sc; 1853 struct mbuf *m_head = NULL; 1854 int idx, pidx = 0; 1855 1856 sc = ifp->if_softc; 1857 VGE_LOCK(sc); 1858 1859 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1860 VGE_UNLOCK(sc); 1861 return; 1862 } 1863 1864#if __FreeBSD_version < 502114 1865 if (ifp->if_snd.ifq_head == NULL) { 1866#else 1867 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1868#endif 1869 VGE_UNLOCK(sc); 1870 return; 1871 } 1872 1873 idx = sc->vge_ldata.vge_tx_prodidx; 1874 1875 pidx = idx - 1; 1876 if (pidx < 0) 1877 pidx = VGE_TX_DESC_CNT - 1; 1878 1879 1880 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1881#if __FreeBSD_version < 502114 1882 IF_DEQUEUE(&ifp->if_snd, m_head); 1883#else 1884 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1885#endif 1886 if (m_head == NULL) 1887 break; 1888 1889 if (vge_encap(sc, m_head, idx)) { 1890#if __FreeBSD_version >= 502114 1891 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1892#else 1893 IF_PREPEND(&ifp->if_snd, m_head); 1894#endif 1895 ifp->if_flags |= IFF_OACTIVE; 1896 break; 1897 } 1898 1899 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1900 htole16(VGE_TXDESC_Q); 1901 1902 pidx = idx; 1903 VGE_TX_DESC_INC(idx); 1904 1905 /* 1906 * If there's a BPF listener, bounce a copy of this frame 1907 * to him. 1908 */ 1909 BPF_MTAP(ifp, m_head); 1910 } 1911 1912 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1913 VGE_UNLOCK(sc); 1914 return; 1915 } 1916 1917 /* Flush the TX descriptors */ 1918 1919 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1920 sc->vge_ldata.vge_tx_list_map, 1921 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1922 1923 /* Issue a transmit command. */ 1924 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1925 1926 sc->vge_ldata.vge_tx_prodidx = idx; 1927 1928 /* 1929 * Use the countdown timer for interrupt moderation. 1930 * 'TX done' interrupts are disabled. Instead, we reset the 1931 * countdown timer, which will begin counting until it hits 1932 * the value in the SSTIMER register, and then trigger an 1933 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1934 * the timer count is reloaded. Only when the transmitter 1935 * is idle will the timer hit 0 and an interrupt fire. 1936 */ 1937 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1938 1939 VGE_UNLOCK(sc); 1940 1941 /* 1942 * Set a timeout in case the chip goes out to lunch. 1943 */ 1944 ifp->if_timer = 5; 1945 1946 return; 1947} 1948 1949static void 1950vge_init(xsc) 1951 void *xsc; 1952{ 1953 struct vge_softc *sc = xsc; 1954 struct ifnet *ifp = &sc->arpcom.ac_if; 1955 struct mii_data *mii; 1956 int i; 1957 1958 VGE_LOCK(sc); 1959 mii = device_get_softc(sc->vge_miibus); 1960 1961 /* 1962 * Cancel pending I/O and free all RX/TX buffers. 1963 */ 1964 vge_stop(sc); 1965 vge_reset(sc); 1966 1967 /* 1968 * Initialize the RX and TX descriptors and mbufs. 1969 */ 1970 1971 vge_rx_list_init(sc); 1972 vge_tx_list_init(sc); 1973 1974 /* Set our station address */ 1975 for (i = 0; i < ETHER_ADDR_LEN; i++) 1976 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1977 1978 /* 1979 * Set receive FIFO threshold. Also allow transmission and 1980 * reception of VLAN tagged frames. 1981 */ 1982 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1983 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1984 1985 /* Set DMA burst length */ 1986 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1987 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1988 1989 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1990 1991 /* Set collision backoff algorithm */ 1992 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1993 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1994 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1995 1996 /* Disable LPSEL field in priority resolution */ 1997 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1998 1999 /* 2000 * Load the addresses of the DMA queues into the chip. 2001 * Note that we only use one transmit queue. 2002 */ 2003 2004 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2005 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2006 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2007 2008 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2009 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2010 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2011 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2012 2013 /* Enable and wake up the RX descriptor queue */ 2014 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2015 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2016 2017 /* Enable the TX descriptor queue */ 2018 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2019 2020 /* Set up the receive filter -- allow large frames for VLANs. */ 2021 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2022 2023 /* If we want promiscuous mode, set the allframes bit. */ 2024 if (ifp->if_flags & IFF_PROMISC) { 2025 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2026 } 2027 2028 /* Set capture broadcast bit to capture broadcast frames. */ 2029 if (ifp->if_flags & IFF_BROADCAST) { 2030 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2031 } 2032 2033 /* Set multicast bit to capture multicast frames. */ 2034 if (ifp->if_flags & IFF_MULTICAST) { 2035 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2036 } 2037 2038 /* Init the cam filter. */ 2039 vge_cam_clear(sc); 2040 2041 /* Init the multicast filter. */ 2042 vge_setmulti(sc); 2043 2044 /* Enable flow control */ 2045 2046 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2047 2048 /* Enable jumbo frame reception (if desired) */ 2049 2050 /* Start the MAC. */ 2051 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2052 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2053 CSR_WRITE_1(sc, VGE_CRS0, 2054 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2055 2056 /* 2057 * Configure one-shot timer for microsecond 2058 * resulution and load it for 500 usecs. 2059 */ 2060 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2061 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2062 2063 /* 2064 * Configure interrupt moderation for receive. Enable 2065 * the holdoff counter and load it, and set the RX 2066 * suppression count to the number of descriptors we 2067 * want to allow before triggering an interrupt. 2068 * The holdoff timer is in units of 20 usecs. 2069 */ 2070 2071#ifdef notyet 2072 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2073 /* Select the interrupt holdoff timer page. */ 2074 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2075 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2076 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2077 2078 /* Enable use of the holdoff timer. */ 2079 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2080 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2081 2082 /* Select the RX suppression threshold page. */ 2083 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2084 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2085 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2086 2087 /* Restore the page select bits. */ 2088 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2089 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2090#endif 2091 2092#ifdef DEVICE_POLLING 2093 /* 2094 * Disable interrupts if we are polling. 2095 */ 2096 if (ifp->if_flags & IFF_POLLING) { 2097 CSR_WRITE_4(sc, VGE_IMR, 0); 2098 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2099 } else /* otherwise ... */ 2100#endif /* DEVICE_POLLING */ 2101 { 2102 /* 2103 * Enable interrupts. 2104 */ 2105 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2106 CSR_WRITE_4(sc, VGE_ISR, 0); 2107 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2108 } 2109 2110 mii_mediachg(mii); 2111 2112 ifp->if_flags |= IFF_RUNNING; 2113 ifp->if_flags &= ~IFF_OACTIVE; 2114 2115 sc->vge_if_flags = 0; 2116 sc->vge_link = 0; 2117 2118 VGE_UNLOCK(sc); 2119 2120 return; 2121} 2122 2123/* 2124 * Set media options. 2125 */ 2126static int 2127vge_ifmedia_upd(ifp) 2128 struct ifnet *ifp; 2129{ 2130 struct vge_softc *sc; 2131 struct mii_data *mii; 2132 2133 sc = ifp->if_softc; 2134 mii = device_get_softc(sc->vge_miibus); 2135 mii_mediachg(mii); 2136 2137 return (0); 2138} 2139 2140/* 2141 * Report current media status. 2142 */ 2143static void 2144vge_ifmedia_sts(ifp, ifmr) 2145 struct ifnet *ifp; 2146 struct ifmediareq *ifmr; 2147{ 2148 struct vge_softc *sc; 2149 struct mii_data *mii; 2150 2151 sc = ifp->if_softc; 2152 mii = device_get_softc(sc->vge_miibus); 2153 2154 mii_pollstat(mii); 2155 ifmr->ifm_active = mii->mii_media_active; 2156 ifmr->ifm_status = mii->mii_media_status; 2157 2158 return; 2159} 2160 2161static void 2162vge_miibus_statchg(dev) 2163 device_t dev; 2164{ 2165 struct vge_softc *sc; 2166 struct mii_data *mii; 2167 struct ifmedia_entry *ife; 2168 2169 sc = device_get_softc(dev); 2170 mii = device_get_softc(sc->vge_miibus); 2171 ife = mii->mii_media.ifm_cur; 2172 2173 /* 2174 * If the user manually selects a media mode, we need to turn 2175 * on the forced MAC mode bit in the DIAGCTL register. If the 2176 * user happens to choose a full duplex mode, we also need to 2177 * set the 'force full duplex' bit. This applies only to 2178 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2179 * mode is disabled, and in 1000baseT mode, full duplex is 2180 * always implied, so we turn on the forced mode bit but leave 2181 * the FDX bit cleared. 2182 */ 2183 2184 switch (IFM_SUBTYPE(ife->ifm_media)) { 2185 case IFM_AUTO: 2186 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2187 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2188 break; 2189 case IFM_1000_T: 2190 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2191 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2192 break; 2193 case IFM_100_TX: 2194 case IFM_10_T: 2195 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2196 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2197 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2198 } else { 2199 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2200 } 2201 break; 2202 default: 2203 device_printf(dev, "unknown media type: %x\n", 2204 IFM_SUBTYPE(ife->ifm_media)); 2205 break; 2206 } 2207 2208 return; 2209} 2210 2211static int 2212vge_ioctl(ifp, command, data) 2213 struct ifnet *ifp; 2214 u_long command; 2215 caddr_t data; 2216{ 2217 struct vge_softc *sc = ifp->if_softc; 2218 struct ifreq *ifr = (struct ifreq *) data; 2219 struct mii_data *mii; 2220 int error = 0; 2221 2222 switch (command) { 2223 case SIOCSIFMTU: 2224 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2225 error = EINVAL; 2226 ifp->if_mtu = ifr->ifr_mtu; 2227 break; 2228 case SIOCSIFFLAGS: 2229 if (ifp->if_flags & IFF_UP) { 2230 if (ifp->if_flags & IFF_RUNNING && 2231 ifp->if_flags & IFF_PROMISC && 2232 !(sc->vge_if_flags & IFF_PROMISC)) { 2233 CSR_SETBIT_1(sc, VGE_RXCTL, 2234 VGE_RXCTL_RX_PROMISC); 2235 vge_setmulti(sc); 2236 } else if (ifp->if_flags & IFF_RUNNING && 2237 !(ifp->if_flags & IFF_PROMISC) && 2238 sc->vge_if_flags & IFF_PROMISC) { 2239 CSR_CLRBIT_1(sc, VGE_RXCTL, 2240 VGE_RXCTL_RX_PROMISC); 2241 vge_setmulti(sc); 2242 } else 2243 vge_init(sc); 2244 } else { 2245 if (ifp->if_flags & IFF_RUNNING) 2246 vge_stop(sc); 2247 } 2248 sc->vge_if_flags = ifp->if_flags; 2249 break; 2250 case SIOCADDMULTI: 2251 case SIOCDELMULTI: 2252 vge_setmulti(sc); 2253 break; 2254 case SIOCGIFMEDIA: 2255 case SIOCSIFMEDIA: 2256 mii = device_get_softc(sc->vge_miibus); 2257 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2258 break; 2259 case SIOCSIFCAP: 2260#ifdef IFCAP_POLLING 2261 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2262#else 2263 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2264#endif 2265 ifp->if_capenable |= 2266#ifdef IFCAP_POLLING 2267 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2268#else 2269 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2270#endif 2271 if (ifp->if_capenable & IFCAP_TXCSUM) 2272 ifp->if_hwassist = VGE_CSUM_FEATURES; 2273 else 2274 ifp->if_hwassist = 0; 2275 if (ifp->if_flags & IFF_RUNNING) 2276 vge_init(sc); 2277 break; 2278 default: 2279 error = ether_ioctl(ifp, command, data); 2280 break; 2281 } 2282 2283 return (error); 2284} 2285 2286static void 2287vge_watchdog(ifp) 2288 struct ifnet *ifp; 2289{ 2290 struct vge_softc *sc; 2291 2292 sc = ifp->if_softc; 2293 VGE_LOCK(sc); 2294 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2295 ifp->if_oerrors++; 2296 2297 vge_txeof(sc); 2298 vge_rxeof(sc); 2299 2300 vge_init(sc); 2301 2302 VGE_UNLOCK(sc); 2303 2304 return; 2305} 2306 2307/* 2308 * Stop the adapter and free any mbufs allocated to the 2309 * RX and TX lists. 2310 */ 2311static void 2312vge_stop(sc) 2313 struct vge_softc *sc; 2314{ 2315 register int i; 2316 struct ifnet *ifp; 2317 2318 VGE_LOCK(sc); 2319 ifp = &sc->arpcom.ac_if; 2320 ifp->if_timer = 0; 2321 2322 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2323#ifdef DEVICE_POLLING 2324 ether_poll_deregister(ifp); 2325#endif /* DEVICE_POLLING */ 2326 2327 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2328 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2329 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2330 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2331 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2332 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2333 2334 if (sc->vge_head != NULL) { 2335 m_freem(sc->vge_head); 2336 sc->vge_head = sc->vge_tail = NULL; 2337 } 2338 2339 /* Free the TX list buffers. */ 2340 2341 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2342 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2343 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2344 sc->vge_ldata.vge_tx_dmamap[i]); 2345 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2346 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2347 } 2348 } 2349 2350 /* Free the RX list buffers. */ 2351 2352 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2353 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2354 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2355 sc->vge_ldata.vge_rx_dmamap[i]); 2356 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2357 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2358 } 2359 } 2360 2361 VGE_UNLOCK(sc); 2362 2363 return; 2364} 2365 2366/* 2367 * Device suspend routine. Stop the interface and save some PCI 2368 * settings in case the BIOS doesn't restore them properly on 2369 * resume. 2370 */ 2371static int 2372vge_suspend(dev) 2373 device_t dev; 2374{ 2375 struct vge_softc *sc; 2376 int i; 2377 2378 sc = device_get_softc(dev); 2379 2380 vge_stop(sc); 2381 2382 for (i = 0; i < 5; i++) 2383 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2384 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2385 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2386 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2387 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2388 2389 sc->suspended = 1; 2390 2391 return (0); 2392} 2393 2394/* 2395 * Device resume routine. Restore some PCI settings in case the BIOS 2396 * doesn't, re-enable busmastering, and restart the interface if 2397 * appropriate. 2398 */ 2399static int 2400vge_resume(dev) 2401 device_t dev; 2402{ 2403 struct vge_softc *sc; 2404 struct ifnet *ifp; 2405 int i; 2406 2407 sc = device_get_softc(dev); 2408 ifp = &sc->arpcom.ac_if; 2409 2410 /* better way to do this? */ 2411 for (i = 0; i < 5; i++) 2412 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2413 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2414 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2415 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2416 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2417 2418 /* reenable busmastering */ 2419 pci_enable_busmaster(dev); 2420 pci_enable_io(dev, SYS_RES_MEMORY); 2421 2422 /* reinitialize interface if necessary */ 2423 if (ifp->if_flags & IFF_UP) 2424 vge_init(sc); 2425 2426 sc->suspended = 0; 2427 2428 return (0); 2429} 2430 2431/* 2432 * Stop all chip I/O so that the kernel's probe routines don't 2433 * get confused by errant DMAs when rebooting. 2434 */ 2435static void 2436vge_shutdown(dev) 2437 device_t dev; 2438{ 2439 struct vge_softc *sc; 2440 2441 sc = device_get_softc(dev); 2442 2443 vge_stop(sc); 2444} 2445