1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
31 *
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
38 *
39 */
40
41/*
42 * TODO:
43 * 1) command failures are not recovered correctly
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD$");
48
49#include <sys/stdint.h>
50#include <sys/stddef.h>
51#include <sys/param.h>
52#include <sys/queue.h>
53#include <sys/types.h>
54#include <sys/systm.h>
55#include <sys/kernel.h>
56#include <sys/bus.h>
57#include <sys/module.h>
58#include <sys/lock.h>
59#include <sys/mutex.h>
60#include <sys/condvar.h>
61#include <sys/sysctl.h>
62#include <sys/sx.h>
63#include <sys/unistd.h>
64#include <sys/callout.h>
65#include <sys/malloc.h>
66#include <sys/priv.h>
67
68#include <dev/usb/usb.h>
69#include <dev/usb/usbdi.h>
70
71#define	USB_DEBUG_VAR ehcidebug
72
73#include <dev/usb/usb_core.h>
74#include <dev/usb/usb_debug.h>
75#include <dev/usb/usb_busdma.h>
76#include <dev/usb/usb_process.h>
77#include <dev/usb/usb_transfer.h>
78#include <dev/usb/usb_device.h>
79#include <dev/usb/usb_hub.h>
80#include <dev/usb/usb_util.h>
81
82#include <dev/usb/usb_controller.h>
83#include <dev/usb/usb_bus.h>
84#include <dev/usb/controller/ehci.h>
85#include <dev/usb/controller/ehcireg.h>
86
87#define	EHCI_BUS2SC(bus) \
88   ((ehci_softc_t *)(((uint8_t *)(bus)) - \
89    ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
90
91#ifdef USB_DEBUG
92static int ehcidebug = 0;
93static int ehcinohighspeed = 0;
94static int ehciiaadbug = 0;
95static int ehcilostintrbug = 0;
96
97static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
98SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
99    &ehcidebug, 0, "Debug level");
100TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
101SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW | CTLFLAG_TUN,
102    &ehcinohighspeed, 0, "Disable High Speed USB");
103TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
104SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW | CTLFLAG_TUN,
105    &ehciiaadbug, 0, "Enable doorbell bug workaround");
106TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
107SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW | CTLFLAG_TUN,
108    &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
109TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
110
111
112static void ehci_dump_regs(ehci_softc_t *sc);
113static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
114
115#endif
116
117#define	EHCI_INTR_ENDPT 1
118
119extern struct usb_bus_methods ehci_bus_methods;
120extern struct usb_pipe_methods ehci_device_bulk_methods;
121extern struct usb_pipe_methods ehci_device_ctrl_methods;
122extern struct usb_pipe_methods ehci_device_intr_methods;
123extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
124extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
125
126static void ehci_do_poll(struct usb_bus *);
127static void ehci_device_done(struct usb_xfer *, usb_error_t);
128static uint8_t ehci_check_transfer(struct usb_xfer *);
129static void ehci_timeout(void *);
130static void ehci_poll_timeout(void *);
131
132static void ehci_root_intr(ehci_softc_t *sc);
133
134struct ehci_std_temp {
135	ehci_softc_t *sc;
136	struct usb_page_cache *pc;
137	ehci_qtd_t *td;
138	ehci_qtd_t *td_next;
139	uint32_t average;
140	uint32_t qtd_status;
141	uint32_t len;
142	uint16_t max_frame_size;
143	uint8_t	shortpkt;
144	uint8_t	auto_data_toggle;
145	uint8_t	setup_alt_next;
146	uint8_t	last_frame;
147};
148
149void
150ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
151{
152	ehci_softc_t *sc = EHCI_BUS2SC(bus);
153	uint32_t i;
154
155	cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
156	    sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
157
158	cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
159	    sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
160
161	cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
162	    sizeof(ehci_qh_t), EHCI_QH_ALIGN);
163
164	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
165		cb(bus, sc->sc_hw.intr_start_pc + i,
166		    sc->sc_hw.intr_start_pg + i,
167		    sizeof(ehci_qh_t), EHCI_QH_ALIGN);
168	}
169
170	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
171		cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
172		    sc->sc_hw.isoc_hs_start_pg + i,
173		    sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
174	}
175
176	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
177		cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
178		    sc->sc_hw.isoc_fs_start_pg + i,
179		    sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
180	}
181}
182
183usb_error_t
184ehci_reset(ehci_softc_t *sc)
185{
186	uint32_t hcr;
187	int i;
188
189	EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
190	for (i = 0; i < 100; i++) {
191		usb_pause_mtx(NULL, hz / 128);
192		hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
193		if (!hcr) {
194			if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
195				/*
196				 * Force USBMODE as requested.  Controllers
197				 * may have multiple operating modes.
198				 */
199				uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
200				if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
201					usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
202					device_printf(sc->sc_bus.bdev,
203					    "set host controller mode\n");
204				}
205				if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
206					usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
207					device_printf(sc->sc_bus.bdev,
208					    "set big-endian mode\n");
209				}
210				EOWRITE4(sc,  EHCI_USBMODE, usbmode);
211			}
212			return (0);
213		}
214	}
215	device_printf(sc->sc_bus.bdev, "Reset timeout\n");
216	return (USB_ERR_IOERROR);
217}
218
219static usb_error_t
220ehci_hcreset(ehci_softc_t *sc)
221{
222	uint32_t hcr;
223	int i;
224
225	EOWRITE4(sc, EHCI_USBCMD, 0);	/* Halt controller */
226	for (i = 0; i < 100; i++) {
227		usb_pause_mtx(NULL, hz / 128);
228		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
229		if (hcr)
230			break;
231	}
232	if (!hcr)
233		/*
234                 * Fall through and try reset anyway even though
235                 * Table 2-9 in the EHCI spec says this will result
236                 * in undefined behavior.
237                 */
238		device_printf(sc->sc_bus.bdev, "stop timeout\n");
239
240	return (ehci_reset(sc));
241}
242
243static int
244ehci_init_sub(struct ehci_softc *sc)
245{
246	struct usb_page_search buf_res;
247	uint32_t cparams;
248  	uint32_t hcr;
249	uint8_t i;
250
251	cparams = EREAD4(sc, EHCI_HCCPARAMS);
252
253	DPRINTF("cparams=0x%x\n", cparams);
254
255	if (EHCI_HCC_64BIT(cparams)) {
256		DPRINTF("HCC uses 64-bit structures\n");
257
258		/* MUST clear segment register if 64 bit capable */
259		EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
260	}
261
262	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
263	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
264
265	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
266	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
267
268	/* enable interrupts */
269	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
270
271	/* turn on controller */
272	EOWRITE4(sc, EHCI_USBCMD,
273	    EHCI_CMD_ITC_1 |		/* 1 microframes interrupt delay */
274	    (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
275	    EHCI_CMD_ASE |
276	    EHCI_CMD_PSE |
277	    EHCI_CMD_RS);
278
279	/* Take over port ownership */
280	EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
281
282	for (i = 0; i < 100; i++) {
283		usb_pause_mtx(NULL, hz / 128);
284		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
285		if (!hcr) {
286			break;
287		}
288	}
289	if (hcr) {
290		device_printf(sc->sc_bus.bdev, "Run timeout\n");
291		return (USB_ERR_IOERROR);
292	}
293	return (USB_ERR_NORMAL_COMPLETION);
294}
295
296usb_error_t
297ehci_init(ehci_softc_t *sc)
298{
299	struct usb_page_search buf_res;
300	uint32_t version;
301	uint32_t sparams;
302	uint16_t i;
303	uint16_t x;
304	uint16_t y;
305	uint16_t bit;
306	usb_error_t err = 0;
307
308	DPRINTF("start\n");
309
310	usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
311	usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
312
313	sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
314
315#ifdef USB_DEBUG
316	if (ehciiaadbug)
317		sc->sc_flags |= EHCI_SCFLG_IAADBUG;
318	if (ehcilostintrbug)
319		sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
320	if (ehcidebug > 2) {
321		ehci_dump_regs(sc);
322	}
323#endif
324
325	version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
326	device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
327	    version >> 8, version & 0xff);
328
329	sparams = EREAD4(sc, EHCI_HCSPARAMS);
330	DPRINTF("sparams=0x%x\n", sparams);
331
332	sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
333	sc->sc_bus.usbrev = USB_REV_2_0;
334
335	if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) {
336		/* Reset the controller */
337		DPRINTF("%s: resetting\n",
338		    device_get_nameunit(sc->sc_bus.bdev));
339
340		err = ehci_hcreset(sc);
341		if (err) {
342			device_printf(sc->sc_bus.bdev, "reset timeout\n");
343			return (err);
344		}
345	}
346
347	/*
348	 * use current frame-list-size selection 0: 1024*4 bytes 1:  512*4
349	 * bytes 2:  256*4 bytes 3:      unknown
350	 */
351	if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
352		device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
353		return (USB_ERR_IOERROR);
354	}
355	/* set up the bus struct */
356	sc->sc_bus.methods = &ehci_bus_methods;
357
358	sc->sc_eintrs = EHCI_NORMAL_INTRS;
359
360	if (1) {
361		struct ehci_qh_sub *qh;
362
363		usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
364
365		qh = buf_res.buffer;
366
367		sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
368
369		/* init terminate TD */
370		qh->qtd_next =
371		    htohc32(sc, EHCI_LINK_TERMINATE);
372		qh->qtd_altnext =
373		    htohc32(sc, EHCI_LINK_TERMINATE);
374		qh->qtd_status =
375		    htohc32(sc, EHCI_QTD_HALTED);
376	}
377
378	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
379		ehci_qh_t *qh;
380
381		usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
382
383		qh = buf_res.buffer;
384
385		/* initialize page cache pointer */
386
387		qh->page_cache = sc->sc_hw.intr_start_pc + i;
388
389		/* store a pointer to queue head */
390
391		sc->sc_intr_p_last[i] = qh;
392
393		qh->qh_self =
394		    htohc32(sc, buf_res.physaddr) |
395		    htohc32(sc, EHCI_LINK_QH);
396
397		qh->qh_endp =
398		    htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
399		qh->qh_endphub =
400		    htohc32(sc, EHCI_QH_SET_MULT(1));
401		qh->qh_curqtd = 0;
402
403		qh->qh_qtd.qtd_next =
404		    htohc32(sc, EHCI_LINK_TERMINATE);
405		qh->qh_qtd.qtd_altnext =
406		    htohc32(sc, EHCI_LINK_TERMINATE);
407		qh->qh_qtd.qtd_status =
408		    htohc32(sc, EHCI_QTD_HALTED);
409	}
410
411	/*
412	 * the QHs are arranged to give poll intervals that are
413	 * powers of 2 times 1ms
414	 */
415	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
416	while (bit) {
417		x = bit;
418		while (x & bit) {
419			ehci_qh_t *qh_x;
420			ehci_qh_t *qh_y;
421
422			y = (x ^ bit) | (bit / 2);
423
424			qh_x = sc->sc_intr_p_last[x];
425			qh_y = sc->sc_intr_p_last[y];
426
427			/*
428			 * the next QH has half the poll interval
429			 */
430			qh_x->qh_link = qh_y->qh_self;
431
432			x++;
433		}
434		bit >>= 1;
435	}
436
437	if (1) {
438		ehci_qh_t *qh;
439
440		qh = sc->sc_intr_p_last[0];
441
442		/* the last (1ms) QH terminates */
443		qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
444	}
445	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
446		ehci_sitd_t *sitd;
447		ehci_itd_t *itd;
448
449		usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
450
451		sitd = buf_res.buffer;
452
453		/* initialize page cache pointer */
454
455		sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
456
457		/* store a pointer to the transfer descriptor */
458
459		sc->sc_isoc_fs_p_last[i] = sitd;
460
461		/* initialize full speed isochronous */
462
463		sitd->sitd_self =
464		    htohc32(sc, buf_res.physaddr) |
465		    htohc32(sc, EHCI_LINK_SITD);
466
467		sitd->sitd_back =
468		    htohc32(sc, EHCI_LINK_TERMINATE);
469
470		sitd->sitd_next =
471		    sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
472
473
474		usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
475
476		itd = buf_res.buffer;
477
478		/* initialize page cache pointer */
479
480		itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
481
482		/* store a pointer to the transfer descriptor */
483
484		sc->sc_isoc_hs_p_last[i] = itd;
485
486		/* initialize high speed isochronous */
487
488		itd->itd_self =
489		    htohc32(sc, buf_res.physaddr) |
490		    htohc32(sc, EHCI_LINK_ITD);
491
492		itd->itd_next =
493		    sitd->sitd_self;
494	}
495
496	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
497
498	if (1) {
499		uint32_t *pframes;
500
501		pframes = buf_res.buffer;
502
503		/*
504		 * execution order:
505		 * pframes -> high speed isochronous ->
506		 *    full speed isochronous -> interrupt QH's
507		 */
508		for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
509			pframes[i] = sc->sc_isoc_hs_p_last
510			    [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
511		}
512	}
513	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
514
515	if (1) {
516
517		ehci_qh_t *qh;
518
519		qh = buf_res.buffer;
520
521		/* initialize page cache pointer */
522
523		qh->page_cache = &sc->sc_hw.async_start_pc;
524
525		/* store a pointer to the queue head */
526
527		sc->sc_async_p_last = qh;
528
529		/* init dummy QH that starts the async list */
530
531		qh->qh_self =
532		    htohc32(sc, buf_res.physaddr) |
533		    htohc32(sc, EHCI_LINK_QH);
534
535		/* fill the QH */
536		qh->qh_endp =
537		    htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
538		qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
539		qh->qh_link = qh->qh_self;
540		qh->qh_curqtd = 0;
541
542		/* fill the overlay qTD */
543		qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
544		qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
545		qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
546	}
547	/* flush all cache into memory */
548
549	usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
550
551#ifdef USB_DEBUG
552	if (ehcidebug) {
553		ehci_dump_sqh(sc, sc->sc_async_p_last);
554	}
555#endif
556
557	/* finial setup */
558 	err = ehci_init_sub(sc);
559
560	if (!err) {
561		/* catch any lost interrupts */
562		ehci_do_poll(&sc->sc_bus);
563	}
564	return (err);
565}
566
567/*
568 * shut down the controller when the system is going down
569 */
570void
571ehci_detach(ehci_softc_t *sc)
572{
573	USB_BUS_LOCK(&sc->sc_bus);
574
575	usb_callout_stop(&sc->sc_tmo_pcd);
576	usb_callout_stop(&sc->sc_tmo_poll);
577
578	EOWRITE4(sc, EHCI_USBINTR, 0);
579	USB_BUS_UNLOCK(&sc->sc_bus);
580
581	if (ehci_hcreset(sc)) {
582		DPRINTF("reset failed!\n");
583	}
584
585	/* XXX let stray task complete */
586	usb_pause_mtx(NULL, hz / 20);
587
588	usb_callout_drain(&sc->sc_tmo_pcd);
589	usb_callout_drain(&sc->sc_tmo_poll);
590}
591
592static void
593ehci_suspend(ehci_softc_t *sc)
594{
595	DPRINTF("stopping the HC\n");
596
597	/* reset HC */
598	ehci_hcreset(sc);
599}
600
601static void
602ehci_resume(ehci_softc_t *sc)
603{
604	/* reset HC */
605	ehci_hcreset(sc);
606
607	/* setup HC */
608	ehci_init_sub(sc);
609
610	/* catch any lost interrupts */
611	ehci_do_poll(&sc->sc_bus);
612}
613
614#ifdef USB_DEBUG
615static void
616ehci_dump_regs(ehci_softc_t *sc)
617{
618	uint32_t i;
619
620	i = EOREAD4(sc, EHCI_USBCMD);
621	printf("cmd=0x%08x\n", i);
622
623	if (i & EHCI_CMD_ITC_1)
624		printf(" EHCI_CMD_ITC_1\n");
625	if (i & EHCI_CMD_ITC_2)
626		printf(" EHCI_CMD_ITC_2\n");
627	if (i & EHCI_CMD_ITC_4)
628		printf(" EHCI_CMD_ITC_4\n");
629	if (i & EHCI_CMD_ITC_8)
630		printf(" EHCI_CMD_ITC_8\n");
631	if (i & EHCI_CMD_ITC_16)
632		printf(" EHCI_CMD_ITC_16\n");
633	if (i & EHCI_CMD_ITC_32)
634		printf(" EHCI_CMD_ITC_32\n");
635	if (i & EHCI_CMD_ITC_64)
636		printf(" EHCI_CMD_ITC_64\n");
637	if (i & EHCI_CMD_ASPME)
638		printf(" EHCI_CMD_ASPME\n");
639	if (i & EHCI_CMD_ASPMC)
640		printf(" EHCI_CMD_ASPMC\n");
641	if (i & EHCI_CMD_LHCR)
642		printf(" EHCI_CMD_LHCR\n");
643	if (i & EHCI_CMD_IAAD)
644		printf(" EHCI_CMD_IAAD\n");
645	if (i & EHCI_CMD_ASE)
646		printf(" EHCI_CMD_ASE\n");
647	if (i & EHCI_CMD_PSE)
648		printf(" EHCI_CMD_PSE\n");
649	if (i & EHCI_CMD_FLS_M)
650		printf(" EHCI_CMD_FLS_M\n");
651	if (i & EHCI_CMD_HCRESET)
652		printf(" EHCI_CMD_HCRESET\n");
653	if (i & EHCI_CMD_RS)
654		printf(" EHCI_CMD_RS\n");
655
656	i = EOREAD4(sc, EHCI_USBSTS);
657
658	printf("sts=0x%08x\n", i);
659
660	if (i & EHCI_STS_ASS)
661		printf(" EHCI_STS_ASS\n");
662	if (i & EHCI_STS_PSS)
663		printf(" EHCI_STS_PSS\n");
664	if (i & EHCI_STS_REC)
665		printf(" EHCI_STS_REC\n");
666	if (i & EHCI_STS_HCH)
667		printf(" EHCI_STS_HCH\n");
668	if (i & EHCI_STS_IAA)
669		printf(" EHCI_STS_IAA\n");
670	if (i & EHCI_STS_HSE)
671		printf(" EHCI_STS_HSE\n");
672	if (i & EHCI_STS_FLR)
673		printf(" EHCI_STS_FLR\n");
674	if (i & EHCI_STS_PCD)
675		printf(" EHCI_STS_PCD\n");
676	if (i & EHCI_STS_ERRINT)
677		printf(" EHCI_STS_ERRINT\n");
678	if (i & EHCI_STS_INT)
679		printf(" EHCI_STS_INT\n");
680
681	printf("ien=0x%08x\n",
682	    EOREAD4(sc, EHCI_USBINTR));
683	printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
684	    EOREAD4(sc, EHCI_FRINDEX),
685	    EOREAD4(sc, EHCI_CTRLDSSEGMENT),
686	    EOREAD4(sc, EHCI_PERIODICLISTBASE),
687	    EOREAD4(sc, EHCI_ASYNCLISTADDR));
688	for (i = 1; i <= sc->sc_noport; i++) {
689		printf("port %d status=0x%08x\n", i,
690		    EOREAD4(sc, EHCI_PORTSC(i)));
691	}
692}
693
694static void
695ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
696{
697	link = hc32toh(sc, link);
698	printf("0x%08x", link);
699	if (link & EHCI_LINK_TERMINATE)
700		printf("<T>");
701	else {
702		printf("<");
703		if (type) {
704			switch (EHCI_LINK_TYPE(link)) {
705			case EHCI_LINK_ITD:
706				printf("ITD");
707				break;
708			case EHCI_LINK_QH:
709				printf("QH");
710				break;
711			case EHCI_LINK_SITD:
712				printf("SITD");
713				break;
714			case EHCI_LINK_FSTN:
715				printf("FSTN");
716				break;
717			}
718		}
719		printf(">");
720	}
721}
722
723static void
724ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
725{
726	uint32_t s;
727
728	printf("  next=");
729	ehci_dump_link(sc, qtd->qtd_next, 0);
730	printf(" altnext=");
731	ehci_dump_link(sc, qtd->qtd_altnext, 0);
732	printf("\n");
733	s = hc32toh(sc, qtd->qtd_status);
734	printf("  status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
735	    s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
736	    EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
737	printf("    cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
738	    EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
739	    (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
740	    (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
741	    (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
742	    (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
743	    (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
744	    (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
745	    (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
746	    (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
747
748	for (s = 0; s < 5; s++) {
749		printf("  buffer[%d]=0x%08x\n", s,
750		    hc32toh(sc, qtd->qtd_buffer[s]));
751	}
752	for (s = 0; s < 5; s++) {
753		printf("  buffer_hi[%d]=0x%08x\n", s,
754		    hc32toh(sc, qtd->qtd_buffer_hi[s]));
755	}
756}
757
758static uint8_t
759ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
760{
761	uint8_t temp;
762
763	usb_pc_cpu_invalidate(sqtd->page_cache);
764	printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
765	ehci_dump_qtd(sc, sqtd);
766	temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
767	return (temp);
768}
769
770static void
771ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
772{
773	uint16_t i;
774	uint8_t stop;
775
776	stop = 0;
777	for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
778		stop = ehci_dump_sqtd(sc, sqtd);
779	}
780	if (sqtd) {
781		printf("dump aborted, too many TDs\n");
782	}
783}
784
785static void
786ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
787{
788	uint32_t endp;
789	uint32_t endphub;
790
791	usb_pc_cpu_invalidate(qh->page_cache);
792	printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
793	printf("  link=");
794	ehci_dump_link(sc, qh->qh_link, 1);
795	printf("\n");
796	endp = hc32toh(sc, qh->qh_endp);
797	printf("  endp=0x%08x\n", endp);
798	printf("    addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
799	    EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
800	    EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
801	    EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
802	printf("    mpl=0x%x ctl=%d nrl=%d\n",
803	    EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
804	    EHCI_QH_GET_NRL(endp));
805	endphub = hc32toh(sc, qh->qh_endphub);
806	printf("  endphub=0x%08x\n", endphub);
807	printf("    smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
808	    EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
809	    EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
810	    EHCI_QH_GET_MULT(endphub));
811	printf("  curqtd=");
812	ehci_dump_link(sc, qh->qh_curqtd, 0);
813	printf("\n");
814	printf("Overlay qTD:\n");
815	ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
816}
817
818static void
819ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
820{
821	usb_pc_cpu_invalidate(sitd->page_cache);
822	printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
823	printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
824	printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
825	    hc32toh(sc, sitd->sitd_portaddr),
826	    (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
827	    ? "in" : "out",
828	    EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
829	    EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
830	    EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
831	    EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
832	printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
833	printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
834	    (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
835	    EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
836	printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
837	    hc32toh(sc, sitd->sitd_back),
838	    hc32toh(sc, sitd->sitd_bp[0]),
839	    hc32toh(sc, sitd->sitd_bp[1]),
840	    hc32toh(sc, sitd->sitd_bp_hi[0]),
841	    hc32toh(sc, sitd->sitd_bp_hi[1]));
842}
843
844static void
845ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
846{
847	usb_pc_cpu_invalidate(itd->page_cache);
848	printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
849	printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
850	printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
851	    (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
852	printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
853	    (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
854	printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
855	    (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
856	printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
857	    (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
858	printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
859	    (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
860	printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
861	    (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
862	printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
863	    (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
864	printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
865	    (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
866	printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
867	printf("  addr=0x%02x; endpt=0x%01x\n",
868	    EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
869	    EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
870	printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
871	printf(" dir=%s; mpl=0x%02x\n",
872	    (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
873	    EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
874	printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
875	    hc32toh(sc, itd->itd_bp[2]),
876	    hc32toh(sc, itd->itd_bp[3]),
877	    hc32toh(sc, itd->itd_bp[4]),
878	    hc32toh(sc, itd->itd_bp[5]),
879	    hc32toh(sc, itd->itd_bp[6]));
880	printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
881	    "       0x%08x,0x%08x,0x%08x\n",
882	    hc32toh(sc, itd->itd_bp_hi[0]),
883	    hc32toh(sc, itd->itd_bp_hi[1]),
884	    hc32toh(sc, itd->itd_bp_hi[2]),
885	    hc32toh(sc, itd->itd_bp_hi[3]),
886	    hc32toh(sc, itd->itd_bp_hi[4]),
887	    hc32toh(sc, itd->itd_bp_hi[5]),
888	    hc32toh(sc, itd->itd_bp_hi[6]));
889}
890
891static void
892ehci_dump_isoc(ehci_softc_t *sc)
893{
894	ehci_itd_t *itd;
895	ehci_sitd_t *sitd;
896	uint16_t max = 1000;
897	uint16_t pos;
898
899	pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
900	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
901
902	printf("%s: isochronous dump from frame 0x%03x:\n",
903	    __FUNCTION__, pos);
904
905	itd = sc->sc_isoc_hs_p_last[pos];
906	sitd = sc->sc_isoc_fs_p_last[pos];
907
908	while (itd && max && max--) {
909		ehci_dump_itd(sc, itd);
910		itd = itd->prev;
911	}
912
913	while (sitd && max && max--) {
914		ehci_dump_sitd(sc, sitd);
915		sitd = sitd->prev;
916	}
917}
918
919#endif
920
921static void
922ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
923{
924	/* check for early completion */
925	if (ehci_check_transfer(xfer)) {
926		return;
927	}
928	/* put transfer on interrupt queue */
929	usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
930
931	/* start timeout, if any */
932	if (xfer->timeout != 0) {
933		usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
934	}
935}
936
937#define	EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
938static ehci_sitd_t *
939_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
940{
941	DPRINTFN(11, "%p to %p\n", std, last);
942
943	/* (sc->sc_bus.mtx) must be locked */
944
945	std->next = last->next;
946	std->sitd_next = last->sitd_next;
947
948	std->prev = last;
949
950	usb_pc_cpu_flush(std->page_cache);
951
952	/*
953	 * the last->next->prev is never followed: std->next->prev = std;
954	 */
955	last->next = std;
956	last->sitd_next = std->sitd_self;
957
958	usb_pc_cpu_flush(last->page_cache);
959
960	return (std);
961}
962
963#define	EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
964static ehci_itd_t *
965_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
966{
967	DPRINTFN(11, "%p to %p\n", std, last);
968
969	/* (sc->sc_bus.mtx) must be locked */
970
971	std->next = last->next;
972	std->itd_next = last->itd_next;
973
974	std->prev = last;
975
976	usb_pc_cpu_flush(std->page_cache);
977
978	/*
979	 * the last->next->prev is never followed: std->next->prev = std;
980	 */
981	last->next = std;
982	last->itd_next = std->itd_self;
983
984	usb_pc_cpu_flush(last->page_cache);
985
986	return (std);
987}
988
989#define	EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
990static ehci_qh_t *
991_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
992{
993	DPRINTFN(11, "%p to %p\n", sqh, last);
994
995	if (sqh->prev != NULL) {
996		/* should not happen */
997		DPRINTFN(0, "QH already linked!\n");
998		return (last);
999	}
1000	/* (sc->sc_bus.mtx) must be locked */
1001
1002	sqh->next = last->next;
1003	sqh->qh_link = last->qh_link;
1004
1005	sqh->prev = last;
1006
1007	usb_pc_cpu_flush(sqh->page_cache);
1008
1009	/*
1010	 * the last->next->prev is never followed: sqh->next->prev = sqh;
1011	 */
1012
1013	last->next = sqh;
1014	last->qh_link = sqh->qh_self;
1015
1016	usb_pc_cpu_flush(last->page_cache);
1017
1018	return (sqh);
1019}
1020
1021#define	EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1022static ehci_sitd_t *
1023_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1024{
1025	DPRINTFN(11, "%p from %p\n", std, last);
1026
1027	/* (sc->sc_bus.mtx) must be locked */
1028
1029	std->prev->next = std->next;
1030	std->prev->sitd_next = std->sitd_next;
1031
1032	usb_pc_cpu_flush(std->prev->page_cache);
1033
1034	if (std->next) {
1035		std->next->prev = std->prev;
1036		usb_pc_cpu_flush(std->next->page_cache);
1037	}
1038	return ((last == std) ? std->prev : last);
1039}
1040
1041#define	EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1042static ehci_itd_t *
1043_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1044{
1045	DPRINTFN(11, "%p from %p\n", std, last);
1046
1047	/* (sc->sc_bus.mtx) must be locked */
1048
1049	std->prev->next = std->next;
1050	std->prev->itd_next = std->itd_next;
1051
1052	usb_pc_cpu_flush(std->prev->page_cache);
1053
1054	if (std->next) {
1055		std->next->prev = std->prev;
1056		usb_pc_cpu_flush(std->next->page_cache);
1057	}
1058	return ((last == std) ? std->prev : last);
1059}
1060
1061#define	EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1062static ehci_qh_t *
1063_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1064{
1065	DPRINTFN(11, "%p from %p\n", sqh, last);
1066
1067	/* (sc->sc_bus.mtx) must be locked */
1068
1069	/* only remove if not removed from a queue */
1070	if (sqh->prev) {
1071
1072		sqh->prev->next = sqh->next;
1073		sqh->prev->qh_link = sqh->qh_link;
1074
1075		usb_pc_cpu_flush(sqh->prev->page_cache);
1076
1077		if (sqh->next) {
1078			sqh->next->prev = sqh->prev;
1079			usb_pc_cpu_flush(sqh->next->page_cache);
1080		}
1081		last = ((last == sqh) ? sqh->prev : last);
1082
1083		sqh->prev = 0;
1084
1085		usb_pc_cpu_flush(sqh->page_cache);
1086	}
1087	return (last);
1088}
1089
1090static void
1091ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1092{
1093	uint16_t rem;
1094	uint8_t dt;
1095
1096	/* count number of full packets */
1097	dt = (actlen / xfer->max_packet_size) & 1;
1098
1099	/* compute remainder */
1100	rem = actlen % xfer->max_packet_size;
1101
1102	if (rem > 0)
1103		dt ^= 1;	/* short packet at the end */
1104	else if (actlen != xlen)
1105		dt ^= 1;	/* zero length packet at the end */
1106	else if (xlen == 0)
1107		dt ^= 1;	/* zero length transfer */
1108
1109	xfer->endpoint->toggle_next ^= dt;
1110}
1111
1112static usb_error_t
1113ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1114{
1115	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1116	ehci_qtd_t *td;
1117	ehci_qtd_t *td_alt_next;
1118	uint32_t status;
1119	uint16_t len;
1120
1121	td = xfer->td_transfer_cache;
1122	td_alt_next = td->alt_next;
1123
1124	if (xfer->aframes != xfer->nframes) {
1125		usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1126	}
1127	while (1) {
1128
1129		usb_pc_cpu_invalidate(td->page_cache);
1130		status = hc32toh(sc, td->qtd_status);
1131
1132		len = EHCI_QTD_GET_BYTES(status);
1133
1134		/*
1135	         * Verify the status length and
1136		 * add the length to "frlengths[]":
1137	         */
1138		if (len > td->len) {
1139			/* should not happen */
1140			DPRINTF("Invalid status length, "
1141			    "0x%04x/0x%04x bytes\n", len, td->len);
1142			status |= EHCI_QTD_HALTED;
1143		} else if (xfer->aframes != xfer->nframes) {
1144			xfer->frlengths[xfer->aframes] += td->len - len;
1145			/* manually update data toggle */
1146			ehci_data_toggle_update(xfer, td->len - len, td->len);
1147		}
1148
1149		/* Check for last transfer */
1150		if (((void *)td) == xfer->td_transfer_last) {
1151			td = NULL;
1152			break;
1153		}
1154		/* Check for transfer error */
1155		if (status & EHCI_QTD_HALTED) {
1156			/* the transfer is finished */
1157			td = NULL;
1158			break;
1159		}
1160		/* Check for short transfer */
1161		if (len > 0) {
1162			if (xfer->flags_int.short_frames_ok) {
1163				/* follow alt next */
1164				td = td->alt_next;
1165			} else {
1166				/* the transfer is finished */
1167				td = NULL;
1168			}
1169			break;
1170		}
1171		td = td->obj_next;
1172
1173		if (td->alt_next != td_alt_next) {
1174			/* this USB frame is complete */
1175			break;
1176		}
1177	}
1178
1179	/* update transfer cache */
1180
1181	xfer->td_transfer_cache = td;
1182
1183#ifdef USB_DEBUG
1184	if (status & EHCI_QTD_STATERRS) {
1185		DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1186		    "status=%s%s%s%s%s%s%s%s\n",
1187		    xfer->address, xfer->endpointno, xfer->aframes,
1188		    (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1189		    (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1190		    (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1191		    (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1192		    (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1193		    (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1194		    (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1195		    (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1196	}
1197#endif
1198	if (status & EHCI_QTD_HALTED) {
1199		if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1200		    (xfer->xroot->udev->address != 0)) {
1201			/* try to separate I/O errors from STALL */
1202			if (EHCI_QTD_GET_CERR(status) == 0)
1203				return (USB_ERR_IOERROR);
1204		}
1205		return (USB_ERR_STALLED);
1206	}
1207	return (USB_ERR_NORMAL_COMPLETION);
1208}
1209
1210static void
1211ehci_non_isoc_done(struct usb_xfer *xfer)
1212{
1213	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1214	ehci_qh_t *qh;
1215	uint32_t status;
1216	usb_error_t err = 0;
1217
1218	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1219	    xfer, xfer->endpoint);
1220
1221#ifdef USB_DEBUG
1222	if (ehcidebug > 10) {
1223		ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1224
1225		ehci_dump_sqtds(sc, xfer->td_transfer_first);
1226	}
1227#endif
1228
1229	/* extract data toggle directly from the QH's overlay area */
1230
1231	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1232
1233	usb_pc_cpu_invalidate(qh->page_cache);
1234
1235	status = hc32toh(sc, qh->qh_qtd.qtd_status);
1236
1237	/* reset scanner */
1238
1239	xfer->td_transfer_cache = xfer->td_transfer_first;
1240
1241	if (xfer->flags_int.control_xfr) {
1242
1243		if (xfer->flags_int.control_hdr) {
1244
1245			err = ehci_non_isoc_done_sub(xfer);
1246		}
1247		xfer->aframes = 1;
1248
1249		if (xfer->td_transfer_cache == NULL) {
1250			goto done;
1251		}
1252	}
1253	while (xfer->aframes != xfer->nframes) {
1254
1255		err = ehci_non_isoc_done_sub(xfer);
1256		xfer->aframes++;
1257
1258		if (xfer->td_transfer_cache == NULL) {
1259			goto done;
1260		}
1261	}
1262
1263	if (xfer->flags_int.control_xfr &&
1264	    !xfer->flags_int.control_act) {
1265
1266		err = ehci_non_isoc_done_sub(xfer);
1267	}
1268done:
1269	ehci_device_done(xfer, err);
1270}
1271
1272/*------------------------------------------------------------------------*
1273 *	ehci_check_transfer
1274 *
1275 * Return values:
1276 *    0: USB transfer is not finished
1277 * Else: USB transfer is finished
1278 *------------------------------------------------------------------------*/
1279static uint8_t
1280ehci_check_transfer(struct usb_xfer *xfer)
1281{
1282	struct usb_pipe_methods *methods = xfer->endpoint->methods;
1283	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1284
1285	uint32_t status;
1286
1287	DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1288
1289	if (methods == &ehci_device_isoc_fs_methods) {
1290		ehci_sitd_t *td;
1291
1292		/* isochronous full speed transfer */
1293
1294		td = xfer->td_transfer_last;
1295		usb_pc_cpu_invalidate(td->page_cache);
1296		status = hc32toh(sc, td->sitd_status);
1297
1298		/* also check if first is complete */
1299
1300		td = xfer->td_transfer_first;
1301		usb_pc_cpu_invalidate(td->page_cache);
1302		status |= hc32toh(sc, td->sitd_status);
1303
1304		if (!(status & EHCI_SITD_ACTIVE)) {
1305			ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1306			goto transferred;
1307		}
1308	} else if (methods == &ehci_device_isoc_hs_methods) {
1309		ehci_itd_t *td;
1310
1311		/* isochronous high speed transfer */
1312
1313		/* check last transfer */
1314		td = xfer->td_transfer_last;
1315		usb_pc_cpu_invalidate(td->page_cache);
1316		status = td->itd_status[0];
1317		status |= td->itd_status[1];
1318		status |= td->itd_status[2];
1319		status |= td->itd_status[3];
1320		status |= td->itd_status[4];
1321		status |= td->itd_status[5];
1322		status |= td->itd_status[6];
1323		status |= td->itd_status[7];
1324
1325		/* also check first transfer */
1326		td = xfer->td_transfer_first;
1327		usb_pc_cpu_invalidate(td->page_cache);
1328		status |= td->itd_status[0];
1329		status |= td->itd_status[1];
1330		status |= td->itd_status[2];
1331		status |= td->itd_status[3];
1332		status |= td->itd_status[4];
1333		status |= td->itd_status[5];
1334		status |= td->itd_status[6];
1335		status |= td->itd_status[7];
1336
1337		/* if no transactions are active we continue */
1338		if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1339			ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1340			goto transferred;
1341		}
1342	} else {
1343		ehci_qtd_t *td;
1344		ehci_qh_t *qh;
1345
1346		/* non-isochronous transfer */
1347
1348		/*
1349		 * check whether there is an error somewhere in the middle,
1350		 * or whether there was a short packet (SPD and not ACTIVE)
1351		 */
1352		td = xfer->td_transfer_cache;
1353
1354		qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1355
1356		usb_pc_cpu_invalidate(qh->page_cache);
1357
1358		status = hc32toh(sc, qh->qh_qtd.qtd_status);
1359		if (status & EHCI_QTD_ACTIVE) {
1360			/* transfer is pending */
1361			goto done;
1362		}
1363
1364		while (1) {
1365			usb_pc_cpu_invalidate(td->page_cache);
1366			status = hc32toh(sc, td->qtd_status);
1367
1368			/*
1369			 * Check if there is an active TD which
1370			 * indicates that the transfer isn't done.
1371			 */
1372			if (status & EHCI_QTD_ACTIVE) {
1373				/* update cache */
1374				xfer->td_transfer_cache = td;
1375				goto done;
1376			}
1377			/*
1378			 * last transfer descriptor makes the transfer done
1379			 */
1380			if (((void *)td) == xfer->td_transfer_last) {
1381				break;
1382			}
1383			/*
1384			 * any kind of error makes the transfer done
1385			 */
1386			if (status & EHCI_QTD_HALTED) {
1387				break;
1388			}
1389			/*
1390			 * if there is no alternate next transfer, a short
1391			 * packet also makes the transfer done
1392			 */
1393			if (EHCI_QTD_GET_BYTES(status)) {
1394				if (xfer->flags_int.short_frames_ok) {
1395					/* follow alt next */
1396					if (td->alt_next) {
1397						td = td->alt_next;
1398						continue;
1399					}
1400				}
1401				/* transfer is done */
1402				break;
1403			}
1404			td = td->obj_next;
1405		}
1406		ehci_non_isoc_done(xfer);
1407		goto transferred;
1408	}
1409
1410done:
1411	DPRINTFN(13, "xfer=%p is still active\n", xfer);
1412	return (0);
1413
1414transferred:
1415	return (1);
1416}
1417
1418static void
1419ehci_pcd_enable(ehci_softc_t *sc)
1420{
1421	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1422
1423	sc->sc_eintrs |= EHCI_STS_PCD;
1424	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1425
1426	/* acknowledge any PCD interrupt */
1427	EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1428
1429	ehci_root_intr(sc);
1430}
1431
1432static void
1433ehci_interrupt_poll(ehci_softc_t *sc)
1434{
1435	struct usb_xfer *xfer;
1436
1437repeat:
1438	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1439		/*
1440		 * check if transfer is transferred
1441		 */
1442		if (ehci_check_transfer(xfer)) {
1443			/* queue has been modified */
1444			goto repeat;
1445		}
1446	}
1447}
1448
1449/*
1450 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1451 * writing back the qTD status, or miss signalling occasionally under
1452 * heavy load.  If the host machine is too fast, we can miss
1453 * transaction completion - when we scan the active list the
1454 * transaction still seems to be active. This generally exhibits
1455 * itself as a umass stall that never recovers.
1456 *
1457 * We work around this behaviour by setting up this callback after any
1458 * softintr that completes with transactions still pending, giving us
1459 * another chance to check for completion after the writeback has
1460 * taken place.
1461 */
1462static void
1463ehci_poll_timeout(void *arg)
1464{
1465	ehci_softc_t *sc = arg;
1466
1467	DPRINTFN(3, "\n");
1468	ehci_interrupt_poll(sc);
1469}
1470
1471/*------------------------------------------------------------------------*
1472 *	ehci_interrupt - EHCI interrupt handler
1473 *
1474 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1475 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1476 * is present !
1477 *------------------------------------------------------------------------*/
1478void
1479ehci_interrupt(ehci_softc_t *sc)
1480{
1481	uint32_t status;
1482
1483	USB_BUS_LOCK(&sc->sc_bus);
1484
1485	DPRINTFN(16, "real interrupt\n");
1486
1487#ifdef USB_DEBUG
1488	if (ehcidebug > 15) {
1489		ehci_dump_regs(sc);
1490	}
1491#endif
1492
1493	status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1494	if (status == 0) {
1495		/* the interrupt was not for us */
1496		goto done;
1497	}
1498	if (!(status & sc->sc_eintrs)) {
1499		goto done;
1500	}
1501	EOWRITE4(sc, EHCI_USBSTS, status);	/* acknowledge */
1502
1503	status &= sc->sc_eintrs;
1504
1505	if (status & EHCI_STS_HSE) {
1506		printf("%s: unrecoverable error, "
1507		    "controller halted\n", __FUNCTION__);
1508#ifdef USB_DEBUG
1509		ehci_dump_regs(sc);
1510		ehci_dump_isoc(sc);
1511#endif
1512	}
1513	if (status & EHCI_STS_PCD) {
1514		/*
1515		 * Disable PCD interrupt for now, because it will be
1516		 * on until the port has been reset.
1517		 */
1518		sc->sc_eintrs &= ~EHCI_STS_PCD;
1519		EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1520
1521		ehci_root_intr(sc);
1522
1523		/* do not allow RHSC interrupts > 1 per second */
1524		usb_callout_reset(&sc->sc_tmo_pcd, hz,
1525		    (void *)&ehci_pcd_enable, sc);
1526	}
1527	status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1528
1529	if (status != 0) {
1530		/* block unprocessed interrupts */
1531		sc->sc_eintrs &= ~status;
1532		EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1533		printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1534	}
1535	/* poll all the USB transfers */
1536	ehci_interrupt_poll(sc);
1537
1538	if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1539		usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1540		    (void *)&ehci_poll_timeout, sc);
1541	}
1542
1543done:
1544	USB_BUS_UNLOCK(&sc->sc_bus);
1545}
1546
1547/*
1548 * called when a request does not complete
1549 */
1550static void
1551ehci_timeout(void *arg)
1552{
1553	struct usb_xfer *xfer = arg;
1554
1555	DPRINTF("xfer=%p\n", xfer);
1556
1557	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1558
1559	/* transfer is transferred */
1560	ehci_device_done(xfer, USB_ERR_TIMEOUT);
1561}
1562
1563static void
1564ehci_do_poll(struct usb_bus *bus)
1565{
1566	ehci_softc_t *sc = EHCI_BUS2SC(bus);
1567
1568	USB_BUS_LOCK(&sc->sc_bus);
1569	ehci_interrupt_poll(sc);
1570	USB_BUS_UNLOCK(&sc->sc_bus);
1571}
1572
1573static void
1574ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1575{
1576	struct usb_page_search buf_res;
1577	ehci_qtd_t *td;
1578	ehci_qtd_t *td_next;
1579	ehci_qtd_t *td_alt_next;
1580	uint32_t buf_offset;
1581	uint32_t average;
1582	uint32_t len_old;
1583	uint32_t terminate;
1584	uint32_t qtd_altnext;
1585	uint8_t shortpkt_old;
1586	uint8_t precompute;
1587
1588	terminate = temp->sc->sc_terminate_self;
1589	qtd_altnext = temp->sc->sc_terminate_self;
1590	td_alt_next = NULL;
1591	buf_offset = 0;
1592	shortpkt_old = temp->shortpkt;
1593	len_old = temp->len;
1594	precompute = 1;
1595
1596restart:
1597
1598	td = temp->td;
1599	td_next = temp->td_next;
1600
1601	while (1) {
1602
1603		if (temp->len == 0) {
1604
1605			if (temp->shortpkt) {
1606				break;
1607			}
1608			/* send a Zero Length Packet, ZLP, last */
1609
1610			temp->shortpkt = 1;
1611			average = 0;
1612
1613		} else {
1614
1615			average = temp->average;
1616
1617			if (temp->len < average) {
1618				if (temp->len % temp->max_frame_size) {
1619					temp->shortpkt = 1;
1620				}
1621				average = temp->len;
1622			}
1623		}
1624
1625		if (td_next == NULL) {
1626			panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1627		}
1628		/* get next TD */
1629
1630		td = td_next;
1631		td_next = td->obj_next;
1632
1633		/* check if we are pre-computing */
1634
1635		if (precompute) {
1636
1637			/* update remaining length */
1638
1639			temp->len -= average;
1640
1641			continue;
1642		}
1643		/* fill out current TD */
1644
1645		td->qtd_status =
1646		    temp->qtd_status |
1647		    htohc32(temp->sc, EHCI_QTD_IOC |
1648			EHCI_QTD_SET_BYTES(average));
1649
1650		if (average == 0) {
1651
1652			if (temp->auto_data_toggle == 0) {
1653
1654				/* update data toggle, ZLP case */
1655
1656				temp->qtd_status ^=
1657				    htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1658			}
1659			td->len = 0;
1660
1661			/* properly reset reserved fields */
1662			td->qtd_buffer[0] = 0;
1663			td->qtd_buffer[1] = 0;
1664			td->qtd_buffer[2] = 0;
1665			td->qtd_buffer[3] = 0;
1666			td->qtd_buffer[4] = 0;
1667			td->qtd_buffer_hi[0] = 0;
1668			td->qtd_buffer_hi[1] = 0;
1669			td->qtd_buffer_hi[2] = 0;
1670			td->qtd_buffer_hi[3] = 0;
1671			td->qtd_buffer_hi[4] = 0;
1672		} else {
1673
1674			uint8_t x;
1675
1676			if (temp->auto_data_toggle == 0) {
1677
1678				/* update data toggle */
1679
1680				if (((average + temp->max_frame_size - 1) /
1681				    temp->max_frame_size) & 1) {
1682					temp->qtd_status ^=
1683					    htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1684				}
1685			}
1686			td->len = average;
1687
1688			/* update remaining length */
1689
1690			temp->len -= average;
1691
1692			/* fill out buffer pointers */
1693
1694			usbd_get_page(temp->pc, buf_offset, &buf_res);
1695			td->qtd_buffer[0] =
1696			    htohc32(temp->sc, buf_res.physaddr);
1697			td->qtd_buffer_hi[0] = 0;
1698
1699			x = 1;
1700
1701			while (average > EHCI_PAGE_SIZE) {
1702				average -= EHCI_PAGE_SIZE;
1703				buf_offset += EHCI_PAGE_SIZE;
1704				usbd_get_page(temp->pc, buf_offset, &buf_res);
1705				td->qtd_buffer[x] =
1706				    htohc32(temp->sc,
1707				    buf_res.physaddr & (~0xFFF));
1708				td->qtd_buffer_hi[x] = 0;
1709				x++;
1710			}
1711
1712			/*
1713			 * NOTE: The "average" variable is never zero after
1714			 * exiting the loop above !
1715			 *
1716			 * NOTE: We have to subtract one from the offset to
1717			 * ensure that we are computing the physical address
1718			 * of a valid page !
1719			 */
1720			buf_offset += average;
1721			usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1722			td->qtd_buffer[x] =
1723			    htohc32(temp->sc,
1724			    buf_res.physaddr & (~0xFFF));
1725			td->qtd_buffer_hi[x] = 0;
1726
1727			/* properly reset reserved fields */
1728			while (++x < EHCI_QTD_NBUFFERS) {
1729				td->qtd_buffer[x] = 0;
1730				td->qtd_buffer_hi[x] = 0;
1731			}
1732		}
1733
1734		if (td_next) {
1735			/* link the current TD with the next one */
1736			td->qtd_next = td_next->qtd_self;
1737		}
1738		td->qtd_altnext = qtd_altnext;
1739		td->alt_next = td_alt_next;
1740
1741		usb_pc_cpu_flush(td->page_cache);
1742	}
1743
1744	if (precompute) {
1745		precompute = 0;
1746
1747		/* setup alt next pointer, if any */
1748		if (temp->last_frame) {
1749			td_alt_next = NULL;
1750			qtd_altnext = terminate;
1751		} else {
1752			/* we use this field internally */
1753			td_alt_next = td_next;
1754			if (temp->setup_alt_next) {
1755				qtd_altnext = td_next->qtd_self;
1756			} else {
1757				qtd_altnext = terminate;
1758			}
1759		}
1760
1761		/* restore */
1762		temp->shortpkt = shortpkt_old;
1763		temp->len = len_old;
1764		goto restart;
1765	}
1766	temp->td = td;
1767	temp->td_next = td_next;
1768}
1769
1770static void
1771ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1772{
1773	struct ehci_std_temp temp;
1774	struct usb_pipe_methods *methods;
1775	ehci_qh_t *qh;
1776	ehci_qtd_t *td;
1777	uint32_t qh_endp;
1778	uint32_t qh_endphub;
1779	uint32_t x;
1780
1781	DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1782	    xfer->address, UE_GET_ADDR(xfer->endpointno),
1783	    xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1784
1785	temp.average = xfer->max_hc_frame_size;
1786	temp.max_frame_size = xfer->max_frame_size;
1787	temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1788
1789	/* toggle the DMA set we are using */
1790	xfer->flags_int.curr_dma_set ^= 1;
1791
1792	/* get next DMA set */
1793	td = xfer->td_start[xfer->flags_int.curr_dma_set];
1794
1795	xfer->td_transfer_first = td;
1796	xfer->td_transfer_cache = td;
1797
1798	temp.td = NULL;
1799	temp.td_next = td;
1800	temp.qtd_status = 0;
1801	temp.last_frame = 0;
1802	temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1803
1804	if (xfer->flags_int.control_xfr) {
1805		if (xfer->endpoint->toggle_next) {
1806			/* DATA1 is next */
1807			temp.qtd_status |=
1808			    htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1809		}
1810		temp.auto_data_toggle = 0;
1811	} else {
1812		temp.auto_data_toggle = 1;
1813	}
1814
1815	if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1816	    (xfer->xroot->udev->address != 0)) {
1817		/* max 3 retries */
1818		temp.qtd_status |=
1819		    htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1820	}
1821	/* check if we should prepend a setup message */
1822
1823	if (xfer->flags_int.control_xfr) {
1824		if (xfer->flags_int.control_hdr) {
1825
1826			xfer->endpoint->toggle_next = 0;
1827
1828			temp.qtd_status &=
1829			    htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1830			temp.qtd_status |= htohc32(temp.sc,
1831			    EHCI_QTD_ACTIVE |
1832			    EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1833			    EHCI_QTD_SET_TOGGLE(0));
1834
1835			temp.len = xfer->frlengths[0];
1836			temp.pc = xfer->frbuffers + 0;
1837			temp.shortpkt = temp.len ? 1 : 0;
1838			/* check for last frame */
1839			if (xfer->nframes == 1) {
1840				/* no STATUS stage yet, SETUP is last */
1841				if (xfer->flags_int.control_act) {
1842					temp.last_frame = 1;
1843					temp.setup_alt_next = 0;
1844				}
1845			}
1846			ehci_setup_standard_chain_sub(&temp);
1847		}
1848		x = 1;
1849	} else {
1850		x = 0;
1851	}
1852
1853	while (x != xfer->nframes) {
1854
1855		/* DATA0 / DATA1 message */
1856
1857		temp.len = xfer->frlengths[x];
1858		temp.pc = xfer->frbuffers + x;
1859
1860		x++;
1861
1862		if (x == xfer->nframes) {
1863			if (xfer->flags_int.control_xfr) {
1864				/* no STATUS stage yet, DATA is last */
1865				if (xfer->flags_int.control_act) {
1866					temp.last_frame = 1;
1867					temp.setup_alt_next = 0;
1868				}
1869			} else {
1870				temp.last_frame = 1;
1871				temp.setup_alt_next = 0;
1872			}
1873		}
1874		/* keep previous data toggle and error count */
1875
1876		temp.qtd_status &=
1877		    htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1878		    EHCI_QTD_SET_TOGGLE(1));
1879
1880		if (temp.len == 0) {
1881
1882			/* make sure that we send an USB packet */
1883
1884			temp.shortpkt = 0;
1885
1886		} else {
1887
1888			/* regular data transfer */
1889
1890			temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1891		}
1892
1893		/* set endpoint direction */
1894
1895		temp.qtd_status |=
1896		    (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1897		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1898		    EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1899		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1900		    EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1901
1902		ehci_setup_standard_chain_sub(&temp);
1903	}
1904
1905	/* check if we should append a status stage */
1906
1907	if (xfer->flags_int.control_xfr &&
1908	    !xfer->flags_int.control_act) {
1909
1910		/*
1911		 * Send a DATA1 message and invert the current endpoint
1912		 * direction.
1913		 */
1914
1915		temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1916		    EHCI_QTD_SET_TOGGLE(1));
1917		temp.qtd_status |=
1918		    (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1919		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1920		    EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1921		    EHCI_QTD_SET_TOGGLE(1)) :
1922		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1923		    EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1924		    EHCI_QTD_SET_TOGGLE(1));
1925
1926		temp.len = 0;
1927		temp.pc = NULL;
1928		temp.shortpkt = 0;
1929		temp.last_frame = 1;
1930		temp.setup_alt_next = 0;
1931
1932		ehci_setup_standard_chain_sub(&temp);
1933	}
1934	td = temp.td;
1935
1936	/* the last TD terminates the transfer: */
1937	td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1938	td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1939
1940	usb_pc_cpu_flush(td->page_cache);
1941
1942	/* must have at least one frame! */
1943
1944	xfer->td_transfer_last = td;
1945
1946#ifdef USB_DEBUG
1947	if (ehcidebug > 8) {
1948		DPRINTF("nexttog=%d; data before transfer:\n",
1949		    xfer->endpoint->toggle_next);
1950		ehci_dump_sqtds(temp.sc,
1951		    xfer->td_transfer_first);
1952	}
1953#endif
1954
1955	methods = xfer->endpoint->methods;
1956
1957	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1958
1959	/* the "qh_link" field is filled when the QH is added */
1960
1961	qh_endp =
1962	    (EHCI_QH_SET_ADDR(xfer->address) |
1963	    EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1964	    EHCI_QH_SET_MPL(xfer->max_packet_size));
1965
1966	if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1967		qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1968		if (methods != &ehci_device_intr_methods)
1969			qh_endp |= EHCI_QH_SET_NRL(8);
1970	} else {
1971
1972		if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1973			qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1974		} else {
1975			qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1976		}
1977
1978		if (methods == &ehci_device_ctrl_methods) {
1979			qh_endp |= EHCI_QH_CTL;
1980		}
1981		if (methods != &ehci_device_intr_methods) {
1982			/* Only try one time per microframe! */
1983			qh_endp |= EHCI_QH_SET_NRL(1);
1984		}
1985	}
1986
1987	if (temp.auto_data_toggle == 0) {
1988		/* software computes the data toggle */
1989		qh_endp |= EHCI_QH_DTC;
1990	}
1991
1992	qh->qh_endp = htohc32(temp.sc, qh_endp);
1993
1994	qh_endphub =
1995	    (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1996	    EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
1997	    EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
1998	    EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1999	    EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
2000
2001	qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2002	qh->qh_curqtd = 0;
2003
2004	/* fill the overlay qTD */
2005
2006	if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2007		/* DATA1 is next */
2008		qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2009	} else {
2010		qh->qh_qtd.qtd_status = 0;
2011	}
2012
2013	td = xfer->td_transfer_first;
2014
2015	qh->qh_qtd.qtd_next = td->qtd_self;
2016	qh->qh_qtd.qtd_altnext =
2017	    htohc32(temp.sc, EHCI_LINK_TERMINATE);
2018
2019	/* properly reset reserved fields */
2020	qh->qh_qtd.qtd_buffer[0] = 0;
2021	qh->qh_qtd.qtd_buffer[1] = 0;
2022	qh->qh_qtd.qtd_buffer[2] = 0;
2023	qh->qh_qtd.qtd_buffer[3] = 0;
2024	qh->qh_qtd.qtd_buffer[4] = 0;
2025	qh->qh_qtd.qtd_buffer_hi[0] = 0;
2026	qh->qh_qtd.qtd_buffer_hi[1] = 0;
2027	qh->qh_qtd.qtd_buffer_hi[2] = 0;
2028	qh->qh_qtd.qtd_buffer_hi[3] = 0;
2029	qh->qh_qtd.qtd_buffer_hi[4] = 0;
2030
2031	usb_pc_cpu_flush(qh->page_cache);
2032
2033	if (xfer->xroot->udev->flags.self_suspended == 0) {
2034		EHCI_APPEND_QH(qh, *qh_last);
2035	}
2036}
2037
2038static void
2039ehci_root_intr(ehci_softc_t *sc)
2040{
2041	uint16_t i;
2042	uint16_t m;
2043
2044	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2045
2046	/* clear any old interrupt data */
2047	memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2048
2049	/* set bits */
2050	m = (sc->sc_noport + 1);
2051	if (m > (8 * sizeof(sc->sc_hub_idata))) {
2052		m = (8 * sizeof(sc->sc_hub_idata));
2053	}
2054	for (i = 1; i < m; i++) {
2055		/* pick out CHANGE bits from the status register */
2056		if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2057			sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2058			DPRINTF("port %d changed\n", i);
2059		}
2060	}
2061	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2062	    sizeof(sc->sc_hub_idata));
2063}
2064
2065static void
2066ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2067{
2068	uint32_t nframes = xfer->nframes;
2069	uint32_t status;
2070	uint32_t *plen = xfer->frlengths;
2071	uint16_t len = 0;
2072	ehci_sitd_t *td = xfer->td_transfer_first;
2073	ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2074
2075	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2076	    xfer, xfer->endpoint);
2077
2078	while (nframes--) {
2079		if (td == NULL) {
2080			panic("%s:%d: out of TD's\n",
2081			    __FUNCTION__, __LINE__);
2082		}
2083		if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2084			pp_last = &sc->sc_isoc_fs_p_last[0];
2085		}
2086#ifdef USB_DEBUG
2087		if (ehcidebug > 15) {
2088			DPRINTF("isoc FS-TD\n");
2089			ehci_dump_sitd(sc, td);
2090		}
2091#endif
2092		usb_pc_cpu_invalidate(td->page_cache);
2093		status = hc32toh(sc, td->sitd_status);
2094
2095		len = EHCI_SITD_GET_LEN(status);
2096
2097		DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2098
2099		if (*plen >= len) {
2100			len = *plen - len;
2101		} else {
2102			len = 0;
2103		}
2104
2105		*plen = len;
2106
2107		/* remove FS-TD from schedule */
2108		EHCI_REMOVE_FS_TD(td, *pp_last);
2109
2110		pp_last++;
2111		plen++;
2112		td = td->obj_next;
2113	}
2114
2115	xfer->aframes = xfer->nframes;
2116}
2117
2118static void
2119ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2120{
2121	uint32_t nframes = xfer->nframes;
2122	uint32_t status;
2123	uint32_t *plen = xfer->frlengths;
2124	uint16_t len = 0;
2125	uint8_t td_no = 0;
2126	ehci_itd_t *td = xfer->td_transfer_first;
2127	ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2128
2129	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2130	    xfer, xfer->endpoint);
2131
2132	while (nframes) {
2133		if (td == NULL) {
2134			panic("%s:%d: out of TD's\n",
2135			    __FUNCTION__, __LINE__);
2136		}
2137		if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2138			pp_last = &sc->sc_isoc_hs_p_last[0];
2139		}
2140#ifdef USB_DEBUG
2141		if (ehcidebug > 15) {
2142			DPRINTF("isoc HS-TD\n");
2143			ehci_dump_itd(sc, td);
2144		}
2145#endif
2146
2147		usb_pc_cpu_invalidate(td->page_cache);
2148		status = hc32toh(sc, td->itd_status[td_no]);
2149
2150		len = EHCI_ITD_GET_LEN(status);
2151
2152		DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2153
2154		if (xfer->endpoint->usb_smask & (1 << td_no)) {
2155
2156			if (*plen >= len) {
2157				/*
2158				 * The length is valid. NOTE: The
2159				 * complete length is written back
2160				 * into the status field, and not the
2161				 * remainder like with other transfer
2162				 * descriptor types.
2163				 */
2164			} else {
2165				/* Invalid length - truncate */
2166				len = 0;
2167			}
2168
2169			*plen = len;
2170			plen++;
2171			nframes--;
2172		}
2173
2174		td_no++;
2175
2176		if ((td_no == 8) || (nframes == 0)) {
2177			/* remove HS-TD from schedule */
2178			EHCI_REMOVE_HS_TD(td, *pp_last);
2179			pp_last++;
2180
2181			td_no = 0;
2182			td = td->obj_next;
2183		}
2184	}
2185	xfer->aframes = xfer->nframes;
2186}
2187
2188/* NOTE: "done" can be run two times in a row,
2189 * from close and from interrupt
2190 */
2191static void
2192ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2193{
2194	struct usb_pipe_methods *methods = xfer->endpoint->methods;
2195	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2196
2197	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2198
2199	DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2200	    xfer, xfer->endpoint, error);
2201
2202	if ((methods == &ehci_device_bulk_methods) ||
2203	    (methods == &ehci_device_ctrl_methods)) {
2204#ifdef USB_DEBUG
2205		if (ehcidebug > 8) {
2206			DPRINTF("nexttog=%d; data after transfer:\n",
2207			    xfer->endpoint->toggle_next);
2208			ehci_dump_sqtds(sc,
2209			    xfer->td_transfer_first);
2210		}
2211#endif
2212
2213		EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2214		    sc->sc_async_p_last);
2215	}
2216	if (methods == &ehci_device_intr_methods) {
2217		EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2218		    sc->sc_intr_p_last[xfer->qh_pos]);
2219	}
2220	/*
2221	 * Only finish isochronous transfers once which will update
2222	 * "xfer->frlengths".
2223	 */
2224	if (xfer->td_transfer_first &&
2225	    xfer->td_transfer_last) {
2226		if (methods == &ehci_device_isoc_fs_methods) {
2227			ehci_isoc_fs_done(sc, xfer);
2228		}
2229		if (methods == &ehci_device_isoc_hs_methods) {
2230			ehci_isoc_hs_done(sc, xfer);
2231		}
2232		xfer->td_transfer_first = NULL;
2233		xfer->td_transfer_last = NULL;
2234	}
2235	/* dequeue transfer and start next transfer */
2236	usbd_transfer_done(xfer, error);
2237}
2238
2239/*------------------------------------------------------------------------*
2240 * ehci bulk support
2241 *------------------------------------------------------------------------*/
2242static void
2243ehci_device_bulk_open(struct usb_xfer *xfer)
2244{
2245	return;
2246}
2247
2248static void
2249ehci_device_bulk_close(struct usb_xfer *xfer)
2250{
2251	ehci_device_done(xfer, USB_ERR_CANCELLED);
2252}
2253
2254static void
2255ehci_device_bulk_enter(struct usb_xfer *xfer)
2256{
2257	return;
2258}
2259
2260static void
2261ehci_doorbell_async(struct ehci_softc *sc)
2262{
2263	uint32_t temp;
2264
2265	/*
2266	 * XXX Performance quirk: Some Host Controllers have a too low
2267	 * interrupt rate. Issue an IAAD to stimulate the Host
2268	 * Controller after queueing the BULK transfer.
2269	 *
2270	 * XXX Force the host controller to refresh any QH caches.
2271	 */
2272	temp = EOREAD4(sc, EHCI_USBCMD);
2273	if (!(temp & EHCI_CMD_IAAD))
2274		EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2275}
2276
2277static void
2278ehci_device_bulk_start(struct usb_xfer *xfer)
2279{
2280	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2281
2282	/* setup TD's and QH */
2283	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2284
2285	/* put transfer on interrupt queue */
2286	ehci_transfer_intr_enqueue(xfer);
2287
2288	/*
2289	 * XXX Certain nVidia chipsets choke when using the IAAD
2290	 * feature too frequently.
2291	 */
2292	if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2293		return;
2294
2295	ehci_doorbell_async(sc);
2296}
2297
2298struct usb_pipe_methods ehci_device_bulk_methods =
2299{
2300	.open = ehci_device_bulk_open,
2301	.close = ehci_device_bulk_close,
2302	.enter = ehci_device_bulk_enter,
2303	.start = ehci_device_bulk_start,
2304};
2305
2306/*------------------------------------------------------------------------*
2307 * ehci control support
2308 *------------------------------------------------------------------------*/
2309static void
2310ehci_device_ctrl_open(struct usb_xfer *xfer)
2311{
2312	return;
2313}
2314
2315static void
2316ehci_device_ctrl_close(struct usb_xfer *xfer)
2317{
2318	ehci_device_done(xfer, USB_ERR_CANCELLED);
2319}
2320
2321static void
2322ehci_device_ctrl_enter(struct usb_xfer *xfer)
2323{
2324	return;
2325}
2326
2327static void
2328ehci_device_ctrl_start(struct usb_xfer *xfer)
2329{
2330	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2331
2332	/* setup TD's and QH */
2333	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2334
2335	/* put transfer on interrupt queue */
2336	ehci_transfer_intr_enqueue(xfer);
2337}
2338
2339struct usb_pipe_methods ehci_device_ctrl_methods =
2340{
2341	.open = ehci_device_ctrl_open,
2342	.close = ehci_device_ctrl_close,
2343	.enter = ehci_device_ctrl_enter,
2344	.start = ehci_device_ctrl_start,
2345};
2346
2347/*------------------------------------------------------------------------*
2348 * ehci interrupt support
2349 *------------------------------------------------------------------------*/
2350static void
2351ehci_device_intr_open(struct usb_xfer *xfer)
2352{
2353	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2354	uint16_t best;
2355	uint16_t bit;
2356	uint16_t x;
2357
2358	usb_hs_bandwidth_alloc(xfer);
2359
2360	/*
2361	 * Find the best QH position corresponding to the given interval:
2362	 */
2363
2364	best = 0;
2365	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2366	while (bit) {
2367		if (xfer->interval >= bit) {
2368			x = bit;
2369			best = bit;
2370			while (x & bit) {
2371				if (sc->sc_intr_stat[x] <
2372				    sc->sc_intr_stat[best]) {
2373					best = x;
2374				}
2375				x++;
2376			}
2377			break;
2378		}
2379		bit >>= 1;
2380	}
2381
2382	sc->sc_intr_stat[best]++;
2383	xfer->qh_pos = best;
2384
2385	DPRINTFN(3, "best=%d interval=%d\n",
2386	    best, xfer->interval);
2387}
2388
2389static void
2390ehci_device_intr_close(struct usb_xfer *xfer)
2391{
2392	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2393
2394	sc->sc_intr_stat[xfer->qh_pos]--;
2395
2396	ehci_device_done(xfer, USB_ERR_CANCELLED);
2397
2398	/* bandwidth must be freed after device done */
2399	usb_hs_bandwidth_free(xfer);
2400}
2401
2402static void
2403ehci_device_intr_enter(struct usb_xfer *xfer)
2404{
2405	return;
2406}
2407
2408static void
2409ehci_device_intr_start(struct usb_xfer *xfer)
2410{
2411	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2412
2413	/* setup TD's and QH */
2414	ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2415
2416	/* put transfer on interrupt queue */
2417	ehci_transfer_intr_enqueue(xfer);
2418}
2419
2420struct usb_pipe_methods ehci_device_intr_methods =
2421{
2422	.open = ehci_device_intr_open,
2423	.close = ehci_device_intr_close,
2424	.enter = ehci_device_intr_enter,
2425	.start = ehci_device_intr_start,
2426};
2427
2428/*------------------------------------------------------------------------*
2429 * ehci full speed isochronous support
2430 *------------------------------------------------------------------------*/
2431static void
2432ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2433{
2434	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2435	ehci_sitd_t *td;
2436	uint32_t sitd_portaddr;
2437	uint8_t ds;
2438
2439	sitd_portaddr =
2440	    EHCI_SITD_SET_ADDR(xfer->address) |
2441	    EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2442	    EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2443	    EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2444
2445	if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
2446		sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2447
2448	sitd_portaddr = htohc32(sc, sitd_portaddr);
2449
2450	/* initialize all TD's */
2451
2452	for (ds = 0; ds != 2; ds++) {
2453
2454		for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2455
2456			td->sitd_portaddr = sitd_portaddr;
2457
2458			/*
2459			 * TODO: make some kind of automatic
2460			 * SMASK/CMASK selection based on micro-frame
2461			 * usage
2462			 *
2463			 * micro-frame usage (8 microframes per 1ms)
2464			 */
2465			td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2466
2467			usb_pc_cpu_flush(td->page_cache);
2468		}
2469	}
2470}
2471
2472static void
2473ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2474{
2475	ehci_device_done(xfer, USB_ERR_CANCELLED);
2476}
2477
2478static void
2479ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2480{
2481	struct usb_page_search buf_res;
2482	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2483	ehci_sitd_t *td;
2484	ehci_sitd_t *td_last = NULL;
2485	ehci_sitd_t **pp_last;
2486	uint32_t *plen;
2487	uint32_t buf_offset;
2488	uint32_t nframes;
2489	uint32_t temp;
2490	uint32_t sitd_mask;
2491	uint16_t tlen;
2492	uint8_t sa;
2493	uint8_t sb;
2494
2495#ifdef USB_DEBUG
2496	uint8_t once = 1;
2497
2498#endif
2499
2500	DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2501	    xfer, xfer->endpoint->isoc_next, xfer->nframes);
2502
2503	/* get the current frame index */
2504
2505	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2506
2507	/*
2508	 * check if the frame index is within the window where the frames
2509	 * will be inserted
2510	 */
2511	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2512	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2513
2514	if ((xfer->endpoint->is_synced == 0) ||
2515	    (buf_offset < xfer->nframes)) {
2516		/*
2517		 * If there is data underflow or the pipe queue is empty we
2518		 * schedule the transfer a few frames ahead of the current
2519		 * frame position. Else two isochronous transfers might
2520		 * overlap.
2521		 */
2522		xfer->endpoint->isoc_next = (nframes + 3) &
2523		    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2524		xfer->endpoint->is_synced = 1;
2525		DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2526	}
2527	/*
2528	 * compute how many milliseconds the insertion is ahead of the
2529	 * current frame position:
2530	 */
2531	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2532	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2533
2534	/*
2535	 * pre-compute when the isochronous transfer will be finished:
2536	 */
2537	xfer->isoc_time_complete =
2538	    usb_isoc_time_expand(&sc->sc_bus, nframes) +
2539	    buf_offset + xfer->nframes;
2540
2541	/* get the real number of frames */
2542
2543	nframes = xfer->nframes;
2544
2545	buf_offset = 0;
2546
2547	plen = xfer->frlengths;
2548
2549	/* toggle the DMA set we are using */
2550	xfer->flags_int.curr_dma_set ^= 1;
2551
2552	/* get next DMA set */
2553	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2554	xfer->td_transfer_first = td;
2555
2556	pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2557
2558	/* store starting position */
2559
2560	xfer->qh_pos = xfer->endpoint->isoc_next;
2561
2562	while (nframes--) {
2563		if (td == NULL) {
2564			panic("%s:%d: out of TD's\n",
2565			    __FUNCTION__, __LINE__);
2566		}
2567		if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT])
2568			pp_last = &sc->sc_isoc_fs_p_last[0];
2569
2570		/* reuse sitd_portaddr and sitd_back from last transfer */
2571
2572		if (*plen > xfer->max_frame_size) {
2573#ifdef USB_DEBUG
2574			if (once) {
2575				once = 0;
2576				printf("%s: frame length(%d) exceeds %d "
2577				    "bytes (frame truncated)\n",
2578				    __FUNCTION__, *plen,
2579				    xfer->max_frame_size);
2580			}
2581#endif
2582			*plen = xfer->max_frame_size;
2583		}
2584
2585		/* allocate a slot */
2586
2587		sa = usbd_fs_isoc_schedule_alloc_slot(xfer,
2588		    xfer->isoc_time_complete - nframes - 1);
2589
2590		if (sa == 255) {
2591			/*
2592			 * Schedule is FULL, set length to zero:
2593			 */
2594
2595			*plen = 0;
2596			sa = USB_FS_ISOC_UFRAME_MAX - 1;
2597		}
2598		if (*plen) {
2599			/*
2600			 * only call "usbd_get_page()" when we have a
2601			 * non-zero length
2602			 */
2603			usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2604			td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2605			buf_offset += *plen;
2606			/*
2607			 * NOTE: We need to subtract one from the offset so
2608			 * that we are on a valid page!
2609			 */
2610			usbd_get_page(xfer->frbuffers, buf_offset - 1,
2611			    &buf_res);
2612			temp = buf_res.physaddr & ~0xFFF;
2613		} else {
2614			td->sitd_bp[0] = 0;
2615			temp = 0;
2616		}
2617
2618		if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2619			tlen = *plen;
2620			if (tlen <= 188) {
2621				temp |= 1;	/* T-count = 1, TP = ALL */
2622				tlen = 1;
2623			} else {
2624				tlen += 187;
2625				tlen /= 188;
2626				temp |= tlen;	/* T-count = [1..6] */
2627				temp |= 8;	/* TP = Begin */
2628			}
2629
2630			tlen += sa;
2631
2632			if (tlen >= 8) {
2633				sb = 0;
2634			} else {
2635				sb = (1 << tlen);
2636			}
2637
2638			sa = (1 << sa);
2639			sa = (sb - sa) & 0x3F;
2640			sb = 0;
2641		} else {
2642			sb = (-(4 << sa)) & 0xFE;
2643			sa = (1 << sa) & 0x3F;
2644		}
2645
2646		sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2647		    EHCI_SITD_SET_CMASK(sb));
2648
2649		td->sitd_bp[1] = htohc32(sc, temp);
2650
2651		td->sitd_mask = htohc32(sc, sitd_mask);
2652
2653		if (nframes == 0) {
2654			td->sitd_status = htohc32(sc,
2655			    EHCI_SITD_IOC |
2656			    EHCI_SITD_ACTIVE |
2657			    EHCI_SITD_SET_LEN(*plen));
2658		} else {
2659			td->sitd_status = htohc32(sc,
2660			    EHCI_SITD_ACTIVE |
2661			    EHCI_SITD_SET_LEN(*plen));
2662		}
2663		usb_pc_cpu_flush(td->page_cache);
2664
2665#ifdef USB_DEBUG
2666		if (ehcidebug > 15) {
2667			DPRINTF("FS-TD %d\n", nframes);
2668			ehci_dump_sitd(sc, td);
2669		}
2670#endif
2671		/* insert TD into schedule */
2672		EHCI_APPEND_FS_TD(td, *pp_last);
2673		pp_last++;
2674
2675		plen++;
2676		td_last = td;
2677		td = td->obj_next;
2678	}
2679
2680	xfer->td_transfer_last = td_last;
2681
2682	/* update isoc_next */
2683	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2684	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2685
2686	/*
2687	 * We don't allow cancelling of the SPLIT transaction USB FULL
2688	 * speed transfer, because it disturbs the bandwidth
2689	 * computation algorithm.
2690	 */
2691	xfer->flags_int.can_cancel_immed = 0;
2692}
2693
2694static void
2695ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2696{
2697	/*
2698	 * We don't allow cancelling of the SPLIT transaction USB FULL
2699	 * speed transfer, because it disturbs the bandwidth
2700	 * computation algorithm.
2701	 */
2702	xfer->flags_int.can_cancel_immed = 0;
2703
2704	/* set a default timeout */
2705	if (xfer->timeout == 0)
2706		xfer->timeout = 500; /* ms */
2707
2708	/* put transfer on interrupt queue */
2709	ehci_transfer_intr_enqueue(xfer);
2710}
2711
2712struct usb_pipe_methods ehci_device_isoc_fs_methods =
2713{
2714	.open = ehci_device_isoc_fs_open,
2715	.close = ehci_device_isoc_fs_close,
2716	.enter = ehci_device_isoc_fs_enter,
2717	.start = ehci_device_isoc_fs_start,
2718};
2719
2720/*------------------------------------------------------------------------*
2721 * ehci high speed isochronous support
2722 *------------------------------------------------------------------------*/
2723static void
2724ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2725{
2726	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2727	ehci_itd_t *td;
2728	uint32_t temp;
2729	uint8_t ds;
2730
2731	usb_hs_bandwidth_alloc(xfer);
2732
2733	/* initialize all TD's */
2734
2735	for (ds = 0; ds != 2; ds++) {
2736
2737		for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2738
2739			/* set TD inactive */
2740			td->itd_status[0] = 0;
2741			td->itd_status[1] = 0;
2742			td->itd_status[2] = 0;
2743			td->itd_status[3] = 0;
2744			td->itd_status[4] = 0;
2745			td->itd_status[5] = 0;
2746			td->itd_status[6] = 0;
2747			td->itd_status[7] = 0;
2748
2749			/* set endpoint and address */
2750			td->itd_bp[0] = htohc32(sc,
2751			    EHCI_ITD_SET_ADDR(xfer->address) |
2752			    EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2753
2754			temp =
2755			    EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2756
2757			/* set direction */
2758			if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2759				temp |= EHCI_ITD_SET_DIR_IN;
2760			}
2761			/* set maximum packet size */
2762			td->itd_bp[1] = htohc32(sc, temp);
2763
2764			/* set transfer multiplier */
2765			td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2766
2767			usb_pc_cpu_flush(td->page_cache);
2768		}
2769	}
2770}
2771
2772static void
2773ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2774{
2775	ehci_device_done(xfer, USB_ERR_CANCELLED);
2776
2777	/* bandwidth must be freed after device done */
2778	usb_hs_bandwidth_free(xfer);
2779}
2780
2781static void
2782ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2783{
2784	struct usb_page_search buf_res;
2785	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2786	ehci_itd_t *td;
2787	ehci_itd_t *td_last = NULL;
2788	ehci_itd_t **pp_last;
2789	bus_size_t page_addr;
2790	uint32_t *plen;
2791	uint32_t status;
2792	uint32_t buf_offset;
2793	uint32_t nframes;
2794	uint32_t itd_offset[8 + 1];
2795	uint8_t x;
2796	uint8_t td_no;
2797	uint8_t page_no;
2798	uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2799
2800#ifdef USB_DEBUG
2801	uint8_t once = 1;
2802
2803#endif
2804
2805	DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2806	    xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2807
2808	/* get the current frame index */
2809
2810	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2811
2812	/*
2813	 * check if the frame index is within the window where the frames
2814	 * will be inserted
2815	 */
2816	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2817	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2818
2819	if ((xfer->endpoint->is_synced == 0) ||
2820	    (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2821		/*
2822		 * If there is data underflow or the pipe queue is empty we
2823		 * schedule the transfer a few frames ahead of the current
2824		 * frame position. Else two isochronous transfers might
2825		 * overlap.
2826		 */
2827		xfer->endpoint->isoc_next = (nframes + 3) &
2828		    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2829		xfer->endpoint->is_synced = 1;
2830		DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2831	}
2832	/*
2833	 * compute how many milliseconds the insertion is ahead of the
2834	 * current frame position:
2835	 */
2836	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2837	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2838
2839	/*
2840	 * pre-compute when the isochronous transfer will be finished:
2841	 */
2842	xfer->isoc_time_complete =
2843	    usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2844	    (((xfer->nframes << shift) + 7) / 8);
2845
2846	/* get the real number of frames */
2847
2848	nframes = xfer->nframes;
2849
2850	buf_offset = 0;
2851	td_no = 0;
2852
2853	plen = xfer->frlengths;
2854
2855	/* toggle the DMA set we are using */
2856	xfer->flags_int.curr_dma_set ^= 1;
2857
2858	/* get next DMA set */
2859	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2860	xfer->td_transfer_first = td;
2861
2862	pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2863
2864	/* store starting position */
2865
2866	xfer->qh_pos = xfer->endpoint->isoc_next;
2867
2868	while (nframes) {
2869		if (td == NULL) {
2870			panic("%s:%d: out of TD's\n",
2871			    __FUNCTION__, __LINE__);
2872		}
2873		if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2874			pp_last = &sc->sc_isoc_hs_p_last[0];
2875		}
2876		/* range check */
2877		if (*plen > xfer->max_frame_size) {
2878#ifdef USB_DEBUG
2879			if (once) {
2880				once = 0;
2881				printf("%s: frame length(%d) exceeds %d bytes "
2882				    "(frame truncated)\n",
2883				    __FUNCTION__, *plen, xfer->max_frame_size);
2884			}
2885#endif
2886			*plen = xfer->max_frame_size;
2887		}
2888
2889		if (xfer->endpoint->usb_smask & (1 << td_no)) {
2890			status = (EHCI_ITD_SET_LEN(*plen) |
2891			    EHCI_ITD_ACTIVE |
2892			    EHCI_ITD_SET_PG(0));
2893			td->itd_status[td_no] = htohc32(sc, status);
2894			itd_offset[td_no] = buf_offset;
2895			buf_offset += *plen;
2896			plen++;
2897			nframes --;
2898		} else {
2899			td->itd_status[td_no] = 0;	/* not active */
2900			itd_offset[td_no] = buf_offset;
2901		}
2902
2903		td_no++;
2904
2905		if ((td_no == 8) || (nframes == 0)) {
2906
2907			/* the rest of the transfers are not active, if any */
2908			for (x = td_no; x != 8; x++) {
2909				td->itd_status[x] = 0;	/* not active */
2910			}
2911
2912			/* check if there is any data to be transferred */
2913			if (itd_offset[0] != buf_offset) {
2914				page_no = 0;
2915				itd_offset[td_no] = buf_offset;
2916
2917				/* get first page offset */
2918				usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2919				/* get page address */
2920				page_addr = buf_res.physaddr & ~0xFFF;
2921				/* update page address */
2922				td->itd_bp[0] &= htohc32(sc, 0xFFF);
2923				td->itd_bp[0] |= htohc32(sc, page_addr);
2924
2925				for (x = 0; x != td_no; x++) {
2926					/* set page number and page offset */
2927					status = (EHCI_ITD_SET_PG(page_no) |
2928					    (buf_res.physaddr & 0xFFF));
2929					td->itd_status[x] |= htohc32(sc, status);
2930
2931					/* get next page offset */
2932					if (itd_offset[x + 1] == buf_offset) {
2933						/*
2934						 * We subtract one so that
2935						 * we don't go off the last
2936						 * page!
2937						 */
2938						usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2939					} else {
2940						usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2941					}
2942
2943					/* check if we need a new page */
2944					if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2945						/* new page needed */
2946						page_addr = buf_res.physaddr & ~0xFFF;
2947						if (page_no == 6) {
2948							panic("%s: too many pages\n", __FUNCTION__);
2949						}
2950						page_no++;
2951						/* update page address */
2952						td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2953						td->itd_bp[page_no] |= htohc32(sc, page_addr);
2954					}
2955				}
2956			}
2957			/* set IOC bit if we are complete */
2958			if (nframes == 0) {
2959				td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2960			}
2961			usb_pc_cpu_flush(td->page_cache);
2962#ifdef USB_DEBUG
2963			if (ehcidebug > 15) {
2964				DPRINTF("HS-TD %d\n", nframes);
2965				ehci_dump_itd(sc, td);
2966			}
2967#endif
2968			/* insert TD into schedule */
2969			EHCI_APPEND_HS_TD(td, *pp_last);
2970			pp_last++;
2971
2972			td_no = 0;
2973			td_last = td;
2974			td = td->obj_next;
2975		}
2976	}
2977
2978	xfer->td_transfer_last = td_last;
2979
2980	/* update isoc_next */
2981	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2982	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2983}
2984
2985static void
2986ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2987{
2988	/* put transfer on interrupt queue */
2989	ehci_transfer_intr_enqueue(xfer);
2990}
2991
2992struct usb_pipe_methods ehci_device_isoc_hs_methods =
2993{
2994	.open = ehci_device_isoc_hs_open,
2995	.close = ehci_device_isoc_hs_close,
2996	.enter = ehci_device_isoc_hs_enter,
2997	.start = ehci_device_isoc_hs_start,
2998};
2999
3000/*------------------------------------------------------------------------*
3001 * ehci root control support
3002 *------------------------------------------------------------------------*
3003 * Simulate a hardware hub by handling all the necessary requests.
3004 *------------------------------------------------------------------------*/
3005
3006static const
3007struct usb_device_descriptor ehci_devd =
3008{
3009	sizeof(struct usb_device_descriptor),
3010	UDESC_DEVICE,			/* type */
3011	{0x00, 0x02},			/* USB version */
3012	UDCLASS_HUB,			/* class */
3013	UDSUBCLASS_HUB,			/* subclass */
3014	UDPROTO_HSHUBSTT,		/* protocol */
3015	64,				/* max packet */
3016	{0}, {0}, {0x00, 0x01},		/* device id */
3017	1, 2, 0,			/* string indicies */
3018	1				/* # of configurations */
3019};
3020
3021static const
3022struct usb_device_qualifier ehci_odevd =
3023{
3024	sizeof(struct usb_device_qualifier),
3025	UDESC_DEVICE_QUALIFIER,		/* type */
3026	{0x00, 0x02},			/* USB version */
3027	UDCLASS_HUB,			/* class */
3028	UDSUBCLASS_HUB,			/* subclass */
3029	UDPROTO_FSHUB,			/* protocol */
3030	0,				/* max packet */
3031	0,				/* # of configurations */
3032	0
3033};
3034
3035static const struct ehci_config_desc ehci_confd = {
3036	.confd = {
3037		.bLength = sizeof(struct usb_config_descriptor),
3038		.bDescriptorType = UDESC_CONFIG,
3039		.wTotalLength[0] = sizeof(ehci_confd),
3040		.bNumInterface = 1,
3041		.bConfigurationValue = 1,
3042		.iConfiguration = 0,
3043		.bmAttributes = UC_SELF_POWERED,
3044		.bMaxPower = 0		/* max power */
3045	},
3046	.ifcd = {
3047		.bLength = sizeof(struct usb_interface_descriptor),
3048		.bDescriptorType = UDESC_INTERFACE,
3049		.bNumEndpoints = 1,
3050		.bInterfaceClass = UICLASS_HUB,
3051		.bInterfaceSubClass = UISUBCLASS_HUB,
3052		.bInterfaceProtocol = 0,
3053	},
3054	.endpd = {
3055		.bLength = sizeof(struct usb_endpoint_descriptor),
3056		.bDescriptorType = UDESC_ENDPOINT,
3057		.bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3058		.bmAttributes = UE_INTERRUPT,
3059		.wMaxPacketSize[0] = 8,	/* max packet (63 ports) */
3060		.bInterval = 255,
3061	},
3062};
3063
3064static const
3065struct usb_hub_descriptor ehci_hubd =
3066{
3067	.bDescLength = 0,		/* dynamic length */
3068	.bDescriptorType = UDESC_HUB,
3069};
3070
3071static void
3072ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3073{
3074	uint32_t port;
3075	uint32_t v;
3076
3077	DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3078
3079	port = EHCI_PORTSC(index);
3080	v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3081	EOWRITE4(sc, port, v | EHCI_PS_PO);
3082}
3083
3084static usb_error_t
3085ehci_roothub_exec(struct usb_device *udev,
3086    struct usb_device_request *req, const void **pptr, uint16_t *plength)
3087{
3088	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3089	const char *str_ptr;
3090	const void *ptr;
3091	uint32_t port;
3092	uint32_t v;
3093	uint16_t len;
3094	uint16_t i;
3095	uint16_t value;
3096	uint16_t index;
3097	usb_error_t err;
3098
3099	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3100
3101	/* buffer reset */
3102	ptr = (const void *)&sc->sc_hub_desc;
3103	len = 0;
3104	err = 0;
3105
3106	value = UGETW(req->wValue);
3107	index = UGETW(req->wIndex);
3108
3109	DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3110	    "wValue=0x%04x wIndex=0x%04x\n",
3111	    req->bmRequestType, req->bRequest,
3112	    UGETW(req->wLength), value, index);
3113
3114#define	C(x,y) ((x) | ((y) << 8))
3115	switch (C(req->bRequest, req->bmRequestType)) {
3116	case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3117	case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3118	case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3119		/*
3120		 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3121		 * for the integrated root hub.
3122		 */
3123		break;
3124	case C(UR_GET_CONFIG, UT_READ_DEVICE):
3125		len = 1;
3126		sc->sc_hub_desc.temp[0] = sc->sc_conf;
3127		break;
3128	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3129		switch (value >> 8) {
3130		case UDESC_DEVICE:
3131			if ((value & 0xff) != 0) {
3132				err = USB_ERR_IOERROR;
3133				goto done;
3134			}
3135			len = sizeof(ehci_devd);
3136			ptr = (const void *)&ehci_devd;
3137			break;
3138			/*
3139			 * We can't really operate at another speed,
3140			 * but the specification says we need this
3141			 * descriptor:
3142			 */
3143		case UDESC_DEVICE_QUALIFIER:
3144			if ((value & 0xff) != 0) {
3145				err = USB_ERR_IOERROR;
3146				goto done;
3147			}
3148			len = sizeof(ehci_odevd);
3149			ptr = (const void *)&ehci_odevd;
3150			break;
3151
3152		case UDESC_CONFIG:
3153			if ((value & 0xff) != 0) {
3154				err = USB_ERR_IOERROR;
3155				goto done;
3156			}
3157			len = sizeof(ehci_confd);
3158			ptr = (const void *)&ehci_confd;
3159			break;
3160
3161		case UDESC_STRING:
3162			switch (value & 0xff) {
3163			case 0:	/* Language table */
3164				str_ptr = "\001";
3165				break;
3166
3167			case 1:	/* Vendor */
3168				str_ptr = sc->sc_vendor;
3169				break;
3170
3171			case 2:	/* Product */
3172				str_ptr = "EHCI root HUB";
3173				break;
3174
3175			default:
3176				str_ptr = "";
3177				break;
3178			}
3179
3180			len = usb_make_str_desc(
3181			    sc->sc_hub_desc.temp,
3182			    sizeof(sc->sc_hub_desc.temp),
3183			    str_ptr);
3184			break;
3185		default:
3186			err = USB_ERR_IOERROR;
3187			goto done;
3188		}
3189		break;
3190	case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3191		len = 1;
3192		sc->sc_hub_desc.temp[0] = 0;
3193		break;
3194	case C(UR_GET_STATUS, UT_READ_DEVICE):
3195		len = 2;
3196		USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3197		break;
3198	case C(UR_GET_STATUS, UT_READ_INTERFACE):
3199	case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3200		len = 2;
3201		USETW(sc->sc_hub_desc.stat.wStatus, 0);
3202		break;
3203	case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3204		if (value >= EHCI_MAX_DEVICES) {
3205			err = USB_ERR_IOERROR;
3206			goto done;
3207		}
3208		sc->sc_addr = value;
3209		break;
3210	case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3211		if ((value != 0) && (value != 1)) {
3212			err = USB_ERR_IOERROR;
3213			goto done;
3214		}
3215		sc->sc_conf = value;
3216		break;
3217	case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3218		break;
3219	case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3220	case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3221	case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3222		err = USB_ERR_IOERROR;
3223		goto done;
3224	case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3225		break;
3226	case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3227		break;
3228		/* Hub requests */
3229	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3230		break;
3231	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3232		DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3233
3234		if ((index < 1) ||
3235		    (index > sc->sc_noport)) {
3236			err = USB_ERR_IOERROR;
3237			goto done;
3238		}
3239		port = EHCI_PORTSC(index);
3240		v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3241		switch (value) {
3242		case UHF_PORT_ENABLE:
3243			EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3244			break;
3245		case UHF_PORT_SUSPEND:
3246			if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3247
3248				/*
3249				 * waking up a High Speed device is rather
3250				 * complicated if
3251				 */
3252				EOWRITE4(sc, port, v | EHCI_PS_FPR);
3253			}
3254			/* wait 20ms for resume sequence to complete */
3255			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3256
3257			EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3258			    EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3259
3260			/* 4ms settle time */
3261			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3262			break;
3263		case UHF_PORT_POWER:
3264			EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3265			break;
3266		case UHF_PORT_TEST:
3267			DPRINTFN(3, "clear port test "
3268			    "%d\n", index);
3269			break;
3270		case UHF_PORT_INDICATOR:
3271			DPRINTFN(3, "clear port ind "
3272			    "%d\n", index);
3273			EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3274			break;
3275		case UHF_C_PORT_CONNECTION:
3276			EOWRITE4(sc, port, v | EHCI_PS_CSC);
3277			break;
3278		case UHF_C_PORT_ENABLE:
3279			EOWRITE4(sc, port, v | EHCI_PS_PEC);
3280			break;
3281		case UHF_C_PORT_SUSPEND:
3282			EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3283			break;
3284		case UHF_C_PORT_OVER_CURRENT:
3285			EOWRITE4(sc, port, v | EHCI_PS_OCC);
3286			break;
3287		case UHF_C_PORT_RESET:
3288			sc->sc_isreset = 0;
3289			break;
3290		default:
3291			err = USB_ERR_IOERROR;
3292			goto done;
3293		}
3294		break;
3295	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3296		if ((value & 0xff) != 0) {
3297			err = USB_ERR_IOERROR;
3298			goto done;
3299		}
3300		v = EREAD4(sc, EHCI_HCSPARAMS);
3301
3302		sc->sc_hub_desc.hubd = ehci_hubd;
3303		sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3304
3305		if (EHCI_HCS_PPC(v))
3306			i = UHD_PWR_INDIVIDUAL;
3307		else
3308			i = UHD_PWR_NO_SWITCH;
3309
3310		if (EHCI_HCS_P_INDICATOR(v))
3311			i |= UHD_PORT_IND;
3312
3313		USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3314		/* XXX can't find out? */
3315		sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3316		/* XXX don't know if ports are removable or not */
3317		sc->sc_hub_desc.hubd.bDescLength =
3318		    8 + ((sc->sc_noport + 7) / 8);
3319		len = sc->sc_hub_desc.hubd.bDescLength;
3320		break;
3321	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3322		len = 16;
3323		memset(sc->sc_hub_desc.temp, 0, 16);
3324		break;
3325	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3326		DPRINTFN(9, "get port status i=%d\n",
3327		    index);
3328		if ((index < 1) ||
3329		    (index > sc->sc_noport)) {
3330			err = USB_ERR_IOERROR;
3331			goto done;
3332		}
3333		v = EOREAD4(sc, EHCI_PORTSC(index));
3334		DPRINTFN(9, "port status=0x%04x\n", v);
3335		if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3336			if ((v & 0xc000000) == 0x8000000)
3337				i = UPS_HIGH_SPEED;
3338			else if ((v & 0xc000000) == 0x4000000)
3339				i = UPS_LOW_SPEED;
3340			else
3341				i = 0;
3342		} else {
3343			i = UPS_HIGH_SPEED;
3344		}
3345		if (v & EHCI_PS_CS)
3346			i |= UPS_CURRENT_CONNECT_STATUS;
3347		if (v & EHCI_PS_PE)
3348			i |= UPS_PORT_ENABLED;
3349		if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3350			i |= UPS_SUSPEND;
3351		if (v & EHCI_PS_OCA)
3352			i |= UPS_OVERCURRENT_INDICATOR;
3353		if (v & EHCI_PS_PR)
3354			i |= UPS_RESET;
3355		if (v & EHCI_PS_PP)
3356			i |= UPS_PORT_POWER;
3357		USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3358		i = 0;
3359		if (v & EHCI_PS_CSC)
3360			i |= UPS_C_CONNECT_STATUS;
3361		if (v & EHCI_PS_PEC)
3362			i |= UPS_C_PORT_ENABLED;
3363		if (v & EHCI_PS_OCC)
3364			i |= UPS_C_OVERCURRENT_INDICATOR;
3365		if (v & EHCI_PS_FPR)
3366			i |= UPS_C_SUSPEND;
3367		if (sc->sc_isreset)
3368			i |= UPS_C_PORT_RESET;
3369		USETW(sc->sc_hub_desc.ps.wPortChange, i);
3370		len = sizeof(sc->sc_hub_desc.ps);
3371		break;
3372	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3373		err = USB_ERR_IOERROR;
3374		goto done;
3375	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3376		break;
3377	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3378		if ((index < 1) ||
3379		    (index > sc->sc_noport)) {
3380			err = USB_ERR_IOERROR;
3381			goto done;
3382		}
3383		port = EHCI_PORTSC(index);
3384		v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3385		switch (value) {
3386		case UHF_PORT_ENABLE:
3387			EOWRITE4(sc, port, v | EHCI_PS_PE);
3388			break;
3389		case UHF_PORT_SUSPEND:
3390			EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3391			break;
3392		case UHF_PORT_RESET:
3393			DPRINTFN(6, "reset port %d\n", index);
3394#ifdef USB_DEBUG
3395			if (ehcinohighspeed) {
3396				/*
3397				 * Connect USB device to companion
3398				 * controller.
3399				 */
3400				ehci_disown(sc, index, 1);
3401				break;
3402			}
3403#endif
3404			if (EHCI_PS_IS_LOWSPEED(v) &&
3405			    (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3406				/* Low speed device, give up ownership. */
3407				ehci_disown(sc, index, 1);
3408				break;
3409			}
3410			/* Start reset sequence. */
3411			v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3412			EOWRITE4(sc, port, v | EHCI_PS_PR);
3413
3414			/* Wait for reset to complete. */
3415			usb_pause_mtx(&sc->sc_bus.bus_mtx,
3416			    USB_MS_TO_TICKS(usb_port_root_reset_delay));
3417
3418			/* Terminate reset sequence. */
3419			if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3420				EOWRITE4(sc, port, v);
3421
3422			/* Wait for HC to complete reset. */
3423			usb_pause_mtx(&sc->sc_bus.bus_mtx,
3424			    USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3425
3426			v = EOREAD4(sc, port);
3427			DPRINTF("ehci after reset, status=0x%08x\n", v);
3428			if (v & EHCI_PS_PR) {
3429				device_printf(sc->sc_bus.bdev,
3430				    "port reset timeout\n");
3431				err = USB_ERR_TIMEOUT;
3432				goto done;
3433			}
3434			if (!(v & EHCI_PS_PE) &&
3435			    (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3436				/* Not a high speed device, give up ownership.*/
3437				ehci_disown(sc, index, 0);
3438				break;
3439			}
3440			sc->sc_isreset = 1;
3441			DPRINTF("ehci port %d reset, status = 0x%08x\n",
3442			    index, v);
3443			break;
3444
3445		case UHF_PORT_POWER:
3446			DPRINTFN(3, "set port power %d\n", index);
3447			EOWRITE4(sc, port, v | EHCI_PS_PP);
3448			break;
3449
3450		case UHF_PORT_TEST:
3451			DPRINTFN(3, "set port test %d\n", index);
3452			break;
3453
3454		case UHF_PORT_INDICATOR:
3455			DPRINTFN(3, "set port ind %d\n", index);
3456			EOWRITE4(sc, port, v | EHCI_PS_PIC);
3457			break;
3458
3459		default:
3460			err = USB_ERR_IOERROR;
3461			goto done;
3462		}
3463		break;
3464	case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3465	case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3466	case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3467	case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3468		break;
3469	default:
3470		err = USB_ERR_IOERROR;
3471		goto done;
3472	}
3473done:
3474	*plength = len;
3475	*pptr = ptr;
3476	return (err);
3477}
3478
3479static void
3480ehci_xfer_setup(struct usb_setup_params *parm)
3481{
3482	struct usb_page_search page_info;
3483	struct usb_page_cache *pc;
3484	ehci_softc_t *sc;
3485	struct usb_xfer *xfer;
3486	void *last_obj;
3487	uint32_t nqtd;
3488	uint32_t nqh;
3489	uint32_t nsitd;
3490	uint32_t nitd;
3491	uint32_t n;
3492
3493	sc = EHCI_BUS2SC(parm->udev->bus);
3494	xfer = parm->curr_xfer;
3495
3496	nqtd = 0;
3497	nqh = 0;
3498	nsitd = 0;
3499	nitd = 0;
3500
3501	/*
3502	 * compute maximum number of some structures
3503	 */
3504	if (parm->methods == &ehci_device_ctrl_methods) {
3505
3506		/*
3507		 * The proof for the "nqtd" formula is illustrated like
3508		 * this:
3509		 *
3510		 * +------------------------------------+
3511		 * |                                    |
3512		 * |         |remainder ->              |
3513		 * |   +-----+---+                      |
3514		 * |   | xxx | x | frm 0                |
3515		 * |   +-----+---++                     |
3516		 * |   | xxx | xx | frm 1               |
3517		 * |   +-----+----+                     |
3518		 * |            ...                     |
3519		 * +------------------------------------+
3520		 *
3521		 * "xxx" means a completely full USB transfer descriptor
3522		 *
3523		 * "x" and "xx" means a short USB packet
3524		 *
3525		 * For the remainder of an USB transfer modulo
3526		 * "max_data_length" we need two USB transfer descriptors.
3527		 * One to transfer the remaining data and one to finalise
3528		 * with a zero length packet in case the "force_short_xfer"
3529		 * flag is set. We only need two USB transfer descriptors in
3530		 * the case where the transfer length of the first one is a
3531		 * factor of "max_frame_size". The rest of the needed USB
3532		 * transfer descriptors is given by the buffer size divided
3533		 * by the maximum data payload.
3534		 */
3535		parm->hc_max_packet_size = 0x400;
3536		parm->hc_max_packet_count = 1;
3537		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3538		xfer->flags_int.bdma_enable = 1;
3539
3540		usbd_transfer_setup_sub(parm);
3541
3542		nqh = 1;
3543		nqtd = ((2 * xfer->nframes) + 1	/* STATUS */
3544		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3545
3546	} else if (parm->methods == &ehci_device_bulk_methods) {
3547
3548		parm->hc_max_packet_size = 0x400;
3549		parm->hc_max_packet_count = 1;
3550		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3551		xfer->flags_int.bdma_enable = 1;
3552
3553		usbd_transfer_setup_sub(parm);
3554
3555		nqh = 1;
3556		nqtd = ((2 * xfer->nframes)
3557		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3558
3559	} else if (parm->methods == &ehci_device_intr_methods) {
3560
3561		if (parm->speed == USB_SPEED_HIGH) {
3562			parm->hc_max_packet_size = 0x400;
3563			parm->hc_max_packet_count = 3;
3564		} else if (parm->speed == USB_SPEED_FULL) {
3565			parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3566			parm->hc_max_packet_count = 1;
3567		} else {
3568			parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3569			parm->hc_max_packet_count = 1;
3570		}
3571
3572		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3573		xfer->flags_int.bdma_enable = 1;
3574
3575		usbd_transfer_setup_sub(parm);
3576
3577		nqh = 1;
3578		nqtd = ((2 * xfer->nframes)
3579		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3580
3581	} else if (parm->methods == &ehci_device_isoc_fs_methods) {
3582
3583		parm->hc_max_packet_size = 0x3FF;
3584		parm->hc_max_packet_count = 1;
3585		parm->hc_max_frame_size = 0x3FF;
3586		xfer->flags_int.bdma_enable = 1;
3587
3588		usbd_transfer_setup_sub(parm);
3589
3590		nsitd = xfer->nframes;
3591
3592	} else if (parm->methods == &ehci_device_isoc_hs_methods) {
3593
3594		parm->hc_max_packet_size = 0x400;
3595		parm->hc_max_packet_count = 3;
3596		parm->hc_max_frame_size = 0xC00;
3597		xfer->flags_int.bdma_enable = 1;
3598
3599		usbd_transfer_setup_sub(parm);
3600
3601		nitd = ((xfer->nframes + 7) / 8) <<
3602		    usbd_xfer_get_fps_shift(xfer);
3603
3604	} else {
3605
3606		parm->hc_max_packet_size = 0x400;
3607		parm->hc_max_packet_count = 1;
3608		parm->hc_max_frame_size = 0x400;
3609
3610		usbd_transfer_setup_sub(parm);
3611	}
3612
3613alloc_dma_set:
3614
3615	if (parm->err) {
3616		return;
3617	}
3618	/*
3619	 * Allocate queue heads and transfer descriptors
3620	 */
3621	last_obj = NULL;
3622
3623	if (usbd_transfer_setup_sub_malloc(
3624	    parm, &pc, sizeof(ehci_itd_t),
3625	    EHCI_ITD_ALIGN, nitd)) {
3626		parm->err = USB_ERR_NOMEM;
3627		return;
3628	}
3629	if (parm->buf) {
3630		for (n = 0; n != nitd; n++) {
3631			ehci_itd_t *td;
3632
3633			usbd_get_page(pc + n, 0, &page_info);
3634
3635			td = page_info.buffer;
3636
3637			/* init TD */
3638			td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3639			td->obj_next = last_obj;
3640			td->page_cache = pc + n;
3641
3642			last_obj = td;
3643
3644			usb_pc_cpu_flush(pc + n);
3645		}
3646	}
3647	if (usbd_transfer_setup_sub_malloc(
3648	    parm, &pc, sizeof(ehci_sitd_t),
3649	    EHCI_SITD_ALIGN, nsitd)) {
3650		parm->err = USB_ERR_NOMEM;
3651		return;
3652	}
3653	if (parm->buf) {
3654		for (n = 0; n != nsitd; n++) {
3655			ehci_sitd_t *td;
3656
3657			usbd_get_page(pc + n, 0, &page_info);
3658
3659			td = page_info.buffer;
3660
3661			/* init TD */
3662			td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3663			td->obj_next = last_obj;
3664			td->page_cache = pc + n;
3665
3666			last_obj = td;
3667
3668			usb_pc_cpu_flush(pc + n);
3669		}
3670	}
3671	if (usbd_transfer_setup_sub_malloc(
3672	    parm, &pc, sizeof(ehci_qtd_t),
3673	    EHCI_QTD_ALIGN, nqtd)) {
3674		parm->err = USB_ERR_NOMEM;
3675		return;
3676	}
3677	if (parm->buf) {
3678		for (n = 0; n != nqtd; n++) {
3679			ehci_qtd_t *qtd;
3680
3681			usbd_get_page(pc + n, 0, &page_info);
3682
3683			qtd = page_info.buffer;
3684
3685			/* init TD */
3686			qtd->qtd_self = htohc32(sc, page_info.physaddr);
3687			qtd->obj_next = last_obj;
3688			qtd->page_cache = pc + n;
3689
3690			last_obj = qtd;
3691
3692			usb_pc_cpu_flush(pc + n);
3693		}
3694	}
3695	xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3696
3697	last_obj = NULL;
3698
3699	if (usbd_transfer_setup_sub_malloc(
3700	    parm, &pc, sizeof(ehci_qh_t),
3701	    EHCI_QH_ALIGN, nqh)) {
3702		parm->err = USB_ERR_NOMEM;
3703		return;
3704	}
3705	if (parm->buf) {
3706		for (n = 0; n != nqh; n++) {
3707			ehci_qh_t *qh;
3708
3709			usbd_get_page(pc + n, 0, &page_info);
3710
3711			qh = page_info.buffer;
3712
3713			/* init QH */
3714			qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3715			qh->obj_next = last_obj;
3716			qh->page_cache = pc + n;
3717
3718			last_obj = qh;
3719
3720			usb_pc_cpu_flush(pc + n);
3721		}
3722	}
3723	xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3724
3725	if (!xfer->flags_int.curr_dma_set) {
3726		xfer->flags_int.curr_dma_set = 1;
3727		goto alloc_dma_set;
3728	}
3729}
3730
3731static void
3732ehci_xfer_unsetup(struct usb_xfer *xfer)
3733{
3734	return;
3735}
3736
3737static void
3738ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3739    struct usb_endpoint *ep)
3740{
3741	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3742
3743	DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3744	    ep, udev->address,
3745	    edesc->bEndpointAddress, udev->flags.usb_mode,
3746	    sc->sc_addr);
3747
3748	if (udev->device_index != sc->sc_addr) {
3749
3750		if ((udev->speed != USB_SPEED_HIGH) &&
3751		    ((udev->hs_hub_addr == 0) ||
3752		    (udev->hs_port_no == 0) ||
3753		    (udev->parent_hs_hub == NULL) ||
3754		    (udev->parent_hs_hub->hub == NULL))) {
3755			/* We need a transaction translator */
3756			goto done;
3757		}
3758		switch (edesc->bmAttributes & UE_XFERTYPE) {
3759		case UE_CONTROL:
3760			ep->methods = &ehci_device_ctrl_methods;
3761			break;
3762		case UE_INTERRUPT:
3763			ep->methods = &ehci_device_intr_methods;
3764			break;
3765		case UE_ISOCHRONOUS:
3766			if (udev->speed == USB_SPEED_HIGH) {
3767				ep->methods = &ehci_device_isoc_hs_methods;
3768			} else if (udev->speed == USB_SPEED_FULL) {
3769				ep->methods = &ehci_device_isoc_fs_methods;
3770			}
3771			break;
3772		case UE_BULK:
3773			ep->methods = &ehci_device_bulk_methods;
3774			break;
3775		default:
3776			/* do nothing */
3777			break;
3778		}
3779	}
3780done:
3781	return;
3782}
3783
3784static void
3785ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3786{
3787	/*
3788	 * Wait until the hardware has finished any possible use of
3789	 * the transfer descriptor(s) and QH
3790	 */
3791	*pus = (1125);			/* microseconds */
3792}
3793
3794static void
3795ehci_device_resume(struct usb_device *udev)
3796{
3797	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3798	struct usb_xfer *xfer;
3799	struct usb_pipe_methods *methods;
3800
3801	DPRINTF("\n");
3802
3803	USB_BUS_LOCK(udev->bus);
3804
3805	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3806
3807		if (xfer->xroot->udev == udev) {
3808
3809			methods = xfer->endpoint->methods;
3810
3811			if ((methods == &ehci_device_bulk_methods) ||
3812			    (methods == &ehci_device_ctrl_methods)) {
3813				EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3814				    sc->sc_async_p_last);
3815			}
3816			if (methods == &ehci_device_intr_methods) {
3817				EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3818				    sc->sc_intr_p_last[xfer->qh_pos]);
3819			}
3820		}
3821	}
3822
3823	USB_BUS_UNLOCK(udev->bus);
3824
3825	return;
3826}
3827
3828static void
3829ehci_device_suspend(struct usb_device *udev)
3830{
3831	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3832	struct usb_xfer *xfer;
3833	struct usb_pipe_methods *methods;
3834
3835	DPRINTF("\n");
3836
3837	USB_BUS_LOCK(udev->bus);
3838
3839	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3840
3841		if (xfer->xroot->udev == udev) {
3842
3843			methods = xfer->endpoint->methods;
3844
3845			if ((methods == &ehci_device_bulk_methods) ||
3846			    (methods == &ehci_device_ctrl_methods)) {
3847				EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3848				    sc->sc_async_p_last);
3849			}
3850			if (methods == &ehci_device_intr_methods) {
3851				EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3852				    sc->sc_intr_p_last[xfer->qh_pos]);
3853			}
3854		}
3855	}
3856
3857	USB_BUS_UNLOCK(udev->bus);
3858}
3859
3860static void
3861ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3862{
3863	struct ehci_softc *sc = EHCI_BUS2SC(bus);
3864
3865	switch (state) {
3866	case USB_HW_POWER_SUSPEND:
3867	case USB_HW_POWER_SHUTDOWN:
3868		ehci_suspend(sc);
3869		break;
3870	case USB_HW_POWER_RESUME:
3871		ehci_resume(sc);
3872		break;
3873	default:
3874		break;
3875	}
3876}
3877
3878static void
3879ehci_set_hw_power(struct usb_bus *bus)
3880{
3881	ehci_softc_t *sc = EHCI_BUS2SC(bus);
3882	uint32_t temp;
3883	uint32_t flags;
3884
3885	DPRINTF("\n");
3886
3887	USB_BUS_LOCK(bus);
3888
3889	flags = bus->hw_power_state;
3890
3891	temp = EOREAD4(sc, EHCI_USBCMD);
3892
3893	temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3894
3895	if (flags & (USB_HW_POWER_CONTROL |
3896	    USB_HW_POWER_BULK)) {
3897		DPRINTF("Async is active\n");
3898		temp |= EHCI_CMD_ASE;
3899	}
3900	if (flags & (USB_HW_POWER_INTERRUPT |
3901	    USB_HW_POWER_ISOC)) {
3902		DPRINTF("Periodic is active\n");
3903		temp |= EHCI_CMD_PSE;
3904	}
3905	EOWRITE4(sc, EHCI_USBCMD, temp);
3906
3907	USB_BUS_UNLOCK(bus);
3908
3909	return;
3910}
3911
3912static void
3913ehci_start_dma_delay_second(struct usb_xfer *xfer)
3914{
3915	struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3916
3917	DPRINTF("\n");
3918
3919	/* trigger doorbell */
3920	ehci_doorbell_async(sc);
3921
3922	/* give the doorbell 4ms */
3923	usbd_transfer_timeout_ms(xfer,
3924	    (void (*)(void *))&usb_dma_delay_done_cb, 4);
3925}
3926
3927/*
3928 * Ring the doorbell twice before freeing any DMA descriptors. Some host
3929 * controllers apparently cache the QH descriptors and need a message
3930 * that the cache needs to be discarded.
3931 */
3932static void
3933ehci_start_dma_delay(struct usb_xfer *xfer)
3934{
3935	struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3936
3937	DPRINTF("\n");
3938
3939	/* trigger doorbell */
3940	ehci_doorbell_async(sc);
3941
3942	/* give the doorbell 4ms */
3943	usbd_transfer_timeout_ms(xfer,
3944	    (void (*)(void *))&ehci_start_dma_delay_second, 4);
3945}
3946
3947struct usb_bus_methods ehci_bus_methods =
3948{
3949	.endpoint_init = ehci_ep_init,
3950	.xfer_setup = ehci_xfer_setup,
3951	.xfer_unsetup = ehci_xfer_unsetup,
3952	.get_dma_delay = ehci_get_dma_delay,
3953	.device_resume = ehci_device_resume,
3954	.device_suspend = ehci_device_suspend,
3955	.set_hw_power = ehci_set_hw_power,
3956	.set_hw_power_sleep = ehci_set_hw_power_sleep,
3957	.roothub_exec = ehci_roothub_exec,
3958	.xfer_poll = ehci_do_poll,
3959	.start_dma_delay = ehci_start_dma_delay,
3960};
3961