if_tsec.c revision 193096
1/*- 2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27/* 28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29 */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 193096 2009-05-30 15:14:44Z attilio $"); 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_device_polling.h" 35#endif 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/mbuf.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47 48#include <net/bpf.h> 49#include <net/ethernet.h> 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in_systm.h> 58#include <netinet/in.h> 59#include <netinet/ip.h> 60 61#include <machine/bus.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/tsec/if_tsec.h> 67#include <dev/tsec/if_tsecreg.h> 68 69static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71 const char *dname); 72static void tsec_dma_ctl(struct tsec_softc *sc, int state); 73static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74 int fcb_inserted); 75static void tsec_free_dma(struct tsec_softc *sc); 76static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77static int tsec_ifmedia_upd(struct ifnet *ifp); 78static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80 struct mbuf **mbufp, uint32_t *paddr); 81static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82 int nseg, int error); 83static void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84static void tsec_init(void *xsc); 85static void tsec_init_locked(struct tsec_softc *sc); 86static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87static void tsec_reset_mac(struct tsec_softc *sc); 88static void tsec_setfilter(struct tsec_softc *sc); 89static void tsec_set_mac_address(struct tsec_softc *sc); 90static void tsec_start(struct ifnet *ifp); 91static void tsec_start_locked(struct ifnet *ifp); 92static void tsec_stop(struct tsec_softc *sc); 93static void tsec_tick(void *arg); 94static void tsec_watchdog(struct tsec_softc *sc); 95static void tsec_add_sysctls(struct tsec_softc *sc); 96static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98static void tsec_set_rxic(struct tsec_softc *sc); 99static void tsec_set_txic(struct tsec_softc *sc); 100static int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101static void tsec_transmit_intr_locked(struct tsec_softc *sc); 102static void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103static void tsec_offload_setup(struct tsec_softc *sc); 104static void tsec_offload_process_frame(struct tsec_softc *sc, 105 struct mbuf *m); 106static void tsec_setup_multicast(struct tsec_softc *sc); 107static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108 109struct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */ 110 111devclass_t tsec_devclass; 112DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 113MODULE_DEPEND(tsec, ether, 1, 1, 1); 114MODULE_DEPEND(tsec, miibus, 1, 1, 1); 115 116int 117tsec_attach(struct tsec_softc *sc) 118{ 119 uint8_t hwaddr[ETHER_ADDR_LEN]; 120 struct ifnet *ifp; 121 bus_dmamap_t *map_ptr; 122 bus_dmamap_t **map_pptr; 123 int error = 0; 124 int i; 125 126 /* Reset all TSEC counters */ 127 TSEC_TX_RX_COUNTERS_INIT(sc); 128 129 /* Stop DMA engine if enabled by firmware */ 130 tsec_dma_ctl(sc, 0); 131 132 /* Reset MAC */ 133 tsec_reset_mac(sc); 134 135 /* Disable interrupts for now */ 136 tsec_intrs_ctl(sc, 0); 137 138 /* Configure defaults for interrupts coalescing */ 139 sc->rx_ic_time = 768; 140 sc->rx_ic_count = 16; 141 sc->tx_ic_time = 768; 142 sc->tx_ic_count = 16; 143 tsec_set_rxic(sc); 144 tsec_set_txic(sc); 145 tsec_add_sysctls(sc); 146 147 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 148 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 149 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 150 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 151 152 if (error) { 153 tsec_detach(sc); 154 return (ENXIO); 155 } 156 157 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 158 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 159 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 160 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 161 if (error) { 162 tsec_detach(sc); 163 return (ENXIO); 164 } 165 166 /* Allocate a busdma tag for TX mbufs. */ 167 error = bus_dma_tag_create(NULL, /* parent */ 168 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 169 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 170 BUS_SPACE_MAXADDR, /* highaddr */ 171 NULL, NULL, /* filtfunc, filtfuncarg */ 172 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 173 TSEC_TX_NUM_DESC - 1, /* nsegments */ 174 MCLBYTES, 0, /* maxsegsz, flags */ 175 NULL, NULL, /* lockfunc, lockfuncarg */ 176 &sc->tsec_tx_mtag); /* dmat */ 177 if (error) { 178 device_printf(sc->dev, "failed to allocate busdma tag " 179 "(tx mbufs)\n"); 180 tsec_detach(sc); 181 return (ENXIO); 182 } 183 184 /* Allocate a busdma tag for RX mbufs. */ 185 error = bus_dma_tag_create(NULL, /* parent */ 186 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 187 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 188 BUS_SPACE_MAXADDR, /* highaddr */ 189 NULL, NULL, /* filtfunc, filtfuncarg */ 190 MCLBYTES, /* maxsize */ 191 1, /* nsegments */ 192 MCLBYTES, 0, /* maxsegsz, flags */ 193 NULL, NULL, /* lockfunc, lockfuncarg */ 194 &sc->tsec_rx_mtag); /* dmat */ 195 if (error) { 196 device_printf(sc->dev, "failed to allocate busdma tag " 197 "(rx mbufs)\n"); 198 tsec_detach(sc); 199 return (ENXIO); 200 } 201 202 /* Create TX busdma maps */ 203 map_ptr = sc->tx_map_data; 204 map_pptr = sc->tx_map_unused_data; 205 206 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 207 map_pptr[i] = &map_ptr[i]; 208 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 209 if (error) { 210 device_printf(sc->dev, "failed to init TX ring\n"); 211 tsec_detach(sc); 212 return (ENXIO); 213 } 214 } 215 216 /* Create RX busdma maps and zero mbuf handlers */ 217 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 218 error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 219 &sc->rx_data[i].map); 220 if (error) { 221 device_printf(sc->dev, "failed to init RX ring\n"); 222 tsec_detach(sc); 223 return (ENXIO); 224 } 225 sc->rx_data[i].mbuf = NULL; 226 } 227 228 /* Create mbufs for RX buffers */ 229 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 230 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 231 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 232 if (error) { 233 device_printf(sc->dev, "can't load rx DMA map %d, " 234 "error = %d\n", i, error); 235 tsec_detach(sc); 236 return (error); 237 } 238 } 239 240 /* Create network interface for upper layers */ 241 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 242 if (ifp == NULL) { 243 device_printf(sc->dev, "if_alloc() failed\n"); 244 tsec_detach(sc); 245 return (ENOMEM); 246 } 247 248 ifp->if_softc = sc; 249 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 250 ifp->if_mtu = ETHERMTU; 251 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 252 ifp->if_init = tsec_init; 253 ifp->if_start = tsec_start; 254 ifp->if_ioctl = tsec_ioctl; 255 256 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 257 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 258 IFQ_SET_READY(&ifp->if_snd); 259 260 ifp->if_capabilities = IFCAP_VLAN_MTU; 261 if (sc->is_etsec) 262 ifp->if_capabilities |= IFCAP_HWCSUM; 263 264 ifp->if_capenable = ifp->if_capabilities; 265 266#ifdef DEVICE_POLLING 267 /* Advertise that polling is supported */ 268 ifp->if_capabilities |= IFCAP_POLLING; 269#endif 270 271 /* Probe PHY(s) */ 272 error = mii_phy_probe(sc->dev, &sc->tsec_miibus, tsec_ifmedia_upd, 273 tsec_ifmedia_sts); 274 if (error) { 275 device_printf(sc->dev, "MII failed to find PHY!\n"); 276 if_free(ifp); 277 sc->tsec_ifp = NULL; 278 tsec_detach(sc); 279 return (error); 280 } 281 sc->tsec_mii = device_get_softc(sc->tsec_miibus); 282 283 /* Set MAC address */ 284 tsec_get_hwaddr(sc, hwaddr); 285 ether_ifattach(ifp, hwaddr); 286 287 return (0); 288} 289 290int 291tsec_detach(struct tsec_softc *sc) 292{ 293 294#ifdef DEVICE_POLLING 295 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 296 ether_poll_deregister(sc->tsec_ifp); 297#endif 298 299 /* Stop TSEC controller and free TX queue */ 300 if (sc->sc_rres && sc->tsec_ifp) 301 tsec_shutdown(sc->dev); 302 303 /* Detach network interface */ 304 if (sc->tsec_ifp) { 305 ether_ifdetach(sc->tsec_ifp); 306 if_free(sc->tsec_ifp); 307 sc->tsec_ifp = NULL; 308 } 309 310 /* Free DMA resources */ 311 tsec_free_dma(sc); 312 313 return (0); 314} 315 316void 317tsec_shutdown(device_t dev) 318{ 319 struct tsec_softc *sc; 320 321 sc = device_get_softc(dev); 322 323 TSEC_GLOBAL_LOCK(sc); 324 tsec_stop(sc); 325 TSEC_GLOBAL_UNLOCK(sc); 326} 327 328int 329tsec_suspend(device_t dev) 330{ 331 332 /* TODO not implemented! */ 333 return (0); 334} 335 336int 337tsec_resume(device_t dev) 338{ 339 340 /* TODO not implemented! */ 341 return (0); 342} 343 344static void 345tsec_init(void *xsc) 346{ 347 struct tsec_softc *sc = xsc; 348 349 TSEC_GLOBAL_LOCK(sc); 350 tsec_init_locked(sc); 351 TSEC_GLOBAL_UNLOCK(sc); 352} 353 354static void 355tsec_init_locked(struct tsec_softc *sc) 356{ 357 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 358 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 359 struct ifnet *ifp = sc->tsec_ifp; 360 uint32_t timeout, val, i; 361 362 TSEC_GLOBAL_LOCK_ASSERT(sc); 363 tsec_stop(sc); 364 365 /* 366 * These steps are according to the MPC8555E PowerQUICCIII RM: 367 * 14.7 Initialization/Application Information 368 */ 369 370 /* Step 1: soft reset MAC */ 371 tsec_reset_mac(sc); 372 373 /* Step 2: Initialize MACCFG2 */ 374 TSEC_WRITE(sc, TSEC_REG_MACCFG2, 375 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 376 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 377 TSEC_MACCFG2_GMII | /* I/F Mode bit */ 378 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 379 ); 380 381 /* Step 3: Initialize ECNTRL 382 * While the documentation states that R100M is ignored if RPM is 383 * not set, it does seem to be needed to get the orange boxes to 384 * work (which have a Marvell 88E1111 PHY). Go figure. 385 */ 386 387 /* 388 * XXX kludge - use circumstancial evidence to program ECNTRL 389 * correctly. Ideally we need some board information to guide 390 * us here. 391 */ 392 i = TSEC_READ(sc, TSEC_REG_ID2); 393 val = (i & 0xffff) 394 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 395 : TSEC_ECNTRL_R100M; /* Orange + CDS */ 396 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 397 398 /* Step 4: Initialize MAC station address */ 399 tsec_set_mac_address(sc); 400 401 /* 402 * Step 5: Assign a Physical address to the TBI so as to not conflict 403 * with the external PHY physical address 404 */ 405 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 406 407 /* Step 6: Reset the management interface */ 408 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 409 410 /* Step 7: Setup the MII Mgmt clock speed */ 411 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 412 413 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 414 timeout = TSEC_READ_RETRY; 415 while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) & 416 TSEC_MIIMIND_BUSY)) 417 DELAY(TSEC_READ_DELAY); 418 if (timeout == 0) { 419 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 420 return; 421 } 422 423 /* Step 9: Setup the MII Mgmt */ 424 mii_mediachg(sc->tsec_mii); 425 426 /* Step 10: Clear IEVENT register */ 427 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 428 429 /* Step 11: Enable interrupts */ 430#ifdef DEVICE_POLLING 431 /* 432 * ...only if polling is not turned on. Disable interrupts explicitly 433 * if polling is enabled. 434 */ 435 if (ifp->if_capenable & IFCAP_POLLING ) 436 tsec_intrs_ctl(sc, 0); 437 else 438#endif /* DEVICE_POLLING */ 439 tsec_intrs_ctl(sc, 1); 440 441 /* Step 12: Initialize IADDRn */ 442 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 443 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 444 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 445 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 446 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 447 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 448 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 449 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 450 451 /* Step 13: Initialize GADDRn */ 452 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 453 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 454 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 455 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 456 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 457 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 458 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 459 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 460 461 /* Step 14: Initialize RCTRL */ 462 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 463 464 /* Step 15: Initialize DMACTRL */ 465 tsec_dma_ctl(sc, 1); 466 467 /* Step 16: Initialize FIFO_PAUSE_CTRL */ 468 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 469 470 /* 471 * Step 17: Initialize transmit/receive descriptor rings. 472 * Initialize TBASE and RBASE. 473 */ 474 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 475 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 476 477 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 478 tx_desc[i].bufptr = 0; 479 tx_desc[i].length = 0; 480 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 481 TSEC_TXBD_W : 0); 482 } 483 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 484 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 485 486 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 487 rx_desc[i].bufptr = sc->rx_data[i].paddr; 488 rx_desc[i].length = 0; 489 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 490 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 491 } 492 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 494 495 /* Step 18: Initialize the maximum receive buffer length */ 496 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 497 498 /* Step 19: Configure ethernet frame sizes */ 499 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 500 tsec_set_mtu(sc, ifp->if_mtu); 501 502 /* Step 20: Enable Rx and RxBD sdata snooping */ 503 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 504 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 505 506 /* Step 21: Reset collision counters in hardware */ 507 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 508 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 509 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 510 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 511 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 512 513 /* Step 22: Mask all CAM interrupts */ 514 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 515 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 516 517 /* Step 23: Enable Rx and Tx */ 518 val = TSEC_READ(sc, TSEC_REG_MACCFG1); 519 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 520 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 521 522 /* Step 24: Reset TSEC counters for Tx and Rx rings */ 523 TSEC_TX_RX_COUNTERS_INIT(sc); 524 525 /* Step 25: Setup TCP/IP Off-Load engine */ 526 if (sc->is_etsec) 527 tsec_offload_setup(sc); 528 529 /* Step 26: Setup multicast filters */ 530 tsec_setup_multicast(sc); 531 532 /* Step 27: Activate network interface */ 533 ifp->if_drv_flags |= IFF_DRV_RUNNING; 534 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 535 sc->tsec_if_flags = ifp->if_flags; 536 sc->tsec_watchdog = 0; 537 538 /* Schedule watchdog timeout */ 539 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 540} 541 542static void 543tsec_set_mac_address(struct tsec_softc *sc) 544{ 545 uint32_t macbuf[2] = { 0, 0 }; 546 char *macbufp, *curmac; 547 int i; 548 549 TSEC_GLOBAL_LOCK_ASSERT(sc); 550 551 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 552 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, 553 sizeof(macbuf))); 554 555 macbufp = (char *)macbuf; 556 curmac = (char *)IF_LLADDR(sc->tsec_ifp); 557 558 /* Correct order of MAC address bytes */ 559 for (i = 1; i <= ETHER_ADDR_LEN; i++) 560 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 561 562 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 563 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 564 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 565} 566 567/* 568 * DMA control function, if argument state is: 569 * 0 - DMA engine will be disabled 570 * 1 - DMA engine will be enabled 571 */ 572static void 573tsec_dma_ctl(struct tsec_softc *sc, int state) 574{ 575 device_t dev; 576 uint32_t dma_flags, timeout; 577 578 dev = sc->dev; 579 580 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 581 582 switch (state) { 583 case 0: 584 /* Temporarily clear stop graceful stop bits. */ 585 tsec_dma_ctl(sc, 1000); 586 587 /* Set it again */ 588 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 589 break; 590 case 1000: 591 case 1: 592 /* Set write with response (WWR), wait (WOP) and snoop bits */ 593 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 594 DMACTRL_WWR | DMACTRL_WOP); 595 596 /* Clear graceful stop bits */ 597 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 598 break; 599 default: 600 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 601 state); 602 } 603 604 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 605 606 switch (state) { 607 case 0: 608 /* Wait for DMA stop */ 609 timeout = TSEC_READ_RETRY; 610 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 611 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 612 DELAY(TSEC_READ_DELAY); 613 614 if (timeout == 0) 615 device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 616 break; 617 case 1: 618 /* Restart transmission function */ 619 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 620 } 621} 622 623/* 624 * Interrupts control function, if argument state is: 625 * 0 - all TSEC interrupts will be masked 626 * 1 - all TSEC interrupts will be unmasked 627 */ 628static void 629tsec_intrs_ctl(struct tsec_softc *sc, int state) 630{ 631 device_t dev; 632 633 dev = sc->dev; 634 635 switch (state) { 636 case 0: 637 TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 638 break; 639 case 1: 640 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 641 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 642 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 643 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 644 break; 645 default: 646 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 647 state); 648 } 649} 650 651static void 652tsec_reset_mac(struct tsec_softc *sc) 653{ 654 uint32_t maccfg1_flags; 655 656 /* Set soft reset bit */ 657 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 658 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 659 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 660 661 /* Clear soft reset bit */ 662 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 663 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 664 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 665} 666 667static void 668tsec_watchdog(struct tsec_softc *sc) 669{ 670 struct ifnet *ifp; 671 672 TSEC_GLOBAL_LOCK_ASSERT(sc); 673 674 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 675 return; 676 677 ifp = sc->tsec_ifp; 678 ifp->if_oerrors++; 679 if_printf(ifp, "watchdog timeout\n"); 680 681 tsec_stop(sc); 682 tsec_init_locked(sc); 683} 684 685static void 686tsec_start(struct ifnet *ifp) 687{ 688 struct tsec_softc *sc = ifp->if_softc; 689 690 TSEC_TRANSMIT_LOCK(sc); 691 tsec_start_locked(ifp); 692 TSEC_TRANSMIT_UNLOCK(sc); 693} 694 695static void 696tsec_start_locked(struct ifnet *ifp) 697{ 698 struct tsec_softc *sc; 699 struct mbuf *m0, *mtmp; 700 struct tsec_tx_fcb *tx_fcb; 701 unsigned int queued = 0; 702 int csum_flags, fcb_inserted = 0; 703 704 sc = ifp->if_softc; 705 706 TSEC_TRANSMIT_LOCK_ASSERT(sc); 707 708 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 709 IFF_DRV_RUNNING) 710 return; 711 712 if (sc->tsec_link == 0) 713 return; 714 715 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 716 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 717 718 for (;;) { 719 /* Get packet from the queue */ 720 IF_DEQUEUE(&ifp->if_snd, m0); 721 if (m0 == NULL) 722 break; 723 724 /* Insert TCP/IP Off-load frame control block */ 725 csum_flags = m0->m_pkthdr.csum_flags; 726 if (csum_flags) { 727 728 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT); 729 if (m0 == NULL) 730 break; 731 732 tx_fcb = mtod(m0, struct tsec_tx_fcb *); 733 tx_fcb->flags = 0; 734 tx_fcb->l3_offset = ETHER_HDR_LEN; 735 tx_fcb->l4_offset = sizeof(struct ip); 736 737 if (csum_flags & CSUM_IP) 738 tx_fcb->flags |= TSEC_TX_FCB_IP4 | 739 TSEC_TX_FCB_CSUM_IP; 740 741 if (csum_flags & CSUM_TCP) 742 tx_fcb->flags |= TSEC_TX_FCB_TCP | 743 TSEC_TX_FCB_CSUM_TCP_UDP; 744 745 if (csum_flags & CSUM_UDP) 746 tx_fcb->flags |= TSEC_TX_FCB_UDP | 747 TSEC_TX_FCB_CSUM_TCP_UDP; 748 749 fcb_inserted = 1; 750 } 751 752 mtmp = m_defrag(m0, M_DONTWAIT); 753 if (mtmp) 754 m0 = mtmp; 755 756 if (tsec_encap(sc, m0, fcb_inserted)) { 757 IF_PREPEND(&ifp->if_snd, m0); 758 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 759 break; 760 } 761 queued++; 762 BPF_MTAP(ifp, m0); 763 } 764 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 765 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 766 767 if (queued) { 768 /* Enable transmitter and watchdog timer */ 769 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 770 sc->tsec_watchdog = 5; 771 } 772} 773 774static int 775tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 776{ 777 struct tsec_desc *tx_desc = NULL; 778 struct ifnet *ifp; 779 bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 780 bus_dmamap_t *mapp; 781 int csum_flag = 0, error, seg, nsegs; 782 783 TSEC_TRANSMIT_LOCK_ASSERT(sc); 784 785 ifp = sc->tsec_ifp; 786 787 if (TSEC_FREE_TX_DESC(sc) == 0) { 788 /* No free descriptors */ 789 return (-1); 790 } 791 792 /* Fetch unused map */ 793 mapp = TSEC_ALLOC_TX_MAP(sc); 794 795 /* Create mapping in DMA memory */ 796 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 797 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 798 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 799 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 800 TSEC_FREE_TX_MAP(sc, mapp); 801 return ((error != 0) ? error : -1); 802 } 803 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 804 805 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 806 if_printf(ifp, "TX buffer has %d segments\n", nsegs); 807 808 if (fcb_inserted) 809 csum_flag = TSEC_TXBD_TOE; 810 811 /* Everything is ok, now we can send buffers */ 812 for (seg = 0; seg < nsegs; seg++) { 813 tx_desc = TSEC_GET_CUR_TX_DESC(sc); 814 815 tx_desc->length = segs[seg].ds_len; 816 tx_desc->bufptr = segs[seg].ds_addr; 817 818 /* 819 * Set flags: 820 * - wrap 821 * - checksum 822 * - ready to send 823 * - transmit the CRC sequence after the last data byte 824 * - interrupt after the last buffer 825 */ 826 tx_desc->flags = 827 (tx_desc->flags & TSEC_TXBD_W) | 828 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 829 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 830 } 831 832 /* Save mbuf and DMA mapping for release at later stage */ 833 TSEC_PUT_TX_MBUF(sc, m0); 834 TSEC_PUT_TX_MAP(sc, mapp); 835 836 return (0); 837} 838 839static void 840tsec_setfilter(struct tsec_softc *sc) 841{ 842 struct ifnet *ifp; 843 uint32_t flags; 844 845 ifp = sc->tsec_ifp; 846 flags = TSEC_READ(sc, TSEC_REG_RCTRL); 847 848 /* Promiscuous mode */ 849 if (ifp->if_flags & IFF_PROMISC) 850 flags |= TSEC_RCTRL_PROM; 851 else 852 flags &= ~TSEC_RCTRL_PROM; 853 854 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 855} 856 857#ifdef DEVICE_POLLING 858static poll_handler_t tsec_poll; 859 860static int 861tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 862{ 863 uint32_t ie; 864 struct tsec_softc *sc = ifp->if_softc; 865 int rx_npkts; 866 867 rx_npkts = 0; 868 869 TSEC_GLOBAL_LOCK(sc); 870 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 871 TSEC_GLOBAL_UNLOCK(sc); 872 return (rx_npkts); 873 } 874 875 if (cmd == POLL_AND_CHECK_STATUS) { 876 tsec_error_intr_locked(sc, count); 877 878 /* Clear all events reported */ 879 ie = TSEC_READ(sc, TSEC_REG_IEVENT); 880 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 881 } 882 883 tsec_transmit_intr_locked(sc); 884 885 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 886 887 rx_npkts = tsec_receive_intr_locked(sc, count); 888 889 TSEC_RECEIVE_UNLOCK(sc); 890 891 return (rx_npkts); 892} 893#endif /* DEVICE_POLLING */ 894 895static int 896tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 897{ 898 struct tsec_softc *sc = ifp->if_softc; 899 struct ifreq *ifr = (struct ifreq *)data; 900 device_t dev; 901 int mask, error = 0; 902 903 dev = sc->dev; 904 905 switch (command) { 906 case SIOCSIFMTU: 907 TSEC_GLOBAL_LOCK(sc); 908 if (tsec_set_mtu(sc, ifr->ifr_mtu)) 909 ifp->if_mtu = ifr->ifr_mtu; 910 else 911 error = EINVAL; 912 TSEC_GLOBAL_UNLOCK(sc); 913 break; 914 case SIOCSIFFLAGS: 915 TSEC_GLOBAL_LOCK(sc); 916 if (ifp->if_flags & IFF_UP) { 917 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 918 if ((sc->tsec_if_flags ^ ifp->if_flags) & 919 IFF_PROMISC) 920 tsec_setfilter(sc); 921 922 if ((sc->tsec_if_flags ^ ifp->if_flags) & 923 IFF_ALLMULTI) 924 tsec_setup_multicast(sc); 925 } else 926 tsec_init_locked(sc); 927 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 928 tsec_stop(sc); 929 930 sc->tsec_if_flags = ifp->if_flags; 931 TSEC_GLOBAL_UNLOCK(sc); 932 break; 933 case SIOCADDMULTI: 934 case SIOCDELMULTI: 935 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 936 TSEC_GLOBAL_LOCK(sc); 937 tsec_setup_multicast(sc); 938 TSEC_GLOBAL_UNLOCK(sc); 939 } 940 case SIOCGIFMEDIA: 941 case SIOCSIFMEDIA: 942 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 943 command); 944 break; 945 case SIOCSIFCAP: 946 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 947 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 948 TSEC_GLOBAL_LOCK(sc); 949 ifp->if_capenable &= ~IFCAP_HWCSUM; 950 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 951 tsec_offload_setup(sc); 952 TSEC_GLOBAL_UNLOCK(sc); 953 } 954#ifdef DEVICE_POLLING 955 if (mask & IFCAP_POLLING) { 956 if (ifr->ifr_reqcap & IFCAP_POLLING) { 957 error = ether_poll_register(tsec_poll, ifp); 958 if (error) 959 return (error); 960 961 TSEC_GLOBAL_LOCK(sc); 962 /* Disable interrupts */ 963 tsec_intrs_ctl(sc, 0); 964 ifp->if_capenable |= IFCAP_POLLING; 965 TSEC_GLOBAL_UNLOCK(sc); 966 } else { 967 error = ether_poll_deregister(ifp); 968 TSEC_GLOBAL_LOCK(sc); 969 /* Enable interrupts */ 970 tsec_intrs_ctl(sc, 1); 971 ifp->if_capenable &= ~IFCAP_POLLING; 972 TSEC_GLOBAL_UNLOCK(sc); 973 } 974 } 975#endif 976 break; 977 978 default: 979 error = ether_ioctl(ifp, command, data); 980 } 981 982 /* Flush buffers if not empty */ 983 if (ifp->if_flags & IFF_UP) 984 tsec_start(ifp); 985 return (error); 986} 987 988static int 989tsec_ifmedia_upd(struct ifnet *ifp) 990{ 991 struct tsec_softc *sc = ifp->if_softc; 992 struct mii_data *mii; 993 994 TSEC_TRANSMIT_LOCK(sc); 995 996 mii = sc->tsec_mii; 997 mii_mediachg(mii); 998 999 TSEC_TRANSMIT_UNLOCK(sc); 1000 return (0); 1001} 1002 1003static void 1004tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1005{ 1006 struct tsec_softc *sc = ifp->if_softc; 1007 struct mii_data *mii; 1008 1009 TSEC_TRANSMIT_LOCK(sc); 1010 1011 mii = sc->tsec_mii; 1012 mii_pollstat(mii); 1013 1014 ifmr->ifm_active = mii->mii_media_active; 1015 ifmr->ifm_status = mii->mii_media_status; 1016 1017 TSEC_TRANSMIT_UNLOCK(sc); 1018} 1019 1020static int 1021tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1022 uint32_t *paddr) 1023{ 1024 struct mbuf *new_mbuf; 1025 bus_dma_segment_t seg[1]; 1026 int error, nsegs; 1027 1028 KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1029 1030 new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1031 if (new_mbuf == NULL) 1032 return (ENOBUFS); 1033 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1034 1035 if (*mbufp) { 1036 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1037 bus_dmamap_unload(tag, map); 1038 } 1039 1040 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1041 BUS_DMA_NOWAIT); 1042 KASSERT(nsegs == 1, ("Too many segments returned!")); 1043 if (nsegs != 1 || error) 1044 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1045 1046#if 0 1047 if (error) { 1048 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1049 error); 1050 m_freem(new_mbuf); 1051 return (ENOBUFS); 1052 } 1053#endif 1054 1055#if 0 1056 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1057 ("Wrong alignment of RX buffer!")); 1058#endif 1059 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1060 1061 (*mbufp) = new_mbuf; 1062 (*paddr) = seg->ds_addr; 1063 return (0); 1064} 1065 1066static void 1067tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1068{ 1069 u_int32_t *paddr; 1070 1071 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1072 paddr = arg; 1073 *paddr = segs->ds_addr; 1074} 1075 1076static int 1077tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1078 bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1079{ 1080 int error; 1081 1082 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1083 error = bus_dma_tag_create(NULL, /* parent */ 1084 PAGE_SIZE, 0, /* alignment, boundary */ 1085 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1086 BUS_SPACE_MAXADDR, /* highaddr */ 1087 NULL, NULL, /* filtfunc, filtfuncarg */ 1088 dsize, 1, /* maxsize, nsegments */ 1089 dsize, 0, /* maxsegsz, flags */ 1090 NULL, NULL, /* lockfunc, lockfuncarg */ 1091 dtag); /* dmat */ 1092 1093 if (error) { 1094 device_printf(dev, "failed to allocate busdma %s tag\n", 1095 dname); 1096 (*vaddr) = NULL; 1097 return (ENXIO); 1098 } 1099 1100 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1101 dmap); 1102 if (error) { 1103 device_printf(dev, "failed to allocate %s DMA safe memory\n", 1104 dname); 1105 bus_dma_tag_destroy(*dtag); 1106 (*vaddr) = NULL; 1107 return (ENXIO); 1108 } 1109 1110 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1111 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1112 if (error) { 1113 device_printf(dev, "cannot get address of the %s " 1114 "descriptors\n", dname); 1115 bus_dmamem_free(*dtag, *vaddr, *dmap); 1116 bus_dma_tag_destroy(*dtag); 1117 (*vaddr) = NULL; 1118 return (ENXIO); 1119 } 1120 1121 return (0); 1122} 1123 1124static void 1125tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1126{ 1127 1128 if (vaddr == NULL) 1129 return; 1130 1131 /* Unmap descriptors from DMA memory */ 1132 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1133 BUS_DMASYNC_POSTWRITE); 1134 bus_dmamap_unload(dtag, dmap); 1135 1136 /* Free descriptors memory */ 1137 bus_dmamem_free(dtag, vaddr, dmap); 1138 1139 /* Destroy descriptors tag */ 1140 bus_dma_tag_destroy(dtag); 1141} 1142 1143static void 1144tsec_free_dma(struct tsec_softc *sc) 1145{ 1146 int i; 1147 1148 /* Free TX maps */ 1149 for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1150 if (sc->tx_map_data[i] != NULL) 1151 bus_dmamap_destroy(sc->tsec_tx_mtag, 1152 sc->tx_map_data[i]); 1153 /* Destroy tag for TX mbufs */ 1154 bus_dma_tag_destroy(sc->tsec_tx_mtag); 1155 1156 /* Free RX mbufs and maps */ 1157 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1158 if (sc->rx_data[i].mbuf) { 1159 /* Unload buffer from DMA */ 1160 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1161 BUS_DMASYNC_POSTREAD); 1162 bus_dmamap_unload(sc->tsec_rx_mtag, 1163 sc->rx_data[i].map); 1164 1165 /* Free buffer */ 1166 m_freem(sc->rx_data[i].mbuf); 1167 } 1168 /* Destroy map for this buffer */ 1169 if (sc->rx_data[i].map != NULL) 1170 bus_dmamap_destroy(sc->tsec_rx_mtag, 1171 sc->rx_data[i].map); 1172 } 1173 /* Destroy tag for RX mbufs */ 1174 bus_dma_tag_destroy(sc->tsec_rx_mtag); 1175 1176 /* Unload TX/RX descriptors */ 1177 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1178 sc->tsec_tx_vaddr); 1179 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1180 sc->tsec_rx_vaddr); 1181} 1182 1183static void 1184tsec_stop(struct tsec_softc *sc) 1185{ 1186 struct ifnet *ifp; 1187 struct mbuf *m0; 1188 bus_dmamap_t *mapp; 1189 uint32_t tmpval; 1190 1191 TSEC_GLOBAL_LOCK_ASSERT(sc); 1192 1193 ifp = sc->tsec_ifp; 1194 1195 /* Disable interface and watchdog timer */ 1196 callout_stop(&sc->tsec_callout); 1197 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1198 sc->tsec_watchdog = 0; 1199 1200 /* Disable all interrupts and stop DMA */ 1201 tsec_intrs_ctl(sc, 0); 1202 tsec_dma_ctl(sc, 0); 1203 1204 /* Remove pending data from TX queue */ 1205 while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1206 m0 = TSEC_GET_TX_MBUF(sc); 1207 mapp = TSEC_GET_TX_MAP(sc); 1208 1209 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1210 BUS_DMASYNC_POSTWRITE); 1211 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1212 1213 TSEC_FREE_TX_MAP(sc, mapp); 1214 m_freem(m0); 1215 } 1216 1217 /* Disable RX and TX */ 1218 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1219 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1220 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1221 DELAY(10); 1222} 1223 1224static void 1225tsec_tick(void *arg) 1226{ 1227 struct tsec_softc *sc = arg; 1228 struct ifnet *ifp; 1229 int link; 1230 1231 TSEC_GLOBAL_LOCK(sc); 1232 1233 tsec_watchdog(sc); 1234 1235 ifp = sc->tsec_ifp; 1236 link = sc->tsec_link; 1237 1238 mii_tick(sc->tsec_mii); 1239 1240 if (link == 0 && sc->tsec_link == 1 && 1241 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1242 tsec_start_locked(ifp); 1243 1244 /* Schedule another timeout one second from now. */ 1245 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1246 1247 TSEC_GLOBAL_UNLOCK(sc); 1248} 1249 1250/* 1251 * This is the core RX routine. It replenishes mbufs in the descriptor and 1252 * sends data which have been dma'ed into host memory to upper layer. 1253 * 1254 * Loops at most count times if count is > 0, or until done if count < 0. 1255 */ 1256static int 1257tsec_receive_intr_locked(struct tsec_softc *sc, int count) 1258{ 1259 struct tsec_desc *rx_desc; 1260 struct ifnet *ifp; 1261 struct rx_data_type *rx_data; 1262 struct mbuf *m; 1263 device_t dev; 1264 uint32_t i; 1265 int c, rx_npkts; 1266 uint16_t flags; 1267 1268 TSEC_RECEIVE_LOCK_ASSERT(sc); 1269 1270 ifp = sc->tsec_ifp; 1271 rx_data = sc->rx_data; 1272 dev = sc->dev; 1273 rx_npkts = 0; 1274 1275 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1276 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1277 1278 for (c = 0; ; c++) { 1279 if (count >= 0 && count-- == 0) 1280 break; 1281 1282 rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1283 flags = rx_desc->flags; 1284 1285 /* Check if there is anything to receive */ 1286 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1287 /* 1288 * Avoid generating another interrupt 1289 */ 1290 if (flags & TSEC_RXBD_E) 1291 TSEC_WRITE(sc, TSEC_REG_IEVENT, 1292 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1293 /* 1294 * We didn't consume current descriptor and have to 1295 * return it to the queue 1296 */ 1297 TSEC_BACK_CUR_RX_DESC(sc); 1298 break; 1299 } 1300 1301 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1302 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1303 1304 rx_desc->length = 0; 1305 rx_desc->flags = (rx_desc->flags & 1306 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1307 1308 if (sc->frame != NULL) { 1309 m_free(sc->frame); 1310 sc->frame = NULL; 1311 } 1312 1313 continue; 1314 } 1315 1316 /* Ok... process frame */ 1317 i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1318 m = rx_data[i].mbuf; 1319 m->m_len = rx_desc->length; 1320 1321 if (sc->frame != NULL) { 1322 if ((flags & TSEC_RXBD_L) != 0) 1323 m->m_len -= m_length(sc->frame, NULL); 1324 1325 m->m_flags &= ~M_PKTHDR; 1326 m_cat(sc->frame, m); 1327 } else { 1328 sc->frame = m; 1329 } 1330 1331 m = NULL; 1332 1333 if ((flags & TSEC_RXBD_L) != 0) { 1334 m = sc->frame; 1335 sc->frame = NULL; 1336 } 1337 1338 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1339 &rx_data[i].mbuf, &rx_data[i].paddr)) { 1340 ifp->if_ierrors++; 1341 /* 1342 * We ran out of mbufs; didn't consume current 1343 * descriptor and have to return it to the queue. 1344 */ 1345 TSEC_BACK_CUR_RX_DESC(sc); 1346 break; 1347 } 1348 1349 /* Attach new buffer to descriptor and clear flags */ 1350 rx_desc->bufptr = rx_data[i].paddr; 1351 rx_desc->length = 0; 1352 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1353 TSEC_RXBD_E | TSEC_RXBD_I; 1354 1355 if (m != NULL) { 1356 m->m_pkthdr.rcvif = ifp; 1357 1358 m_fixhdr(m); 1359 m_adj(m, -ETHER_CRC_LEN); 1360 1361 if (sc->is_etsec) 1362 tsec_offload_process_frame(sc, m); 1363 1364 TSEC_RECEIVE_UNLOCK(sc); 1365 (*ifp->if_input)(ifp, m); 1366 TSEC_RECEIVE_LOCK(sc); 1367 rx_npkts++; 1368 } 1369 } 1370 1371 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1372 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1373 1374 /* 1375 * Make sure TSEC receiver is not halted. 1376 * 1377 * Various conditions can stop the TSEC receiver, but not all are 1378 * signaled and handled by error interrupt, so make sure the receiver 1379 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1380 * halted, and is harmless if already running. 1381 */ 1382 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1383 return (rx_npkts); 1384} 1385 1386void 1387tsec_receive_intr(void *arg) 1388{ 1389 struct tsec_softc *sc = arg; 1390 1391 TSEC_RECEIVE_LOCK(sc); 1392 1393#ifdef DEVICE_POLLING 1394 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1395 TSEC_RECEIVE_UNLOCK(sc); 1396 return; 1397 } 1398#endif 1399 1400 /* Confirm the interrupt was received by driver */ 1401 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1402 tsec_receive_intr_locked(sc, -1); 1403 1404 TSEC_RECEIVE_UNLOCK(sc); 1405} 1406 1407static void 1408tsec_transmit_intr_locked(struct tsec_softc *sc) 1409{ 1410 struct tsec_desc *tx_desc; 1411 struct ifnet *ifp; 1412 struct mbuf *m0; 1413 bus_dmamap_t *mapp; 1414 int send = 0; 1415 1416 TSEC_TRANSMIT_LOCK_ASSERT(sc); 1417 1418 ifp = sc->tsec_ifp; 1419 1420 /* Update collision statistics */ 1421 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1422 1423 /* Reset collision counters in hardware */ 1424 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1425 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1426 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1427 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1428 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1429 1430 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1431 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1432 1433 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1434 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1435 if (tx_desc->flags & TSEC_TXBD_R) { 1436 TSEC_BACK_DIRTY_TX_DESC(sc); 1437 break; 1438 } 1439 1440 if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1441 continue; 1442 1443 /* 1444 * This is the last buf in this packet, so unmap and free it. 1445 */ 1446 m0 = TSEC_GET_TX_MBUF(sc); 1447 mapp = TSEC_GET_TX_MAP(sc); 1448 1449 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1450 BUS_DMASYNC_POSTWRITE); 1451 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1452 1453 TSEC_FREE_TX_MAP(sc, mapp); 1454 m_freem(m0); 1455 1456 ifp->if_opackets++; 1457 send = 1; 1458 } 1459 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1460 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1461 1462 if (send) { 1463 /* Now send anything that was pending */ 1464 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1465 tsec_start_locked(ifp); 1466 1467 /* Stop wathdog if all sent */ 1468 if (TSEC_EMPTYQ_TX_MBUF(sc)) 1469 sc->tsec_watchdog = 0; 1470 } 1471} 1472 1473void 1474tsec_transmit_intr(void *arg) 1475{ 1476 struct tsec_softc *sc = arg; 1477 1478 TSEC_TRANSMIT_LOCK(sc); 1479 1480#ifdef DEVICE_POLLING 1481 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1482 TSEC_TRANSMIT_UNLOCK(sc); 1483 return; 1484 } 1485#endif 1486 /* Confirm the interrupt was received by driver */ 1487 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1488 tsec_transmit_intr_locked(sc); 1489 1490 TSEC_TRANSMIT_UNLOCK(sc); 1491} 1492 1493static void 1494tsec_error_intr_locked(struct tsec_softc *sc, int count) 1495{ 1496 struct ifnet *ifp; 1497 uint32_t eflags; 1498 1499 TSEC_GLOBAL_LOCK_ASSERT(sc); 1500 1501 ifp = sc->tsec_ifp; 1502 1503 eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1504 1505 /* Clear events bits in hardware */ 1506 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1507 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1508 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1509 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1510 1511 /* Check transmitter errors */ 1512 if (eflags & TSEC_IEVENT_TXE) { 1513 ifp->if_oerrors++; 1514 1515 if (eflags & TSEC_IEVENT_LC) 1516 ifp->if_collisions++; 1517 1518 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1519 } 1520 1521 /* Check receiver errors */ 1522 if (eflags & TSEC_IEVENT_BSY) { 1523 ifp->if_ierrors++; 1524 ifp->if_iqdrops++; 1525 1526 /* Get data from RX buffers */ 1527 tsec_receive_intr_locked(sc, count); 1528 } 1529 1530 if (ifp->if_flags & IFF_DEBUG) 1531 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1532 eflags); 1533 1534 if (eflags & TSEC_IEVENT_EBERR) { 1535 if_printf(ifp, "System bus error occurred during" 1536 "DMA transaction (flags: 0x%x)\n", eflags); 1537 tsec_init_locked(sc); 1538 } 1539 1540 if (eflags & TSEC_IEVENT_BABT) 1541 ifp->if_oerrors++; 1542 1543 if (eflags & TSEC_IEVENT_BABR) 1544 ifp->if_ierrors++; 1545} 1546 1547void 1548tsec_error_intr(void *arg) 1549{ 1550 struct tsec_softc *sc = arg; 1551 1552 TSEC_GLOBAL_LOCK(sc); 1553 tsec_error_intr_locked(sc, -1); 1554 TSEC_GLOBAL_UNLOCK(sc); 1555} 1556 1557int 1558tsec_miibus_readreg(device_t dev, int phy, int reg) 1559{ 1560 struct tsec_softc *sc; 1561 uint32_t timeout; 1562 1563 sc = device_get_softc(dev); 1564 1565 if (device_get_unit(dev) != phy) 1566 return (0); 1567 1568 sc = tsec0_sc; 1569 1570 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1571 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1572 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1573 1574 timeout = TSEC_READ_RETRY; 1575 while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) & 1576 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1577 DELAY(TSEC_READ_DELAY); 1578 1579 if (timeout == 0) 1580 device_printf(dev, "Timeout while reading from PHY!\n"); 1581 1582 return (TSEC_READ(sc, TSEC_REG_MIIMSTAT)); 1583} 1584 1585void 1586tsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1587{ 1588 struct tsec_softc *sc; 1589 uint32_t timeout; 1590 1591 sc = device_get_softc(dev); 1592 1593 if (device_get_unit(dev) != phy) 1594 device_printf(dev, "Trying to write to an alien PHY(%d)\n", 1595 phy); 1596 1597 sc = tsec0_sc; 1598 1599 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1600 TSEC_WRITE(sc, TSEC_REG_MIIMCON, value); 1601 1602 timeout = TSEC_READ_RETRY; 1603 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & 1604 TSEC_MIIMIND_BUSY)) 1605 DELAY(TSEC_READ_DELAY); 1606 1607 if (timeout == 0) 1608 device_printf(dev, "Timeout while writing to PHY!\n"); 1609} 1610 1611void 1612tsec_miibus_statchg(device_t dev) 1613{ 1614 struct tsec_softc *sc; 1615 struct mii_data *mii; 1616 uint32_t ecntrl, id, tmp; 1617 int link; 1618 1619 sc = device_get_softc(dev); 1620 mii = sc->tsec_mii; 1621 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1622 1623 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1624 1625 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1626 tmp |= TSEC_MACCFG2_FULLDUPLEX; 1627 else 1628 tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1629 1630 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1631 case IFM_1000_T: 1632 case IFM_1000_SX: 1633 tmp |= TSEC_MACCFG2_GMII; 1634 sc->tsec_link = link; 1635 break; 1636 case IFM_100_TX: 1637 case IFM_10_T: 1638 tmp |= TSEC_MACCFG2_MII; 1639 sc->tsec_link = link; 1640 break; 1641 case IFM_NONE: 1642 if (link) 1643 device_printf(dev, "No speed selected but link " 1644 "active!\n"); 1645 sc->tsec_link = 0; 1646 return; 1647 default: 1648 sc->tsec_link = 0; 1649 device_printf(dev, "Unknown speed (%d), link %s!\n", 1650 IFM_SUBTYPE(mii->mii_media_active), 1651 ((link) ? "up" : "down")); 1652 return; 1653 } 1654 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1655 1656 /* XXX kludge - use circumstantial evidence for reduced mode. */ 1657 id = TSEC_READ(sc, TSEC_REG_ID2); 1658 if (id & 0xffff) { 1659 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1660 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1661 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1662 } 1663} 1664 1665static void 1666tsec_add_sysctls(struct tsec_softc *sc) 1667{ 1668 struct sysctl_ctx_list *ctx; 1669 struct sysctl_oid_list *children; 1670 struct sysctl_oid *tree; 1671 1672 ctx = device_get_sysctl_ctx(sc->dev); 1673 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1674 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1675 CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1676 children = SYSCTL_CHILDREN(tree); 1677 1678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1679 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1680 "I", "IC RX time threshold (0-65535)"); 1681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1682 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1683 "I", "IC RX frame count threshold (0-255)"); 1684 1685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1686 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1687 "I", "IC TX time threshold (0-65535)"); 1688 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1689 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1690 "I", "IC TX frame count threshold (0-255)"); 1691} 1692 1693/* 1694 * With Interrupt Coalescing (IC) active, a transmit/receive frame 1695 * interrupt is raised either upon: 1696 * 1697 * - threshold-defined period of time elapsed, or 1698 * - threshold-defined number of frames is received/transmitted, 1699 * whichever occurs first. 1700 * 1701 * The following sysctls regulate IC behaviour (for TX/RX separately): 1702 * 1703 * dev.tsec.<unit>.int_coal.rx_time 1704 * dev.tsec.<unit>.int_coal.rx_count 1705 * dev.tsec.<unit>.int_coal.tx_time 1706 * dev.tsec.<unit>.int_coal.tx_count 1707 * 1708 * Values: 1709 * 1710 * - 0 for either time or count disables IC on the given TX/RX path 1711 * 1712 * - count: 1-255 (expresses frame count number; note that value of 1 is 1713 * effectively IC off) 1714 * 1715 * - time: 1-65535 (value corresponds to a real time period and is 1716 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1717 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1718 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1719 * TSEC reference manual. 1720 */ 1721static int 1722tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1723{ 1724 int error; 1725 uint32_t time; 1726 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1727 1728 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1729 1730 error = sysctl_handle_int(oidp, &time, 0, req); 1731 if (error != 0) 1732 return (error); 1733 1734 if (time > 65535) 1735 return (EINVAL); 1736 1737 TSEC_IC_LOCK(sc); 1738 if (arg2 == TSEC_IC_RX) { 1739 sc->rx_ic_time = time; 1740 tsec_set_rxic(sc); 1741 } else { 1742 sc->tx_ic_time = time; 1743 tsec_set_txic(sc); 1744 } 1745 TSEC_IC_UNLOCK(sc); 1746 1747 return (0); 1748} 1749 1750static int 1751tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1752{ 1753 int error; 1754 uint32_t count; 1755 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1756 1757 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1758 1759 error = sysctl_handle_int(oidp, &count, 0, req); 1760 if (error != 0) 1761 return (error); 1762 1763 if (count > 255) 1764 return (EINVAL); 1765 1766 TSEC_IC_LOCK(sc); 1767 if (arg2 == TSEC_IC_RX) { 1768 sc->rx_ic_count = count; 1769 tsec_set_rxic(sc); 1770 } else { 1771 sc->tx_ic_count = count; 1772 tsec_set_txic(sc); 1773 } 1774 TSEC_IC_UNLOCK(sc); 1775 1776 return (0); 1777} 1778 1779static void 1780tsec_set_rxic(struct tsec_softc *sc) 1781{ 1782 uint32_t rxic_val; 1783 1784 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1785 /* Disable RX IC */ 1786 rxic_val = 0; 1787 else { 1788 rxic_val = 0x80000000; 1789 rxic_val |= (sc->rx_ic_count << 21); 1790 rxic_val |= sc->rx_ic_time; 1791 } 1792 1793 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1794} 1795 1796static void 1797tsec_set_txic(struct tsec_softc *sc) 1798{ 1799 uint32_t txic_val; 1800 1801 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1802 /* Disable TX IC */ 1803 txic_val = 0; 1804 else { 1805 txic_val = 0x80000000; 1806 txic_val |= (sc->tx_ic_count << 21); 1807 txic_val |= sc->tx_ic_time; 1808 } 1809 1810 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1811} 1812 1813static void 1814tsec_offload_setup(struct tsec_softc *sc) 1815{ 1816 struct ifnet *ifp = sc->tsec_ifp; 1817 uint32_t reg; 1818 1819 TSEC_GLOBAL_LOCK_ASSERT(sc); 1820 1821 reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1822 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1823 1824 if (ifp->if_capenable & IFCAP_TXCSUM) 1825 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1826 else 1827 ifp->if_hwassist = 0; 1828 1829 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1830 1831 reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1832 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1833 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1834 1835 if (ifp->if_capenable & IFCAP_RXCSUM) 1836 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1837 TSEC_RCTRL_PRSDEP_PARSE_L234; 1838 1839 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1840} 1841 1842 1843static void 1844tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1845{ 1846 struct tsec_rx_fcb rx_fcb; 1847 int csum_flags = 0; 1848 int protocol, flags; 1849 1850 TSEC_RECEIVE_LOCK_ASSERT(sc); 1851 1852 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1853 flags = rx_fcb.flags; 1854 protocol = rx_fcb.protocol; 1855 1856 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1857 csum_flags |= CSUM_IP_CHECKED; 1858 1859 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1860 csum_flags |= CSUM_IP_VALID; 1861 } 1862 1863 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1864 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1865 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1866 1867 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1868 m->m_pkthdr.csum_data = 0xFFFF; 1869 } 1870 1871 m->m_pkthdr.csum_flags = csum_flags; 1872 1873 if (flags & TSEC_RX_FCB_VLAN) { 1874 m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1875 m->m_flags |= M_VLANTAG; 1876 } 1877 1878 m_adj(m, sizeof(struct tsec_rx_fcb)); 1879} 1880 1881static void 1882tsec_setup_multicast(struct tsec_softc *sc) 1883{ 1884 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1885 struct ifnet *ifp = sc->tsec_ifp; 1886 struct ifmultiaddr *ifma; 1887 uint32_t h; 1888 int i; 1889 1890 TSEC_GLOBAL_LOCK_ASSERT(sc); 1891 1892 if (ifp->if_flags & IFF_ALLMULTI) { 1893 for (i = 0; i < 8; i++) 1894 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1895 1896 return; 1897 } 1898 1899 IF_ADDR_LOCK(ifp); 1900 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1901 1902 if (ifma->ifma_addr->sa_family != AF_LINK) 1903 continue; 1904 1905 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1906 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1907 1908 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1909 } 1910 IF_ADDR_UNLOCK(ifp); 1911 1912 for (i = 0; i < 8; i++) 1913 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1914} 1915 1916static int 1917tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1918{ 1919 1920 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1921 1922 TSEC_GLOBAL_LOCK_ASSERT(sc); 1923 1924 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1925 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1926 return (mtu); 1927 } 1928 1929 return (0); 1930} 1931