if_tsec.c revision 188718
1/*- 2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27/* 28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29 */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 188718 2009-02-17 15:59:27Z raj $"); 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_device_polling.h" 35#endif 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/mbuf.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47 48#include <net/bpf.h> 49#include <net/ethernet.h> 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in_systm.h> 58#include <netinet/in.h> 59#include <netinet/ip.h> 60 61#include <machine/bus.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/tsec/if_tsec.h> 67#include <dev/tsec/if_tsecreg.h> 68 69static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71 const char *dname); 72static void tsec_dma_ctl(struct tsec_softc *sc, int state); 73static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74 int fcb_inserted); 75static void tsec_free_dma(struct tsec_softc *sc); 76static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77static int tsec_ifmedia_upd(struct ifnet *ifp); 78static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80 struct mbuf **mbufp, uint32_t *paddr); 81static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82 int nseg, int error); 83static void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84static void tsec_init(void *xsc); 85static void tsec_init_locked(struct tsec_softc *sc); 86static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87static void tsec_reset_mac(struct tsec_softc *sc); 88static void tsec_setfilter(struct tsec_softc *sc); 89static void tsec_set_mac_address(struct tsec_softc *sc); 90static void tsec_start(struct ifnet *ifp); 91static void tsec_start_locked(struct ifnet *ifp); 92static void tsec_stop(struct tsec_softc *sc); 93static void tsec_tick(void *arg); 94static void tsec_watchdog(struct tsec_softc *sc); 95static void tsec_add_sysctls(struct tsec_softc *sc); 96static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98static void tsec_set_rxic(struct tsec_softc *sc); 99static void tsec_set_txic(struct tsec_softc *sc); 100static void tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101static void tsec_transmit_intr_locked(struct tsec_softc *sc); 102static void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103static void tsec_offload_setup(struct tsec_softc *sc); 104static void tsec_offload_process_frame(struct tsec_softc *sc, 105 struct mbuf *m); 106static void tsec_setup_multicast(struct tsec_softc *sc); 107static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108 109struct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */ 110 111devclass_t tsec_devclass; 112DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 113MODULE_DEPEND(tsec, ether, 1, 1, 1); 114MODULE_DEPEND(tsec, miibus, 1, 1, 1); 115 116int 117tsec_attach(struct tsec_softc *sc) 118{ 119 uint8_t hwaddr[ETHER_ADDR_LEN]; 120 struct ifnet *ifp; 121 bus_dmamap_t *map_ptr; 122 bus_dmamap_t **map_pptr; 123 int error = 0; 124 int i; 125 126 /* Reset all TSEC counters */ 127 TSEC_TX_RX_COUNTERS_INIT(sc); 128 129 /* Stop DMA engine if enabled by firmware */ 130 tsec_dma_ctl(sc, 0); 131 132 /* Reset MAC */ 133 tsec_reset_mac(sc); 134 135 /* Disable interrupts for now */ 136 tsec_intrs_ctl(sc, 0); 137 138 /* Configure defaults for interrupts coalescing */ 139 sc->rx_ic_time = 768; 140 sc->rx_ic_count = 16; 141 sc->tx_ic_time = 768; 142 sc->tx_ic_count = 16; 143 tsec_set_rxic(sc); 144 tsec_set_txic(sc); 145 tsec_add_sysctls(sc); 146 147 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 148 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 149 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 150 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 151 152 if (error) { 153 tsec_detach(sc); 154 return (ENXIO); 155 } 156 157 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 158 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 159 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 160 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 161 if (error) { 162 tsec_detach(sc); 163 return (ENXIO); 164 } 165 166 /* Allocate a busdma tag for TX mbufs. */ 167 error = bus_dma_tag_create(NULL, /* parent */ 168 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 169 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 170 BUS_SPACE_MAXADDR, /* highaddr */ 171 NULL, NULL, /* filtfunc, filtfuncarg */ 172 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 173 TSEC_TX_NUM_DESC - 1, /* nsegments */ 174 MCLBYTES, 0, /* maxsegsz, flags */ 175 NULL, NULL, /* lockfunc, lockfuncarg */ 176 &sc->tsec_tx_mtag); /* dmat */ 177 if (error) { 178 device_printf(sc->dev, "failed to allocate busdma tag " 179 "(tx mbufs)\n"); 180 tsec_detach(sc); 181 return (ENXIO); 182 } 183 184 /* Allocate a busdma tag for RX mbufs. */ 185 error = bus_dma_tag_create(NULL, /* parent */ 186 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 187 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 188 BUS_SPACE_MAXADDR, /* highaddr */ 189 NULL, NULL, /* filtfunc, filtfuncarg */ 190 MCLBYTES, /* maxsize */ 191 1, /* nsegments */ 192 MCLBYTES, 0, /* maxsegsz, flags */ 193 NULL, NULL, /* lockfunc, lockfuncarg */ 194 &sc->tsec_rx_mtag); /* dmat */ 195 if (error) { 196 device_printf(sc->dev, "failed to allocate busdma tag " 197 "(rx mbufs)\n"); 198 tsec_detach(sc); 199 return (ENXIO); 200 } 201 202 /* Create TX busdma maps */ 203 map_ptr = sc->tx_map_data; 204 map_pptr = sc->tx_map_unused_data; 205 206 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 207 map_pptr[i] = &map_ptr[i]; 208 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 209 if (error) { 210 device_printf(sc->dev, "failed to init TX ring\n"); 211 tsec_detach(sc); 212 return (ENXIO); 213 } 214 } 215 216 /* Create RX busdma maps and zero mbuf handlers */ 217 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 218 error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 219 &sc->rx_data[i].map); 220 if (error) { 221 device_printf(sc->dev, "failed to init RX ring\n"); 222 tsec_detach(sc); 223 return (ENXIO); 224 } 225 sc->rx_data[i].mbuf = NULL; 226 } 227 228 /* Create mbufs for RX buffers */ 229 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 230 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 231 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 232 if (error) { 233 device_printf(sc->dev, "can't load rx DMA map %d, " 234 "error = %d\n", i, error); 235 tsec_detach(sc); 236 return (error); 237 } 238 } 239 240 /* Create network interface for upper layers */ 241 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 242 if (ifp == NULL) { 243 device_printf(sc->dev, "if_alloc() failed\n"); 244 tsec_detach(sc); 245 return (ENOMEM); 246 } 247 248 ifp->if_softc = sc; 249 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 250 ifp->if_mtu = ETHERMTU; 251 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 252 ifp->if_init = tsec_init; 253 ifp->if_start = tsec_start; 254 ifp->if_ioctl = tsec_ioctl; 255 256 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 257 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 258 IFQ_SET_READY(&ifp->if_snd); 259 260 ifp->if_capabilities = IFCAP_VLAN_MTU; 261 if (sc->is_etsec) 262 ifp->if_capabilities |= IFCAP_HWCSUM; 263 264 ifp->if_capenable = ifp->if_capabilities; 265 266#ifdef DEVICE_POLLING 267 /* Advertise that polling is supported */ 268 ifp->if_capabilities |= IFCAP_POLLING; 269#endif 270 271 /* Probe PHY(s) */ 272 error = mii_phy_probe(sc->dev, &sc->tsec_miibus, tsec_ifmedia_upd, 273 tsec_ifmedia_sts); 274 if (error) { 275 device_printf(sc->dev, "MII failed to find PHY!\n"); 276 if_free(ifp); 277 sc->tsec_ifp = NULL; 278 tsec_detach(sc); 279 return (error); 280 } 281 sc->tsec_mii = device_get_softc(sc->tsec_miibus); 282 283 /* Set MAC address */ 284 tsec_get_hwaddr(sc, hwaddr); 285 ether_ifattach(ifp, hwaddr); 286 287 return (0); 288} 289 290int 291tsec_detach(struct tsec_softc *sc) 292{ 293 294#ifdef DEVICE_POLLING 295 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 296 ether_poll_deregister(sc->tsec_ifp); 297#endif 298 299 /* Stop TSEC controller and free TX queue */ 300 if (sc->sc_rres && sc->tsec_ifp) 301 tsec_shutdown(sc->dev); 302 303 /* Detach network interface */ 304 if (sc->tsec_ifp) { 305 ether_ifdetach(sc->tsec_ifp); 306 if_free(sc->tsec_ifp); 307 sc->tsec_ifp = NULL; 308 } 309 310 /* Free DMA resources */ 311 tsec_free_dma(sc); 312 313 return (0); 314} 315 316void 317tsec_shutdown(device_t dev) 318{ 319 struct tsec_softc *sc; 320 321 sc = device_get_softc(dev); 322 323 TSEC_GLOBAL_LOCK(sc); 324 tsec_stop(sc); 325 TSEC_GLOBAL_UNLOCK(sc); 326} 327 328int 329tsec_suspend(device_t dev) 330{ 331 332 /* TODO not implemented! */ 333 return (0); 334} 335 336int 337tsec_resume(device_t dev) 338{ 339 340 /* TODO not implemented! */ 341 return (0); 342} 343 344static void 345tsec_init(void *xsc) 346{ 347 struct tsec_softc *sc = xsc; 348 349 TSEC_GLOBAL_LOCK(sc); 350 tsec_init_locked(sc); 351 TSEC_GLOBAL_UNLOCK(sc); 352} 353 354static void 355tsec_init_locked(struct tsec_softc *sc) 356{ 357 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 358 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 359 struct ifnet *ifp = sc->tsec_ifp; 360 uint32_t timeout, val, i; 361 362 TSEC_GLOBAL_LOCK_ASSERT(sc); 363 tsec_stop(sc); 364 365 /* 366 * These steps are according to the MPC8555E PowerQUICCIII RM: 367 * 14.7 Initialization/Application Information 368 */ 369 370 /* Step 1: soft reset MAC */ 371 tsec_reset_mac(sc); 372 373 /* Step 2: Initialize MACCFG2 */ 374 TSEC_WRITE(sc, TSEC_REG_MACCFG2, 375 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 376 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 377 TSEC_MACCFG2_GMII | /* I/F Mode bit */ 378 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 379 ); 380 381 /* Step 3: Initialize ECNTRL 382 * While the documentation states that R100M is ignored if RPM is 383 * not set, it does seem to be needed to get the orange boxes to 384 * work (which have a Marvell 88E1111 PHY). Go figure. 385 */ 386 387 /* 388 * XXX kludge - use circumstancial evidence to program ECNTRL 389 * correctly. Ideally we need some board information to guide 390 * us here. 391 */ 392 i = TSEC_READ(sc, TSEC_REG_ID2); 393 val = (i & 0xffff) 394 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 395 : TSEC_ECNTRL_R100M; /* Orange + CDS */ 396 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 397 398 /* Step 4: Initialize MAC station address */ 399 tsec_set_mac_address(sc); 400 401 /* 402 * Step 5: Assign a Physical address to the TBI so as to not conflict 403 * with the external PHY physical address 404 */ 405 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 406 407 /* Step 6: Reset the management interface */ 408 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 409 410 /* Step 7: Setup the MII Mgmt clock speed */ 411 TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 412 413 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 414 timeout = TSEC_READ_RETRY; 415 while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) & 416 TSEC_MIIMIND_BUSY)) 417 DELAY(TSEC_READ_DELAY); 418 if (timeout == 0) { 419 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 420 return; 421 } 422 423 /* Step 9: Setup the MII Mgmt */ 424 mii_mediachg(sc->tsec_mii); 425 426 /* Step 10: Clear IEVENT register */ 427 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 428 429 /* Step 11: Enable interrupts */ 430#ifdef DEVICE_POLLING 431 /* 432 * ...only if polling is not turned on. Disable interrupts explicitly 433 * if polling is enabled. 434 */ 435 if (ifp->if_capenable & IFCAP_POLLING ) 436 tsec_intrs_ctl(sc, 0); 437 else 438#endif /* DEVICE_POLLING */ 439 tsec_intrs_ctl(sc, 1); 440 441 /* Step 12: Initialize IADDRn */ 442 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 443 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 444 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 445 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 446 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 447 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 448 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 449 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 450 451 /* Step 13: Initialize GADDRn */ 452 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 453 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 454 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 455 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 456 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 457 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 458 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 459 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 460 461 /* Step 14: Initialize RCTRL */ 462 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 463 464 /* Step 15: Initialize DMACTRL */ 465 tsec_dma_ctl(sc, 1); 466 467 /* Step 16: Initialize FIFO_PAUSE_CTRL */ 468 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 469 470 /* 471 * Step 17: Initialize transmit/receive descriptor rings. 472 * Initialize TBASE and RBASE. 473 */ 474 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 475 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 476 477 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 478 tx_desc[i].bufptr = 0; 479 tx_desc[i].length = 0; 480 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 481 TSEC_TXBD_W : 0); 482 } 483 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 484 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 485 486 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 487 rx_desc[i].bufptr = sc->rx_data[i].paddr; 488 rx_desc[i].length = 0; 489 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 490 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 491 } 492 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 493 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 494 495 /* Step 18: Initialize the maximum receive buffer length */ 496 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 497 498 /* Step 19: Configure ethernet frame sizes */ 499 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 500 tsec_set_mtu(sc, ifp->if_mtu); 501 502 /* Step 20: Enable Rx and RxBD sdata snooping */ 503 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 504 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 505 506 /* Step 21: Reset collision counters in hardware */ 507 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 508 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 509 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 510 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 511 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 512 513 /* Step 22: Mask all CAM interrupts */ 514 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 515 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 516 517 /* Step 23: Enable Rx and Tx */ 518 val = TSEC_READ(sc, TSEC_REG_MACCFG1); 519 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 520 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 521 522 /* Step 24: Reset TSEC counters for Tx and Rx rings */ 523 TSEC_TX_RX_COUNTERS_INIT(sc); 524 525 /* Step 25: Setup TCP/IP Off-Load engine */ 526 if (sc->is_etsec) 527 tsec_offload_setup(sc); 528 529 /* Step 26: Setup multicast filters */ 530 tsec_setup_multicast(sc); 531 532 /* Step 27: Activate network interface */ 533 ifp->if_drv_flags |= IFF_DRV_RUNNING; 534 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 535 sc->tsec_if_flags = ifp->if_flags; 536 sc->tsec_watchdog = 0; 537 538 /* Schedule watchdog timeout */ 539 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 540} 541 542static void 543tsec_set_mac_address(struct tsec_softc *sc) 544{ 545 uint32_t macbuf[2] = { 0, 0 }; 546 char *macbufp, *curmac; 547 int i; 548 549 TSEC_GLOBAL_LOCK_ASSERT(sc); 550 551 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 552 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, 553 sizeof(macbuf))); 554 555 macbufp = (char *)macbuf; 556 curmac = (char *)IF_LLADDR(sc->tsec_ifp); 557 558 /* Correct order of MAC address bytes */ 559 for (i = 1; i <= ETHER_ADDR_LEN; i++) 560 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 561 562 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 563 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 564 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 565} 566 567/* 568 * DMA control function, if argument state is: 569 * 0 - DMA engine will be disabled 570 * 1 - DMA engine will be enabled 571 */ 572static void 573tsec_dma_ctl(struct tsec_softc *sc, int state) 574{ 575 device_t dev; 576 uint32_t dma_flags, timeout; 577 578 dev = sc->dev; 579 580 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 581 582 switch (state) { 583 case 0: 584 /* Temporarily clear stop graceful stop bits. */ 585 tsec_dma_ctl(sc, 1000); 586 587 /* Set it again */ 588 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 589 break; 590 case 1000: 591 case 1: 592 /* Set write with response (WWR), wait (WOP) and snoop bits */ 593 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 594 DMACTRL_WWR | DMACTRL_WOP); 595 596 /* Clear graceful stop bits */ 597 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 598 break; 599 default: 600 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 601 state); 602 } 603 604 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 605 606 switch (state) { 607 case 0: 608 /* Wait for DMA stop */ 609 timeout = TSEC_READ_RETRY; 610 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 611 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 612 DELAY(TSEC_READ_DELAY); 613 614 if (timeout == 0) 615 device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 616 break; 617 case 1: 618 /* Restart transmission function */ 619 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 620 } 621} 622 623/* 624 * Interrupts control function, if argument state is: 625 * 0 - all TSEC interrupts will be masked 626 * 1 - all TSEC interrupts will be unmasked 627 */ 628static void 629tsec_intrs_ctl(struct tsec_softc *sc, int state) 630{ 631 device_t dev; 632 633 dev = sc->dev; 634 635 switch (state) { 636 case 0: 637 TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 638 break; 639 case 1: 640 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 641 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 642 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 643 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 644 break; 645 default: 646 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 647 state); 648 } 649} 650 651static void 652tsec_reset_mac(struct tsec_softc *sc) 653{ 654 uint32_t maccfg1_flags; 655 656 /* Set soft reset bit */ 657 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 658 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 659 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 660 661 /* Clear soft reset bit */ 662 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 663 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 664 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 665} 666 667static void 668tsec_watchdog(struct tsec_softc *sc) 669{ 670 struct ifnet *ifp; 671 672 TSEC_GLOBAL_LOCK_ASSERT(sc); 673 674 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 675 return; 676 677 ifp = sc->tsec_ifp; 678 ifp->if_oerrors++; 679 if_printf(ifp, "watchdog timeout\n"); 680 681 tsec_stop(sc); 682 tsec_init_locked(sc); 683} 684 685static void 686tsec_start(struct ifnet *ifp) 687{ 688 struct tsec_softc *sc = ifp->if_softc; 689 690 TSEC_TRANSMIT_LOCK(sc); 691 tsec_start_locked(ifp); 692 TSEC_TRANSMIT_UNLOCK(sc); 693} 694 695static void 696tsec_start_locked(struct ifnet *ifp) 697{ 698 struct tsec_softc *sc; 699 struct mbuf *m0, *mtmp; 700 struct tsec_tx_fcb *tx_fcb; 701 unsigned int queued = 0; 702 int csum_flags, fcb_inserted = 0; 703 704 sc = ifp->if_softc; 705 706 TSEC_TRANSMIT_LOCK_ASSERT(sc); 707 708 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 709 IFF_DRV_RUNNING) 710 return; 711 712 if (sc->tsec_link == 0) 713 return; 714 715 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 716 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 717 718 for (;;) { 719 /* Get packet from the queue */ 720 IF_DEQUEUE(&ifp->if_snd, m0); 721 if (m0 == NULL) 722 break; 723 724 /* Insert TCP/IP Off-load frame control block */ 725 csum_flags = m0->m_pkthdr.csum_flags; 726 if (csum_flags) { 727 728 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT); 729 if (m0 == NULL) 730 break; 731 732 tx_fcb = mtod(m0, struct tsec_tx_fcb *); 733 tx_fcb->flags = 0; 734 tx_fcb->l3_offset = ETHER_HDR_LEN; 735 tx_fcb->l4_offset = sizeof(struct ip); 736 737 if (csum_flags & CSUM_IP) 738 tx_fcb->flags |= TSEC_TX_FCB_IP4 | 739 TSEC_TX_FCB_CSUM_IP; 740 741 if (csum_flags & CSUM_TCP) 742 tx_fcb->flags |= TSEC_TX_FCB_TCP | 743 TSEC_TX_FCB_CSUM_TCP_UDP; 744 745 if (csum_flags & CSUM_UDP) 746 tx_fcb->flags |= TSEC_TX_FCB_UDP | 747 TSEC_TX_FCB_CSUM_TCP_UDP; 748 749 fcb_inserted = 1; 750 } 751 752 mtmp = m_defrag(m0, M_DONTWAIT); 753 if (mtmp) 754 m0 = mtmp; 755 756 if (tsec_encap(sc, m0, fcb_inserted)) { 757 IF_PREPEND(&ifp->if_snd, m0); 758 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 759 break; 760 } 761 queued++; 762 BPF_MTAP(ifp, m0); 763 } 764 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 765 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 766 767 if (queued) { 768 /* Enable transmitter and watchdog timer */ 769 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 770 sc->tsec_watchdog = 5; 771 } 772} 773 774static int 775tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 776{ 777 struct tsec_desc *tx_desc = NULL; 778 struct ifnet *ifp; 779 bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 780 bus_dmamap_t *mapp; 781 int csum_flag = 0, error, seg, nsegs; 782 783 TSEC_TRANSMIT_LOCK_ASSERT(sc); 784 785 ifp = sc->tsec_ifp; 786 787 if (TSEC_FREE_TX_DESC(sc) == 0) { 788 /* No free descriptors */ 789 return (-1); 790 } 791 792 /* Fetch unused map */ 793 mapp = TSEC_ALLOC_TX_MAP(sc); 794 795 /* Create mapping in DMA memory */ 796 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 797 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 798 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 799 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 800 TSEC_FREE_TX_MAP(sc, mapp); 801 return ((error != 0) ? error : -1); 802 } 803 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 804 805 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 806 if_printf(ifp, "TX buffer has %d segments\n", nsegs); 807 808 if (fcb_inserted) 809 csum_flag = TSEC_TXBD_TOE; 810 811 /* Everything is ok, now we can send buffers */ 812 for (seg = 0; seg < nsegs; seg++) { 813 tx_desc = TSEC_GET_CUR_TX_DESC(sc); 814 815 tx_desc->length = segs[seg].ds_len; 816 tx_desc->bufptr = segs[seg].ds_addr; 817 818 /* 819 * Set flags: 820 * - wrap 821 * - checksum 822 * - ready to send 823 * - transmit the CRC sequence after the last data byte 824 * - interrupt after the last buffer 825 */ 826 tx_desc->flags = 827 (tx_desc->flags & TSEC_TXBD_W) | 828 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 829 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 830 } 831 832 /* Save mbuf and DMA mapping for release at later stage */ 833 TSEC_PUT_TX_MBUF(sc, m0); 834 TSEC_PUT_TX_MAP(sc, mapp); 835 836 return (0); 837} 838 839static void 840tsec_setfilter(struct tsec_softc *sc) 841{ 842 struct ifnet *ifp; 843 uint32_t flags; 844 845 ifp = sc->tsec_ifp; 846 flags = TSEC_READ(sc, TSEC_REG_RCTRL); 847 848 /* Promiscuous mode */ 849 if (ifp->if_flags & IFF_PROMISC) 850 flags |= TSEC_RCTRL_PROM; 851 else 852 flags &= ~TSEC_RCTRL_PROM; 853 854 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 855} 856 857#ifdef DEVICE_POLLING 858static poll_handler_t tsec_poll; 859 860static void 861tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 862{ 863 uint32_t ie; 864 struct tsec_softc *sc = ifp->if_softc; 865 866 TSEC_GLOBAL_LOCK(sc); 867 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 868 TSEC_GLOBAL_UNLOCK(sc); 869 return; 870 } 871 872 if (cmd == POLL_AND_CHECK_STATUS) { 873 tsec_error_intr_locked(sc, count); 874 875 /* Clear all events reported */ 876 ie = TSEC_READ(sc, TSEC_REG_IEVENT); 877 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 878 } 879 880 tsec_transmit_intr_locked(sc); 881 882 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 883 884 tsec_receive_intr_locked(sc, count); 885 886 TSEC_RECEIVE_UNLOCK(sc); 887} 888#endif /* DEVICE_POLLING */ 889 890static int 891tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 892{ 893 struct tsec_softc *sc = ifp->if_softc; 894 struct ifreq *ifr = (struct ifreq *)data; 895 device_t dev; 896 int mask, error = 0; 897 898 dev = sc->dev; 899 900 switch (command) { 901 case SIOCSIFMTU: 902 TSEC_GLOBAL_LOCK(sc); 903 if (tsec_set_mtu(sc, ifr->ifr_mtu)) 904 ifp->if_mtu = ifr->ifr_mtu; 905 else 906 error = EINVAL; 907 TSEC_GLOBAL_UNLOCK(sc); 908 break; 909 case SIOCSIFFLAGS: 910 TSEC_GLOBAL_LOCK(sc); 911 if (ifp->if_flags & IFF_UP) { 912 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 913 if ((sc->tsec_if_flags ^ ifp->if_flags) & 914 IFF_PROMISC) 915 tsec_setfilter(sc); 916 917 if ((sc->tsec_if_flags ^ ifp->if_flags) & 918 IFF_ALLMULTI) 919 tsec_setup_multicast(sc); 920 } else 921 tsec_init_locked(sc); 922 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 923 tsec_stop(sc); 924 925 sc->tsec_if_flags = ifp->if_flags; 926 TSEC_GLOBAL_UNLOCK(sc); 927 break; 928 case SIOCADDMULTI: 929 case SIOCDELMULTI: 930 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 931 TSEC_GLOBAL_LOCK(sc); 932 tsec_setup_multicast(sc); 933 TSEC_GLOBAL_UNLOCK(sc); 934 } 935 case SIOCGIFMEDIA: 936 case SIOCSIFMEDIA: 937 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 938 command); 939 break; 940 case SIOCSIFCAP: 941 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 942 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 943 TSEC_GLOBAL_LOCK(sc); 944 ifp->if_capenable &= ~IFCAP_HWCSUM; 945 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 946 tsec_offload_setup(sc); 947 TSEC_GLOBAL_UNLOCK(sc); 948 } 949#ifdef DEVICE_POLLING 950 if (mask & IFCAP_POLLING) { 951 if (ifr->ifr_reqcap & IFCAP_POLLING) { 952 error = ether_poll_register(tsec_poll, ifp); 953 if (error) 954 return (error); 955 956 TSEC_GLOBAL_LOCK(sc); 957 /* Disable interrupts */ 958 tsec_intrs_ctl(sc, 0); 959 ifp->if_capenable |= IFCAP_POLLING; 960 TSEC_GLOBAL_UNLOCK(sc); 961 } else { 962 error = ether_poll_deregister(ifp); 963 TSEC_GLOBAL_LOCK(sc); 964 /* Enable interrupts */ 965 tsec_intrs_ctl(sc, 1); 966 ifp->if_capenable &= ~IFCAP_POLLING; 967 TSEC_GLOBAL_UNLOCK(sc); 968 } 969 } 970#endif 971 break; 972 973 default: 974 error = ether_ioctl(ifp, command, data); 975 } 976 977 /* Flush buffers if not empty */ 978 if (ifp->if_flags & IFF_UP) 979 tsec_start(ifp); 980 return (error); 981} 982 983static int 984tsec_ifmedia_upd(struct ifnet *ifp) 985{ 986 struct tsec_softc *sc = ifp->if_softc; 987 struct mii_data *mii; 988 989 TSEC_TRANSMIT_LOCK(sc); 990 991 mii = sc->tsec_mii; 992 mii_mediachg(mii); 993 994 TSEC_TRANSMIT_UNLOCK(sc); 995 return (0); 996} 997 998static void 999tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1000{ 1001 struct tsec_softc *sc = ifp->if_softc; 1002 struct mii_data *mii; 1003 1004 TSEC_TRANSMIT_LOCK(sc); 1005 1006 mii = sc->tsec_mii; 1007 mii_pollstat(mii); 1008 1009 ifmr->ifm_active = mii->mii_media_active; 1010 ifmr->ifm_status = mii->mii_media_status; 1011 1012 TSEC_TRANSMIT_UNLOCK(sc); 1013} 1014 1015static int 1016tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1017 uint32_t *paddr) 1018{ 1019 struct mbuf *new_mbuf; 1020 bus_dma_segment_t seg[1]; 1021 int error, nsegs; 1022 1023 KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1024 1025 new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1026 if (new_mbuf == NULL) 1027 return (ENOBUFS); 1028 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1029 1030 if (*mbufp) { 1031 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1032 bus_dmamap_unload(tag, map); 1033 } 1034 1035 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1036 BUS_DMA_NOWAIT); 1037 KASSERT(nsegs == 1, ("Too many segments returned!")); 1038 if (nsegs != 1 || error) 1039 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1040 1041#if 0 1042 if (error) { 1043 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1044 error); 1045 m_freem(new_mbuf); 1046 return (ENOBUFS); 1047 } 1048#endif 1049 1050#if 0 1051 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1052 ("Wrong alignment of RX buffer!")); 1053#endif 1054 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1055 1056 (*mbufp) = new_mbuf; 1057 (*paddr) = seg->ds_addr; 1058 return (0); 1059} 1060 1061static void 1062tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1063{ 1064 u_int32_t *paddr; 1065 1066 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1067 paddr = arg; 1068 *paddr = segs->ds_addr; 1069} 1070 1071static int 1072tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1073 bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1074{ 1075 int error; 1076 1077 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1078 error = bus_dma_tag_create(NULL, /* parent */ 1079 PAGE_SIZE, 0, /* alignment, boundary */ 1080 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1081 BUS_SPACE_MAXADDR, /* highaddr */ 1082 NULL, NULL, /* filtfunc, filtfuncarg */ 1083 dsize, 1, /* maxsize, nsegments */ 1084 dsize, 0, /* maxsegsz, flags */ 1085 NULL, NULL, /* lockfunc, lockfuncarg */ 1086 dtag); /* dmat */ 1087 1088 if (error) { 1089 device_printf(dev, "failed to allocate busdma %s tag\n", 1090 dname); 1091 (*vaddr) = NULL; 1092 return (ENXIO); 1093 } 1094 1095 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1096 dmap); 1097 if (error) { 1098 device_printf(dev, "failed to allocate %s DMA safe memory\n", 1099 dname); 1100 bus_dma_tag_destroy(*dtag); 1101 (*vaddr) = NULL; 1102 return (ENXIO); 1103 } 1104 1105 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1106 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1107 if (error) { 1108 device_printf(dev, "cannot get address of the %s " 1109 "descriptors\n", dname); 1110 bus_dmamem_free(*dtag, *vaddr, *dmap); 1111 bus_dma_tag_destroy(*dtag); 1112 (*vaddr) = NULL; 1113 return (ENXIO); 1114 } 1115 1116 return (0); 1117} 1118 1119static void 1120tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1121{ 1122 1123 if (vaddr == NULL) 1124 return; 1125 1126 /* Unmap descriptors from DMA memory */ 1127 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1128 BUS_DMASYNC_POSTWRITE); 1129 bus_dmamap_unload(dtag, dmap); 1130 1131 /* Free descriptors memory */ 1132 bus_dmamem_free(dtag, vaddr, dmap); 1133 1134 /* Destroy descriptors tag */ 1135 bus_dma_tag_destroy(dtag); 1136} 1137 1138static void 1139tsec_free_dma(struct tsec_softc *sc) 1140{ 1141 int i; 1142 1143 /* Free TX maps */ 1144 for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1145 if (sc->tx_map_data[i] != NULL) 1146 bus_dmamap_destroy(sc->tsec_tx_mtag, 1147 sc->tx_map_data[i]); 1148 /* Destroy tag for TX mbufs */ 1149 bus_dma_tag_destroy(sc->tsec_tx_mtag); 1150 1151 /* Free RX mbufs and maps */ 1152 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1153 if (sc->rx_data[i].mbuf) { 1154 /* Unload buffer from DMA */ 1155 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1156 BUS_DMASYNC_POSTREAD); 1157 bus_dmamap_unload(sc->tsec_rx_mtag, 1158 sc->rx_data[i].map); 1159 1160 /* Free buffer */ 1161 m_freem(sc->rx_data[i].mbuf); 1162 } 1163 /* Destroy map for this buffer */ 1164 if (sc->rx_data[i].map != NULL) 1165 bus_dmamap_destroy(sc->tsec_rx_mtag, 1166 sc->rx_data[i].map); 1167 } 1168 /* Destroy tag for RX mbufs */ 1169 bus_dma_tag_destroy(sc->tsec_rx_mtag); 1170 1171 /* Unload TX/RX descriptors */ 1172 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1173 sc->tsec_tx_vaddr); 1174 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1175 sc->tsec_rx_vaddr); 1176} 1177 1178static void 1179tsec_stop(struct tsec_softc *sc) 1180{ 1181 struct ifnet *ifp; 1182 struct mbuf *m0; 1183 bus_dmamap_t *mapp; 1184 uint32_t tmpval; 1185 1186 TSEC_GLOBAL_LOCK_ASSERT(sc); 1187 1188 ifp = sc->tsec_ifp; 1189 1190 /* Disable interface and watchdog timer */ 1191 callout_stop(&sc->tsec_callout); 1192 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1193 sc->tsec_watchdog = 0; 1194 1195 /* Disable all interrupts and stop DMA */ 1196 tsec_intrs_ctl(sc, 0); 1197 tsec_dma_ctl(sc, 0); 1198 1199 /* Remove pending data from TX queue */ 1200 while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1201 m0 = TSEC_GET_TX_MBUF(sc); 1202 mapp = TSEC_GET_TX_MAP(sc); 1203 1204 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1205 BUS_DMASYNC_POSTWRITE); 1206 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1207 1208 TSEC_FREE_TX_MAP(sc, mapp); 1209 m_freem(m0); 1210 } 1211 1212 /* Disable RX and TX */ 1213 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1214 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1215 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1216 DELAY(10); 1217} 1218 1219static void 1220tsec_tick(void *arg) 1221{ 1222 struct tsec_softc *sc = arg; 1223 struct ifnet *ifp; 1224 int link; 1225 1226 TSEC_GLOBAL_LOCK(sc); 1227 1228 tsec_watchdog(sc); 1229 1230 ifp = sc->tsec_ifp; 1231 link = sc->tsec_link; 1232 1233 mii_tick(sc->tsec_mii); 1234 1235 if (link == 0 && sc->tsec_link == 1 && 1236 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1237 tsec_start_locked(ifp); 1238 1239 /* Schedule another timeout one second from now. */ 1240 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1241 1242 TSEC_GLOBAL_UNLOCK(sc); 1243} 1244 1245/* 1246 * This is the core RX routine. It replenishes mbufs in the descriptor and 1247 * sends data which have been dma'ed into host memory to upper layer. 1248 * 1249 * Loops at most count times if count is > 0, or until done if count < 0. 1250 */ 1251static void 1252tsec_receive_intr_locked(struct tsec_softc *sc, int count) 1253{ 1254 struct tsec_desc *rx_desc; 1255 struct ifnet *ifp; 1256 struct rx_data_type *rx_data; 1257 struct mbuf *m; 1258 device_t dev; 1259 uint32_t i; 1260 int c; 1261 uint16_t flags; 1262 1263 TSEC_RECEIVE_LOCK_ASSERT(sc); 1264 1265 ifp = sc->tsec_ifp; 1266 rx_data = sc->rx_data; 1267 dev = sc->dev; 1268 1269 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1270 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1271 1272 for (c = 0; ; c++) { 1273 if (count >= 0 && count-- == 0) 1274 break; 1275 1276 rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1277 flags = rx_desc->flags; 1278 1279 /* Check if there is anything to receive */ 1280 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1281 /* 1282 * Avoid generating another interrupt 1283 */ 1284 if (flags & TSEC_RXBD_E) 1285 TSEC_WRITE(sc, TSEC_REG_IEVENT, 1286 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1287 /* 1288 * We didn't consume current descriptor and have to 1289 * return it to the queue 1290 */ 1291 TSEC_BACK_CUR_RX_DESC(sc); 1292 break; 1293 } 1294 1295 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1296 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1297 1298 rx_desc->length = 0; 1299 rx_desc->flags = (rx_desc->flags & 1300 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1301 1302 if (sc->frame != NULL) { 1303 m_free(sc->frame); 1304 sc->frame = NULL; 1305 } 1306 1307 continue; 1308 } 1309 1310 /* Ok... process frame */ 1311 i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1312 m = rx_data[i].mbuf; 1313 m->m_len = rx_desc->length; 1314 1315 if (sc->frame != NULL) { 1316 if ((flags & TSEC_RXBD_L) != 0) 1317 m->m_len -= m_length(sc->frame, NULL); 1318 1319 m->m_flags &= ~M_PKTHDR; 1320 m_cat(sc->frame, m); 1321 } else { 1322 sc->frame = m; 1323 } 1324 1325 m = NULL; 1326 1327 if ((flags & TSEC_RXBD_L) != 0) { 1328 m = sc->frame; 1329 sc->frame = NULL; 1330 } 1331 1332 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1333 &rx_data[i].mbuf, &rx_data[i].paddr)) { 1334 ifp->if_ierrors++; 1335 /* 1336 * We ran out of mbufs; didn't consume current 1337 * descriptor and have to return it to the queue. 1338 */ 1339 TSEC_BACK_CUR_RX_DESC(sc); 1340 break; 1341 } 1342 1343 /* Attach new buffer to descriptor and clear flags */ 1344 rx_desc->bufptr = rx_data[i].paddr; 1345 rx_desc->length = 0; 1346 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1347 TSEC_RXBD_E | TSEC_RXBD_I; 1348 1349 if (m != NULL) { 1350 m->m_pkthdr.rcvif = ifp; 1351 1352 m_fixhdr(m); 1353 m_adj(m, -ETHER_CRC_LEN); 1354 1355 if (sc->is_etsec) 1356 tsec_offload_process_frame(sc, m); 1357 1358 TSEC_RECEIVE_UNLOCK(sc); 1359 (*ifp->if_input)(ifp, m); 1360 TSEC_RECEIVE_LOCK(sc); 1361 } 1362 } 1363 1364 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1365 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1366 1367 /* 1368 * Make sure TSEC receiver is not halted. 1369 * 1370 * Various conditions can stop the TSEC receiver, but not all are 1371 * signaled and handled by error interrupt, so make sure the receiver 1372 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1373 * halted, and is harmless if already running. 1374 */ 1375 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1376} 1377 1378void 1379tsec_receive_intr(void *arg) 1380{ 1381 struct tsec_softc *sc = arg; 1382 1383 TSEC_RECEIVE_LOCK(sc); 1384 1385#ifdef DEVICE_POLLING 1386 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1387 TSEC_RECEIVE_UNLOCK(sc); 1388 return; 1389 } 1390#endif 1391 1392 /* Confirm the interrupt was received by driver */ 1393 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1394 tsec_receive_intr_locked(sc, -1); 1395 1396 TSEC_RECEIVE_UNLOCK(sc); 1397} 1398 1399static void 1400tsec_transmit_intr_locked(struct tsec_softc *sc) 1401{ 1402 struct tsec_desc *tx_desc; 1403 struct ifnet *ifp; 1404 struct mbuf *m0; 1405 bus_dmamap_t *mapp; 1406 int send = 0; 1407 1408 TSEC_TRANSMIT_LOCK_ASSERT(sc); 1409 1410 ifp = sc->tsec_ifp; 1411 1412 /* Update collision statistics */ 1413 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1414 1415 /* Reset collision counters in hardware */ 1416 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1417 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1418 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1419 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1420 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1421 1422 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1423 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1424 1425 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1426 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1427 if (tx_desc->flags & TSEC_TXBD_R) { 1428 TSEC_BACK_DIRTY_TX_DESC(sc); 1429 break; 1430 } 1431 1432 if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1433 continue; 1434 1435 /* 1436 * This is the last buf in this packet, so unmap and free it. 1437 */ 1438 m0 = TSEC_GET_TX_MBUF(sc); 1439 mapp = TSEC_GET_TX_MAP(sc); 1440 1441 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1442 BUS_DMASYNC_POSTWRITE); 1443 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1444 1445 TSEC_FREE_TX_MAP(sc, mapp); 1446 m_freem(m0); 1447 1448 ifp->if_opackets++; 1449 send = 1; 1450 } 1451 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1452 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1453 1454 if (send) { 1455 /* Now send anything that was pending */ 1456 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1457 tsec_start_locked(ifp); 1458 1459 /* Stop wathdog if all sent */ 1460 if (TSEC_EMPTYQ_TX_MBUF(sc)) 1461 sc->tsec_watchdog = 0; 1462 } 1463} 1464 1465void 1466tsec_transmit_intr(void *arg) 1467{ 1468 struct tsec_softc *sc = arg; 1469 1470 TSEC_TRANSMIT_LOCK(sc); 1471 1472#ifdef DEVICE_POLLING 1473 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1474 TSEC_TRANSMIT_UNLOCK(sc); 1475 return; 1476 } 1477#endif 1478 /* Confirm the interrupt was received by driver */ 1479 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1480 tsec_transmit_intr_locked(sc); 1481 1482 TSEC_TRANSMIT_UNLOCK(sc); 1483} 1484 1485static void 1486tsec_error_intr_locked(struct tsec_softc *sc, int count) 1487{ 1488 struct ifnet *ifp; 1489 uint32_t eflags; 1490 1491 TSEC_GLOBAL_LOCK_ASSERT(sc); 1492 1493 ifp = sc->tsec_ifp; 1494 1495 eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1496 1497 /* Clear events bits in hardware */ 1498 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1499 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1500 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1501 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1502 1503 /* Check transmitter errors */ 1504 if (eflags & TSEC_IEVENT_TXE) { 1505 ifp->if_oerrors++; 1506 1507 if (eflags & TSEC_IEVENT_LC) 1508 ifp->if_collisions++; 1509 1510 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1511 } 1512 1513 /* Check receiver errors */ 1514 if (eflags & TSEC_IEVENT_BSY) { 1515 ifp->if_ierrors++; 1516 ifp->if_iqdrops++; 1517 1518 /* Get data from RX buffers */ 1519 tsec_receive_intr_locked(sc, count); 1520 } 1521 1522 if (ifp->if_flags & IFF_DEBUG) 1523 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1524 eflags); 1525 1526 if (eflags & TSEC_IEVENT_EBERR) { 1527 if_printf(ifp, "System bus error occurred during" 1528 "DMA transaction (flags: 0x%x)\n", eflags); 1529 tsec_init_locked(sc); 1530 } 1531 1532 if (eflags & TSEC_IEVENT_BABT) 1533 ifp->if_oerrors++; 1534 1535 if (eflags & TSEC_IEVENT_BABR) 1536 ifp->if_ierrors++; 1537} 1538 1539void 1540tsec_error_intr(void *arg) 1541{ 1542 struct tsec_softc *sc = arg; 1543 1544 TSEC_GLOBAL_LOCK(sc); 1545 tsec_error_intr_locked(sc, -1); 1546 TSEC_GLOBAL_UNLOCK(sc); 1547} 1548 1549int 1550tsec_miibus_readreg(device_t dev, int phy, int reg) 1551{ 1552 struct tsec_softc *sc; 1553 uint32_t timeout; 1554 1555 sc = device_get_softc(dev); 1556 1557 if (device_get_unit(dev) != phy) 1558 return (0); 1559 1560 sc = tsec0_sc; 1561 1562 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1563 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1564 TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1565 1566 timeout = TSEC_READ_RETRY; 1567 while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) & 1568 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1569 DELAY(TSEC_READ_DELAY); 1570 1571 if (timeout == 0) 1572 device_printf(dev, "Timeout while reading from PHY!\n"); 1573 1574 return (TSEC_READ(sc, TSEC_REG_MIIMSTAT)); 1575} 1576 1577void 1578tsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1579{ 1580 struct tsec_softc *sc; 1581 uint32_t timeout; 1582 1583 sc = device_get_softc(dev); 1584 1585 if (device_get_unit(dev) != phy) 1586 device_printf(dev, "Trying to write to an alien PHY(%d)\n", 1587 phy); 1588 1589 sc = tsec0_sc; 1590 1591 TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1592 TSEC_WRITE(sc, TSEC_REG_MIIMCON, value); 1593 1594 timeout = TSEC_READ_RETRY; 1595 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & 1596 TSEC_MIIMIND_BUSY)) 1597 DELAY(TSEC_READ_DELAY); 1598 1599 if (timeout == 0) 1600 device_printf(dev, "Timeout while writing to PHY!\n"); 1601} 1602 1603void 1604tsec_miibus_statchg(device_t dev) 1605{ 1606 struct tsec_softc *sc; 1607 struct mii_data *mii; 1608 uint32_t ecntrl, id, tmp; 1609 int link; 1610 1611 sc = device_get_softc(dev); 1612 mii = sc->tsec_mii; 1613 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1614 1615 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1616 1617 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1618 tmp |= TSEC_MACCFG2_FULLDUPLEX; 1619 else 1620 tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1621 1622 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1623 case IFM_1000_T: 1624 case IFM_1000_SX: 1625 tmp |= TSEC_MACCFG2_GMII; 1626 sc->tsec_link = link; 1627 break; 1628 case IFM_100_TX: 1629 case IFM_10_T: 1630 tmp |= TSEC_MACCFG2_MII; 1631 sc->tsec_link = link; 1632 break; 1633 case IFM_NONE: 1634 if (link) 1635 device_printf(dev, "No speed selected but link " 1636 "active!\n"); 1637 sc->tsec_link = 0; 1638 return; 1639 default: 1640 sc->tsec_link = 0; 1641 device_printf(dev, "Unknown speed (%d), link %s!\n", 1642 IFM_SUBTYPE(mii->mii_media_active), 1643 ((link) ? "up" : "down")); 1644 return; 1645 } 1646 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1647 1648 /* XXX kludge - use circumstantial evidence for reduced mode. */ 1649 id = TSEC_READ(sc, TSEC_REG_ID2); 1650 if (id & 0xffff) { 1651 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1652 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1653 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1654 } 1655} 1656 1657static void 1658tsec_add_sysctls(struct tsec_softc *sc) 1659{ 1660 struct sysctl_ctx_list *ctx; 1661 struct sysctl_oid_list *children; 1662 struct sysctl_oid *tree; 1663 1664 ctx = device_get_sysctl_ctx(sc->dev); 1665 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1666 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1667 CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1668 children = SYSCTL_CHILDREN(tree); 1669 1670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1671 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1672 "I", "IC RX time threshold (0-65535)"); 1673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1674 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1675 "I", "IC RX frame count threshold (0-255)"); 1676 1677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1678 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1679 "I", "IC TX time threshold (0-65535)"); 1680 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1681 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1682 "I", "IC TX frame count threshold (0-255)"); 1683} 1684 1685/* 1686 * With Interrupt Coalescing (IC) active, a transmit/receive frame 1687 * interrupt is raised either upon: 1688 * 1689 * - threshold-defined period of time elapsed, or 1690 * - threshold-defined number of frames is received/transmitted, 1691 * whichever occurs first. 1692 * 1693 * The following sysctls regulate IC behaviour (for TX/RX separately): 1694 * 1695 * dev.tsec.<unit>.int_coal.rx_time 1696 * dev.tsec.<unit>.int_coal.rx_count 1697 * dev.tsec.<unit>.int_coal.tx_time 1698 * dev.tsec.<unit>.int_coal.tx_count 1699 * 1700 * Values: 1701 * 1702 * - 0 for either time or count disables IC on the given TX/RX path 1703 * 1704 * - count: 1-255 (expresses frame count number; note that value of 1 is 1705 * effectively IC off) 1706 * 1707 * - time: 1-65535 (value corresponds to a real time period and is 1708 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1709 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1710 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1711 * TSEC reference manual. 1712 */ 1713 1714static int 1715tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1716{ 1717 int error; 1718 uint32_t time; 1719 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1720 1721 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1722 1723 error = sysctl_handle_int(oidp, &time, 0, req); 1724 if (error != 0) 1725 return (error); 1726 1727 if (time > 65535) 1728 return (EINVAL); 1729 1730 TSEC_IC_LOCK(sc); 1731 if (arg2 == TSEC_IC_RX) { 1732 sc->rx_ic_time = time; 1733 tsec_set_rxic(sc); 1734 } else { 1735 sc->tx_ic_time = time; 1736 tsec_set_txic(sc); 1737 } 1738 TSEC_IC_UNLOCK(sc); 1739 1740 return (0); 1741} 1742 1743static int 1744tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1745{ 1746 int error; 1747 uint32_t count; 1748 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1749 1750 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1751 1752 error = sysctl_handle_int(oidp, &count, 0, req); 1753 if (error != 0) 1754 return (error); 1755 1756 if (count > 255) 1757 return (EINVAL); 1758 1759 TSEC_IC_LOCK(sc); 1760 if (arg2 == TSEC_IC_RX) { 1761 sc->rx_ic_count = count; 1762 tsec_set_rxic(sc); 1763 } else { 1764 sc->tx_ic_count = count; 1765 tsec_set_txic(sc); 1766 } 1767 TSEC_IC_UNLOCK(sc); 1768 1769 return (0); 1770} 1771 1772static void 1773tsec_set_rxic(struct tsec_softc *sc) 1774{ 1775 uint32_t rxic_val; 1776 1777 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1778 /* Disable RX IC */ 1779 rxic_val = 0; 1780 else { 1781 rxic_val = 0x80000000; 1782 rxic_val |= (sc->rx_ic_count << 21); 1783 rxic_val |= sc->rx_ic_time; 1784 } 1785 1786 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1787} 1788 1789static void 1790tsec_set_txic(struct tsec_softc *sc) 1791{ 1792 uint32_t txic_val; 1793 1794 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1795 /* Disable TX IC */ 1796 txic_val = 0; 1797 else { 1798 txic_val = 0x80000000; 1799 txic_val |= (sc->tx_ic_count << 21); 1800 txic_val |= sc->tx_ic_time; 1801 } 1802 1803 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1804} 1805 1806static void 1807tsec_offload_setup(struct tsec_softc *sc) 1808{ 1809 struct ifnet *ifp = sc->tsec_ifp; 1810 uint32_t reg; 1811 1812 TSEC_GLOBAL_LOCK_ASSERT(sc); 1813 1814 reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1815 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1816 1817 if (ifp->if_capenable & IFCAP_TXCSUM) 1818 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1819 else 1820 ifp->if_hwassist = 0; 1821 1822 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1823 1824 reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1825 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1826 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1827 1828 if (ifp->if_capenable & IFCAP_RXCSUM) 1829 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1830 TSEC_RCTRL_PRSDEP_PARSE_L234; 1831 1832 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1833} 1834 1835 1836static void 1837tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1838{ 1839 struct tsec_rx_fcb rx_fcb; 1840 int csum_flags = 0; 1841 int protocol, flags; 1842 1843 TSEC_RECEIVE_LOCK_ASSERT(sc); 1844 1845 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1846 flags = rx_fcb.flags; 1847 protocol = rx_fcb.protocol; 1848 1849 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1850 csum_flags |= CSUM_IP_CHECKED; 1851 1852 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1853 csum_flags |= CSUM_IP_VALID; 1854 } 1855 1856 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1857 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1858 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1859 1860 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1861 m->m_pkthdr.csum_data = 0xFFFF; 1862 } 1863 1864 m->m_pkthdr.csum_flags = csum_flags; 1865 1866 if (flags & TSEC_RX_FCB_VLAN) { 1867 m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1868 m->m_flags |= M_VLANTAG; 1869 } 1870 1871 m_adj(m, sizeof(struct tsec_rx_fcb)); 1872} 1873 1874static void 1875tsec_setup_multicast(struct tsec_softc *sc) 1876{ 1877 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1878 struct ifnet *ifp = sc->tsec_ifp; 1879 struct ifmultiaddr *ifma; 1880 uint32_t h; 1881 int i; 1882 1883 TSEC_GLOBAL_LOCK_ASSERT(sc); 1884 1885 if (ifp->if_flags & IFF_ALLMULTI) { 1886 for (i = 0; i < 8; i++) 1887 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1888 1889 return; 1890 } 1891 1892 IF_ADDR_LOCK(ifp); 1893 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1894 1895 if (ifma->ifma_addr->sa_family != AF_LINK) 1896 continue; 1897 1898 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1899 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1900 1901 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1902 } 1903 IF_ADDR_UNLOCK(ifp); 1904 1905 for (i = 0; i < 8; i++) 1906 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1907} 1908 1909static int 1910tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1911{ 1912 1913 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1914 1915 TSEC_GLOBAL_LOCK_ASSERT(sc); 1916 1917 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1918 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1919 return (mtu); 1920 } 1921 1922 return (0); 1923} 1924