if_tsec.c revision 188715
1176774Sraj/*- 2182189Sraj * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3182189Sraj * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com> 4176774Sraj * All rights reserved. 5176774Sraj * 6176774Sraj * Redistribution and use in source and binary forms, with or without 7176774Sraj * modification, are permitted provided that the following conditions 8176774Sraj * are met: 9176774Sraj * 1. Redistributions of source code must retain the above copyright 10176774Sraj * notice, this list of conditions and the following disclaimer. 11176774Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176774Sraj * notice, this list of conditions and the following disclaimer in the 13176774Sraj * documentation and/or other materials provided with the distribution. 14176774Sraj * 15176774Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176774Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176774Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176774Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176774Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176774Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176774Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176774Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176774Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176774Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176774Sraj */ 26176774Sraj 27176774Sraj/* 28176774Sraj * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29176774Sraj */ 30176774Sraj#include <sys/cdefs.h> 31176774Sraj__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 188715 2009-02-17 15:47:13Z raj $"); 32176774Sraj 33188711Sraj#ifdef HAVE_KERNEL_OPTION_HEADERS 34188711Sraj#include "opt_device_polling.h" 35188711Sraj#endif 36188711Sraj 37176774Sraj#include <sys/param.h> 38176774Sraj#include <sys/systm.h> 39182189Sraj#include <sys/bus.h> 40176774Sraj#include <sys/endian.h> 41176774Sraj#include <sys/mbuf.h> 42176774Sraj#include <sys/kernel.h> 43176774Sraj#include <sys/module.h> 44176774Sraj#include <sys/socket.h> 45182189Sraj#include <sys/sockio.h> 46176774Sraj#include <sys/sysctl.h> 47176774Sraj 48182189Sraj#include <net/bpf.h> 49182189Sraj#include <net/ethernet.h> 50176774Sraj#include <net/if.h> 51182189Sraj#include <net/if_arp.h> 52176774Sraj#include <net/if_dl.h> 53176774Sraj#include <net/if_media.h> 54182189Sraj#include <net/if_types.h> 55182189Sraj#include <net/if_vlan_var.h> 56176774Sraj 57188711Sraj#include <netinet/in_systm.h> 58188711Sraj#include <netinet/in.h> 59188711Sraj#include <netinet/ip.h> 60188711Sraj 61176774Sraj#include <machine/bus.h> 62176774Sraj 63176774Sraj#include <dev/mii/mii.h> 64176774Sraj#include <dev/mii/miivar.h> 65176774Sraj 66176774Sraj#include <dev/tsec/if_tsec.h> 67176774Sraj#include <dev/tsec/if_tsecreg.h> 68176774Sraj 69182189Srajstatic int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70182189Sraj bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71182189Sraj const char *dname); 72182189Srajstatic void tsec_dma_ctl(struct tsec_softc *sc, int state); 73188711Srajstatic int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74188711Sraj int fcb_inserted); 75176774Srajstatic void tsec_free_dma(struct tsec_softc *sc); 76182189Srajstatic void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77176774Srajstatic int tsec_ifmedia_upd(struct ifnet *ifp); 78176774Srajstatic void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79176774Srajstatic int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80176774Sraj struct mbuf **mbufp, uint32_t *paddr); 81176774Srajstatic void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82176774Sraj int nseg, int error); 83182189Srajstatic void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84182189Srajstatic void tsec_init(void *xsc); 85182189Srajstatic void tsec_init_locked(struct tsec_softc *sc); 86182189Srajstatic int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87182189Srajstatic void tsec_reset_mac(struct tsec_softc *sc); 88182189Srajstatic void tsec_setfilter(struct tsec_softc *sc); 89182189Srajstatic void tsec_set_mac_address(struct tsec_softc *sc); 90182189Srajstatic void tsec_start(struct ifnet *ifp); 91182189Srajstatic void tsec_start_locked(struct ifnet *ifp); 92176774Srajstatic void tsec_stop(struct tsec_softc *sc); 93182189Srajstatic void tsec_tick(void *arg); 94182189Srajstatic void tsec_watchdog(struct tsec_softc *sc); 95188711Srajstatic void tsec_add_sysctls(struct tsec_softc *sc); 96188711Srajstatic int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97188711Srajstatic int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98188711Srajstatic void tsec_set_rxic(struct tsec_softc *sc); 99188711Srajstatic void tsec_set_txic(struct tsec_softc *sc); 100188711Srajstatic void tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101188711Srajstatic void tsec_transmit_intr_locked(struct tsec_softc *sc); 102188711Srajstatic void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103188711Srajstatic void tsec_offload_setup(struct tsec_softc *sc); 104188711Srajstatic void tsec_offload_process_frame(struct tsec_softc *sc, 105188711Sraj struct mbuf *m); 106188711Srajstatic void tsec_setup_multicast(struct tsec_softc *sc); 107188711Srajstatic int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108176774Sraj 109182189Srajstruct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */ 110176774Sraj 111182189Srajdevclass_t tsec_devclass; 112182189SrajDRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 113182189SrajMODULE_DEPEND(tsec, ether, 1, 1, 1); 114182189SrajMODULE_DEPEND(tsec, miibus, 1, 1, 1); 115176774Sraj 116182189Srajint 117182189Srajtsec_attach(struct tsec_softc *sc) 118182189Sraj{ 119182189Sraj uint8_t hwaddr[ETHER_ADDR_LEN]; 120182189Sraj struct ifnet *ifp; 121182189Sraj bus_dmamap_t *map_ptr; 122182189Sraj bus_dmamap_t **map_pptr; 123182189Sraj int error = 0; 124182189Sraj int i; 125176774Sraj 126182189Sraj /* Reset all TSEC counters */ 127182189Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 128176774Sraj 129182189Sraj /* Stop DMA engine if enabled by firmware */ 130182189Sraj tsec_dma_ctl(sc, 0); 131176774Sraj 132182189Sraj /* Reset MAC */ 133182189Sraj tsec_reset_mac(sc); 134176774Sraj 135182189Sraj /* Disable interrupts for now */ 136182189Sraj tsec_intrs_ctl(sc, 0); 137176774Sraj 138188711Sraj /* Configure defaults for interrupts coalescing */ 139188711Sraj sc->rx_ic_time = 768; 140188711Sraj sc->rx_ic_count = 16; 141188711Sraj sc->tx_ic_time = 768; 142188711Sraj sc->tx_ic_count = 16; 143188711Sraj tsec_set_rxic(sc); 144188711Sraj tsec_set_txic(sc); 145188711Sraj tsec_add_sysctls(sc); 146188711Sraj 147182189Sraj /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 148188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 149188711Sraj &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 150182189Sraj (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 151188711Sraj 152182189Sraj if (error) { 153182189Sraj tsec_detach(sc); 154182189Sraj return (ENXIO); 155182189Sraj } 156176774Sraj 157182189Sraj /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 158188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 159188711Sraj &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 160182189Sraj (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 161182189Sraj if (error) { 162182189Sraj tsec_detach(sc); 163182189Sraj return (ENXIO); 164182189Sraj } 165176774Sraj 166182189Sraj /* Allocate a busdma tag for TX mbufs. */ 167182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 168188712Sraj TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 169188712Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 170188712Sraj BUS_SPACE_MAXADDR, /* highaddr */ 171188712Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 172188712Sraj MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 173188712Sraj TSEC_TX_NUM_DESC - 1, /* nsegments */ 174188712Sraj MCLBYTES, 0, /* maxsegsz, flags */ 175188712Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 176188712Sraj &sc->tsec_tx_mtag); /* dmat */ 177182189Sraj if (error) { 178188712Sraj device_printf(sc->dev, "failed to allocate busdma tag " 179188712Sraj "(tx mbufs)\n"); 180182189Sraj tsec_detach(sc); 181182189Sraj return (ENXIO); 182182189Sraj } 183182189Sraj 184182189Sraj /* Allocate a busdma tag for RX mbufs. */ 185182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 186188712Sraj TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 187188712Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 188188712Sraj BUS_SPACE_MAXADDR, /* highaddr */ 189188712Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 190188712Sraj MCLBYTES, /* maxsize */ 191188712Sraj 1, /* nsegments */ 192188712Sraj MCLBYTES, 0, /* maxsegsz, flags */ 193188712Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 194188712Sraj &sc->tsec_rx_mtag); /* dmat */ 195182189Sraj if (error) { 196188712Sraj device_printf(sc->dev, "failed to allocate busdma tag " 197188712Sraj "(rx mbufs)\n"); 198182189Sraj tsec_detach(sc); 199182189Sraj return (ENXIO); 200182189Sraj } 201182189Sraj 202182189Sraj /* Create TX busdma maps */ 203182189Sraj map_ptr = sc->tx_map_data; 204182189Sraj map_pptr = sc->tx_map_unused_data; 205182189Sraj 206182189Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 207182189Sraj map_pptr[i] = &map_ptr[i]; 208182189Sraj error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 209182189Sraj if (error) { 210182189Sraj device_printf(sc->dev, "failed to init TX ring\n"); 211182189Sraj tsec_detach(sc); 212182189Sraj return (ENXIO); 213182189Sraj } 214182189Sraj } 215182189Sraj 216182189Sraj /* Create RX busdma maps and zero mbuf handlers */ 217182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 218188712Sraj error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 219188712Sraj &sc->rx_data[i].map); 220182189Sraj if (error) { 221182189Sraj device_printf(sc->dev, "failed to init RX ring\n"); 222182189Sraj tsec_detach(sc); 223182189Sraj return (ENXIO); 224182189Sraj } 225182189Sraj sc->rx_data[i].mbuf = NULL; 226182189Sraj } 227182189Sraj 228182189Sraj /* Create mbufs for RX buffers */ 229182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 230182189Sraj error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 231182189Sraj &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 232182189Sraj if (error) { 233188712Sraj device_printf(sc->dev, "can't load rx DMA map %d, " 234188712Sraj "error = %d\n", i, error); 235182189Sraj tsec_detach(sc); 236182189Sraj return (error); 237182189Sraj } 238182189Sraj } 239182189Sraj 240182189Sraj /* Create network interface for upper layers */ 241182189Sraj ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 242182189Sraj if (ifp == NULL) { 243182189Sraj device_printf(sc->dev, "if_alloc() failed\n"); 244182189Sraj tsec_detach(sc); 245182189Sraj return (ENOMEM); 246182189Sraj } 247182189Sraj 248182189Sraj ifp->if_softc = sc; 249182189Sraj if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 250182189Sraj ifp->if_mtu = ETHERMTU; 251188711Sraj ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 252182189Sraj ifp->if_init = tsec_init; 253182189Sraj ifp->if_start = tsec_start; 254182189Sraj ifp->if_ioctl = tsec_ioctl; 255182189Sraj 256182189Sraj IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 257182189Sraj ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 258182189Sraj IFQ_SET_READY(&ifp->if_snd); 259182189Sraj 260188711Sraj ifp->if_capabilities = IFCAP_VLAN_MTU; 261188711Sraj if (sc->is_etsec) 262188711Sraj ifp->if_capabilities |= IFCAP_HWCSUM; 263188711Sraj 264182189Sraj ifp->if_capenable = ifp->if_capabilities; 265182189Sraj 266188711Sraj#ifdef DEVICE_POLLING 267188711Sraj /* Advertise that polling is supported */ 268188711Sraj ifp->if_capabilities |= IFCAP_POLLING; 269188711Sraj#endif 270188711Sraj 271182189Sraj /* Probe PHY(s) */ 272182189Sraj error = mii_phy_probe(sc->dev, &sc->tsec_miibus, tsec_ifmedia_upd, 273182189Sraj tsec_ifmedia_sts); 274182189Sraj if (error) { 275182189Sraj device_printf(sc->dev, "MII failed to find PHY!\n"); 276182189Sraj if_free(ifp); 277182189Sraj sc->tsec_ifp = NULL; 278182189Sraj tsec_detach(sc); 279182189Sraj return (error); 280182189Sraj } 281182189Sraj sc->tsec_mii = device_get_softc(sc->tsec_miibus); 282182189Sraj 283182189Sraj /* Set MAC address */ 284182189Sraj tsec_get_hwaddr(sc, hwaddr); 285182189Sraj ether_ifattach(ifp, hwaddr); 286182189Sraj 287182189Sraj return (0); 288182189Sraj} 289182189Sraj 290182189Srajint 291182189Srajtsec_detach(struct tsec_softc *sc) 292176774Sraj{ 293176774Sraj 294188711Sraj#ifdef DEVICE_POLLING 295188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 296188711Sraj ether_poll_deregister(sc->tsec_ifp); 297188711Sraj#endif 298188711Sraj 299182189Sraj /* Stop TSEC controller and free TX queue */ 300182189Sraj if (sc->sc_rres && sc->tsec_ifp) 301182189Sraj tsec_shutdown(sc->dev); 302182189Sraj 303182189Sraj /* Detach network interface */ 304182189Sraj if (sc->tsec_ifp) { 305182189Sraj ether_ifdetach(sc->tsec_ifp); 306182189Sraj if_free(sc->tsec_ifp); 307182189Sraj sc->tsec_ifp = NULL; 308177110Sraj } 309177110Sraj 310182189Sraj /* Free DMA resources */ 311182189Sraj tsec_free_dma(sc); 312176774Sraj 313182189Sraj return (0); 314176774Sraj} 315176774Sraj 316182189Srajvoid 317182189Srajtsec_shutdown(device_t dev) 318182189Sraj{ 319182189Sraj struct tsec_softc *sc; 320182189Sraj 321182189Sraj sc = device_get_softc(dev); 322182189Sraj 323182189Sraj TSEC_GLOBAL_LOCK(sc); 324182189Sraj tsec_stop(sc); 325182189Sraj TSEC_GLOBAL_UNLOCK(sc); 326182189Sraj} 327182189Sraj 328182189Srajint 329182189Srajtsec_suspend(device_t dev) 330182189Sraj{ 331182189Sraj 332182189Sraj /* TODO not implemented! */ 333182189Sraj return (0); 334182189Sraj} 335182189Sraj 336182189Srajint 337182189Srajtsec_resume(device_t dev) 338182189Sraj{ 339182189Sraj 340182189Sraj /* TODO not implemented! */ 341182189Sraj return (0); 342182189Sraj} 343182189Sraj 344176774Srajstatic void 345176774Srajtsec_init(void *xsc) 346176774Sraj{ 347176774Sraj struct tsec_softc *sc = xsc; 348176774Sraj 349176774Sraj TSEC_GLOBAL_LOCK(sc); 350176774Sraj tsec_init_locked(sc); 351176774Sraj TSEC_GLOBAL_UNLOCK(sc); 352176774Sraj} 353176774Sraj 354176774Srajstatic void 355176774Srajtsec_init_locked(struct tsec_softc *sc) 356176774Sraj{ 357176774Sraj struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 358176774Sraj struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 359176774Sraj struct ifnet *ifp = sc->tsec_ifp; 360188712Sraj uint32_t timeout, val, i; 361176774Sraj 362176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 363176774Sraj tsec_stop(sc); 364176774Sraj 365176774Sraj /* 366176774Sraj * These steps are according to the MPC8555E PowerQUICCIII RM: 367176774Sraj * 14.7 Initialization/Application Information 368176774Sraj */ 369176774Sraj 370176774Sraj /* Step 1: soft reset MAC */ 371176774Sraj tsec_reset_mac(sc); 372176774Sraj 373176774Sraj /* Step 2: Initialize MACCFG2 */ 374176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, 375176774Sraj TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 376176774Sraj TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 377176774Sraj TSEC_MACCFG2_GMII | /* I/F Mode bit */ 378176774Sraj TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 379176774Sraj ); 380176774Sraj 381176774Sraj /* Step 3: Initialize ECNTRL 382176774Sraj * While the documentation states that R100M is ignored if RPM is 383176774Sraj * not set, it does seem to be needed to get the orange boxes to 384176774Sraj * work (which have a Marvell 88E1111 PHY). Go figure. 385176774Sraj */ 386176774Sraj 387176774Sraj /* 388176774Sraj * XXX kludge - use circumstancial evidence to program ECNTRL 389176774Sraj * correctly. Ideally we need some board information to guide 390176774Sraj * us here. 391176774Sraj */ 392176774Sraj i = TSEC_READ(sc, TSEC_REG_ID2); 393176774Sraj val = (i & 0xffff) 394176774Sraj ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 395176774Sraj : TSEC_ECNTRL_R100M; /* Orange + CDS */ 396176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 397176774Sraj 398176774Sraj /* Step 4: Initialize MAC station address */ 399176774Sraj tsec_set_mac_address(sc); 400176774Sraj 401176774Sraj /* 402176774Sraj * Step 5: Assign a Physical address to the TBI so as to not conflict 403176774Sraj * with the external PHY physical address 404176774Sraj */ 405176774Sraj TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 406176774Sraj 407176774Sraj /* Step 6: Reset the management interface */ 408176774Sraj TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 409176774Sraj 410176774Sraj /* Step 7: Setup the MII Mgmt clock speed */ 411176774Sraj TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 412176774Sraj 413176774Sraj /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 414176774Sraj timeout = TSEC_READ_RETRY; 415176774Sraj while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) & 416176774Sraj TSEC_MIIMIND_BUSY)) 417176774Sraj DELAY(TSEC_READ_DELAY); 418176774Sraj if (timeout == 0) { 419176774Sraj if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 420176774Sraj return; 421176774Sraj } 422176774Sraj 423176774Sraj /* Step 9: Setup the MII Mgmt */ 424176774Sraj mii_mediachg(sc->tsec_mii); 425176774Sraj 426176774Sraj /* Step 10: Clear IEVENT register */ 427176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 428176774Sraj 429188711Sraj /* Step 11: Enable interrupts */ 430188711Sraj#ifdef DEVICE_POLLING 431188711Sraj /* 432188711Sraj * ...only if polling is not turned on. Disable interrupts explicitly 433188711Sraj * if polling is enabled. 434188711Sraj */ 435188711Sraj if (ifp->if_capenable & IFCAP_POLLING ) 436188711Sraj tsec_intrs_ctl(sc, 0); 437188711Sraj else 438188711Sraj#endif /* DEVICE_POLLING */ 439176774Sraj tsec_intrs_ctl(sc, 1); 440176774Sraj 441176774Sraj /* Step 12: Initialize IADDRn */ 442176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 443176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 444176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 445176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 446176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 447176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 448176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 449176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 450176774Sraj 451176774Sraj /* Step 13: Initialize GADDRn */ 452176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 453176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 454176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 455176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 456176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 457176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 458176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 459176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 460176774Sraj 461176774Sraj /* Step 14: Initialize RCTRL */ 462176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 463176774Sraj 464176774Sraj /* Step 15: Initialize DMACTRL */ 465176774Sraj tsec_dma_ctl(sc, 1); 466176774Sraj 467176774Sraj /* Step 16: Initialize FIFO_PAUSE_CTRL */ 468176774Sraj TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 469176774Sraj 470176774Sraj /* 471176774Sraj * Step 17: Initialize transmit/receive descriptor rings. 472176774Sraj * Initialize TBASE and RBASE. 473176774Sraj */ 474176774Sraj TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 475176774Sraj TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 476176774Sraj 477176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 478176774Sraj tx_desc[i].bufptr = 0; 479176774Sraj tx_desc[i].length = 0; 480188712Sraj tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 481188712Sraj TSEC_TXBD_W : 0); 482176774Sraj } 483182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 484182189Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 485176774Sraj 486176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 487176774Sraj rx_desc[i].bufptr = sc->rx_data[i].paddr; 488176774Sraj rx_desc[i].length = 0; 489176774Sraj rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 490182189Sraj ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 491176774Sraj } 492188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 493188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 494176774Sraj 495188711Sraj /* Step 18: Initialize the maximum receive buffer length */ 496188711Sraj TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 497176774Sraj 498188711Sraj /* Step 19: Configure ethernet frame sizes */ 499188711Sraj TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 500188711Sraj tsec_set_mtu(sc, ifp->if_mtu); 501188711Sraj 502188711Sraj /* Step 20: Enable Rx and RxBD sdata snooping */ 503176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 504176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 505176774Sraj 506188711Sraj /* Step 21: Reset collision counters in hardware */ 507176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 508176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 509176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 510176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 511176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 512176774Sraj 513188711Sraj /* Step 22: Mask all CAM interrupts */ 514176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 515176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 516176774Sraj 517188711Sraj /* Step 23: Enable Rx and Tx */ 518176774Sraj val = TSEC_READ(sc, TSEC_REG_MACCFG1); 519176774Sraj val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 520176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 521176774Sraj 522188711Sraj /* Step 24: Reset TSEC counters for Tx and Rx rings */ 523176774Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 524176774Sraj 525188711Sraj /* Step 25: Setup TCP/IP Off-Load engine */ 526188711Sraj if (sc->is_etsec) 527188711Sraj tsec_offload_setup(sc); 528188711Sraj 529188711Sraj /* Step 26: Setup multicast filters */ 530188711Sraj tsec_setup_multicast(sc); 531188711Sraj 532188711Sraj /* Step 27: Activate network interface */ 533176774Sraj ifp->if_drv_flags |= IFF_DRV_RUNNING; 534176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 535176774Sraj sc->tsec_if_flags = ifp->if_flags; 536182187Sraj sc->tsec_watchdog = 0; 537177111Sraj 538177111Sraj /* Schedule watchdog timeout */ 539182187Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 540176774Sraj} 541176774Sraj 542176774Srajstatic void 543176774Srajtsec_set_mac_address(struct tsec_softc *sc) 544176774Sraj{ 545176774Sraj uint32_t macbuf[2] = { 0, 0 }; 546188712Sraj char *macbufp, *curmac; 547182189Sraj int i; 548176774Sraj 549176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 550176774Sraj 551176774Sraj KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 552188712Sraj ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, 553188712Sraj sizeof(macbuf))); 554176774Sraj 555176774Sraj macbufp = (char *)macbuf; 556176774Sraj curmac = (char *)IF_LLADDR(sc->tsec_ifp); 557176774Sraj 558176774Sraj /* Correct order of MAC address bytes */ 559176774Sraj for (i = 1; i <= ETHER_ADDR_LEN; i++) 560176774Sraj macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 561176774Sraj 562176774Sraj /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 563176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 564176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 565176774Sraj} 566176774Sraj 567176774Sraj/* 568176774Sraj * DMA control function, if argument state is: 569176774Sraj * 0 - DMA engine will be disabled 570176774Sraj * 1 - DMA engine will be enabled 571176774Sraj */ 572176774Srajstatic void 573176774Srajtsec_dma_ctl(struct tsec_softc *sc, int state) 574176774Sraj{ 575176774Sraj device_t dev; 576188712Sraj uint32_t dma_flags, timeout; 577176774Sraj 578176774Sraj dev = sc->dev; 579176774Sraj 580176774Sraj dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 581176774Sraj 582176774Sraj switch (state) { 583176774Sraj case 0: 584176774Sraj /* Temporarily clear stop graceful stop bits. */ 585176774Sraj tsec_dma_ctl(sc, 1000); 586176774Sraj 587176774Sraj /* Set it again */ 588176774Sraj dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 589176774Sraj break; 590176774Sraj case 1000: 591176774Sraj case 1: 592176774Sraj /* Set write with response (WWR), wait (WOP) and snoop bits */ 593176774Sraj dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 594176774Sraj DMACTRL_WWR | DMACTRL_WOP); 595176774Sraj 596176774Sraj /* Clear graceful stop bits */ 597176774Sraj dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 598176774Sraj break; 599176774Sraj default: 600176774Sraj device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 601176774Sraj state); 602176774Sraj } 603176774Sraj 604176774Sraj TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 605176774Sraj 606176774Sraj switch (state) { 607176774Sraj case 0: 608176774Sraj /* Wait for DMA stop */ 609176774Sraj timeout = TSEC_READ_RETRY; 610176774Sraj while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 611176774Sraj (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 612176774Sraj DELAY(TSEC_READ_DELAY); 613176774Sraj 614176774Sraj if (timeout == 0) 615176774Sraj device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 616176774Sraj break; 617176774Sraj case 1: 618176774Sraj /* Restart transmission function */ 619176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 620176774Sraj } 621176774Sraj} 622176774Sraj 623176774Sraj/* 624176774Sraj * Interrupts control function, if argument state is: 625176774Sraj * 0 - all TSEC interrupts will be masked 626176774Sraj * 1 - all TSEC interrupts will be unmasked 627176774Sraj */ 628176774Srajstatic void 629176774Srajtsec_intrs_ctl(struct tsec_softc *sc, int state) 630176774Sraj{ 631176774Sraj device_t dev; 632176774Sraj 633176774Sraj dev = sc->dev; 634176774Sraj 635176774Sraj switch (state) { 636176774Sraj case 0: 637176774Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 638176774Sraj break; 639176774Sraj case 1: 640188712Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 641188712Sraj TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 642188712Sraj TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 643188712Sraj TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 644176774Sraj break; 645176774Sraj default: 646176774Sraj device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 647176774Sraj state); 648176774Sraj } 649176774Sraj} 650176774Sraj 651176774Srajstatic void 652176774Srajtsec_reset_mac(struct tsec_softc *sc) 653176774Sraj{ 654176774Sraj uint32_t maccfg1_flags; 655176774Sraj 656176774Sraj /* Set soft reset bit */ 657176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 658176774Sraj maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 659176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 660176774Sraj 661176774Sraj /* Clear soft reset bit */ 662176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 663176774Sraj maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 664176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 665176774Sraj} 666176774Sraj 667176774Srajstatic void 668177111Srajtsec_watchdog(struct tsec_softc *sc) 669176774Sraj{ 670177111Sraj struct ifnet *ifp; 671176774Sraj 672177111Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 673176774Sraj 674182187Sraj if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 675177111Sraj return; 676177111Sraj 677177111Sraj ifp = sc->tsec_ifp; 678176774Sraj ifp->if_oerrors++; 679176774Sraj if_printf(ifp, "watchdog timeout\n"); 680176774Sraj 681176774Sraj tsec_stop(sc); 682176774Sraj tsec_init_locked(sc); 683176774Sraj} 684176774Sraj 685176774Srajstatic void 686176774Srajtsec_start(struct ifnet *ifp) 687176774Sraj{ 688176774Sraj struct tsec_softc *sc = ifp->if_softc; 689176774Sraj 690176774Sraj TSEC_TRANSMIT_LOCK(sc); 691176774Sraj tsec_start_locked(ifp); 692176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 693176774Sraj} 694176774Sraj 695176774Srajstatic void 696176774Srajtsec_start_locked(struct ifnet *ifp) 697176774Sraj{ 698176774Sraj struct tsec_softc *sc; 699188711Sraj struct mbuf *m0, *mtmp; 700188711Sraj struct tsec_tx_fcb *tx_fcb; 701176774Sraj unsigned int queued = 0; 702188711Sraj int csum_flags, fcb_inserted = 0; 703176774Sraj 704176774Sraj sc = ifp->if_softc; 705176774Sraj 706176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 707176774Sraj 708176774Sraj if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 709176774Sraj IFF_DRV_RUNNING) 710176774Sraj return; 711176774Sraj 712176774Sraj if (sc->tsec_link == 0) 713176774Sraj return; 714176774Sraj 715188712Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 716188712Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 717176774Sraj 718176774Sraj for (;;) { 719176774Sraj /* Get packet from the queue */ 720176774Sraj IF_DEQUEUE(&ifp->if_snd, m0); 721176774Sraj if (m0 == NULL) 722176774Sraj break; 723176774Sraj 724188711Sraj /* Insert TCP/IP Off-load frame control block */ 725188711Sraj csum_flags = m0->m_pkthdr.csum_flags; 726188711Sraj if (csum_flags) { 727188711Sraj 728188711Sraj M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT); 729188711Sraj if (m0 == NULL) 730188711Sraj break; 731188711Sraj 732188711Sraj tx_fcb = mtod(m0, struct tsec_tx_fcb *); 733188711Sraj tx_fcb->flags = 0; 734188711Sraj tx_fcb->l3_offset = ETHER_HDR_LEN; 735188711Sraj tx_fcb->l4_offset = sizeof(struct ip); 736188711Sraj 737188711Sraj if (csum_flags & CSUM_IP) 738188711Sraj tx_fcb->flags |= TSEC_TX_FCB_IP4 | 739188711Sraj TSEC_TX_FCB_CSUM_IP; 740188711Sraj 741188711Sraj if (csum_flags & CSUM_TCP) 742188711Sraj tx_fcb->flags |= TSEC_TX_FCB_TCP | 743188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 744188711Sraj 745188711Sraj if (csum_flags & CSUM_UDP) 746188711Sraj tx_fcb->flags |= TSEC_TX_FCB_UDP | 747188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 748188711Sraj 749188711Sraj fcb_inserted = 1; 750188711Sraj } 751188711Sraj 752176774Sraj mtmp = m_defrag(m0, M_DONTWAIT); 753176774Sraj if (mtmp) 754176774Sraj m0 = mtmp; 755176774Sraj 756188711Sraj if (tsec_encap(sc, m0, fcb_inserted)) { 757176774Sraj IF_PREPEND(&ifp->if_snd, m0); 758176774Sraj ifp->if_drv_flags |= IFF_DRV_OACTIVE; 759176774Sraj break; 760176774Sraj } 761176774Sraj queued++; 762176774Sraj BPF_MTAP(ifp, m0); 763176774Sraj } 764188712Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 765188712Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 766176774Sraj 767176774Sraj if (queued) { 768176774Sraj /* Enable transmitter and watchdog timer */ 769176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 770182187Sraj sc->tsec_watchdog = 5; 771176774Sraj } 772176774Sraj} 773176774Sraj 774176774Srajstatic int 775188711Srajtsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 776176774Sraj{ 777176774Sraj struct tsec_desc *tx_desc = NULL; 778176774Sraj struct ifnet *ifp; 779176774Sraj bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 780176774Sraj bus_dmamap_t *mapp; 781188711Sraj int csum_flag = 0, error, seg, nsegs; 782176774Sraj 783176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 784176774Sraj 785176774Sraj ifp = sc->tsec_ifp; 786176774Sraj 787176774Sraj if (TSEC_FREE_TX_DESC(sc) == 0) { 788176774Sraj /* No free descriptors */ 789176774Sraj return (-1); 790176774Sraj } 791176774Sraj 792176774Sraj /* Fetch unused map */ 793176774Sraj mapp = TSEC_ALLOC_TX_MAP(sc); 794176774Sraj 795176774Sraj /* Create mapping in DMA memory */ 796176774Sraj error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 797188712Sraj *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 798176774Sraj if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 799176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 800176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 801176774Sraj return ((error != 0) ? error : -1); 802176774Sraj } 803176774Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 804176774Sraj 805176774Sraj if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 806176774Sraj if_printf(ifp, "TX buffer has %d segments\n", nsegs); 807176774Sraj 808188711Sraj if (fcb_inserted) 809188711Sraj csum_flag = TSEC_TXBD_TOE; 810188711Sraj 811176774Sraj /* Everything is ok, now we can send buffers */ 812176774Sraj for (seg = 0; seg < nsegs; seg++) { 813176774Sraj tx_desc = TSEC_GET_CUR_TX_DESC(sc); 814176774Sraj 815176774Sraj tx_desc->length = segs[seg].ds_len; 816176774Sraj tx_desc->bufptr = segs[seg].ds_addr; 817176774Sraj 818188711Sraj /* 819188711Sraj * Set flags: 820188711Sraj * - wrap 821188711Sraj * - checksum 822188711Sraj * - ready to send 823188711Sraj * - transmit the CRC sequence after the last data byte 824188711Sraj * - interrupt after the last buffer 825188711Sraj */ 826176774Sraj tx_desc->flags = 827188711Sraj (tx_desc->flags & TSEC_TXBD_W) | 828188711Sraj ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 829188711Sraj ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 830176774Sraj } 831176774Sraj 832176774Sraj /* Save mbuf and DMA mapping for release at later stage */ 833176774Sraj TSEC_PUT_TX_MBUF(sc, m0); 834176774Sraj TSEC_PUT_TX_MAP(sc, mapp); 835176774Sraj 836176774Sraj return (0); 837176774Sraj} 838176774Sraj 839176774Srajstatic void 840176774Srajtsec_setfilter(struct tsec_softc *sc) 841176774Sraj{ 842176774Sraj struct ifnet *ifp; 843176774Sraj uint32_t flags; 844176774Sraj 845176774Sraj ifp = sc->tsec_ifp; 846176774Sraj flags = TSEC_READ(sc, TSEC_REG_RCTRL); 847176774Sraj 848176774Sraj /* Promiscuous mode */ 849176774Sraj if (ifp->if_flags & IFF_PROMISC) 850176774Sraj flags |= TSEC_RCTRL_PROM; 851176774Sraj else 852176774Sraj flags &= ~TSEC_RCTRL_PROM; 853176774Sraj 854176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 855176774Sraj} 856176774Sraj 857188711Sraj#ifdef DEVICE_POLLING 858188711Srajstatic poll_handler_t tsec_poll; 859188711Sraj 860188711Srajstatic void 861188711Srajtsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 862188711Sraj{ 863188711Sraj uint32_t ie; 864188711Sraj struct tsec_softc *sc = ifp->if_softc; 865188711Sraj 866188711Sraj TSEC_GLOBAL_LOCK(sc); 867188711Sraj if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 868188711Sraj TSEC_GLOBAL_UNLOCK(sc); 869188711Sraj return; 870188711Sraj } 871188711Sraj 872188711Sraj if (cmd == POLL_AND_CHECK_STATUS) { 873188715Sraj tsec_error_intr_locked(sc, count); 874188711Sraj 875188711Sraj /* Clear all events reported */ 876188715Sraj ie = TSEC_READ(sc, TSEC_REG_IEVENT); 877188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 878188711Sraj } 879188711Sraj 880188711Sraj tsec_transmit_intr_locked(sc); 881188711Sraj 882188711Sraj TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 883188711Sraj 884188711Sraj tsec_receive_intr_locked(sc, count); 885188711Sraj 886188711Sraj TSEC_RECEIVE_UNLOCK(sc); 887188711Sraj} 888188711Sraj#endif /* DEVICE_POLLING */ 889188711Sraj 890176774Srajstatic int 891176774Srajtsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 892176774Sraj{ 893176774Sraj struct tsec_softc *sc = ifp->if_softc; 894176774Sraj struct ifreq *ifr = (struct ifreq *)data; 895176774Sraj device_t dev; 896188711Sraj int mask, error = 0; 897176774Sraj 898176774Sraj dev = sc->dev; 899176774Sraj 900176774Sraj switch (command) { 901188711Sraj case SIOCSIFMTU: 902188711Sraj TSEC_GLOBAL_LOCK(sc); 903188711Sraj if (tsec_set_mtu(sc, ifr->ifr_mtu)) 904188711Sraj ifp->if_mtu = ifr->ifr_mtu; 905188711Sraj else 906188711Sraj error = EINVAL; 907188711Sraj TSEC_GLOBAL_UNLOCK(sc); 908188711Sraj break; 909176774Sraj case SIOCSIFFLAGS: 910176774Sraj TSEC_GLOBAL_LOCK(sc); 911176774Sraj if (ifp->if_flags & IFF_UP) { 912176774Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 913188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 914188711Sraj IFF_PROMISC) 915176774Sraj tsec_setfilter(sc); 916188711Sraj 917188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 918188711Sraj IFF_ALLMULTI) 919188711Sraj tsec_setup_multicast(sc); 920176774Sraj } else 921176774Sraj tsec_init_locked(sc); 922182189Sraj } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 923182189Sraj tsec_stop(sc); 924182189Sraj 925176774Sraj sc->tsec_if_flags = ifp->if_flags; 926176774Sraj TSEC_GLOBAL_UNLOCK(sc); 927176774Sraj break; 928188711Sraj case SIOCADDMULTI: 929188711Sraj case SIOCDELMULTI: 930188711Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 931188711Sraj TSEC_GLOBAL_LOCK(sc); 932188711Sraj tsec_setup_multicast(sc); 933188711Sraj TSEC_GLOBAL_UNLOCK(sc); 934188711Sraj } 935176774Sraj case SIOCGIFMEDIA: 936176774Sraj case SIOCSIFMEDIA: 937188711Sraj error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 938188711Sraj command); 939176774Sraj break; 940188711Sraj case SIOCSIFCAP: 941188711Sraj mask = ifp->if_capenable ^ ifr->ifr_reqcap; 942188711Sraj if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 943188711Sraj TSEC_GLOBAL_LOCK(sc); 944188711Sraj ifp->if_capenable &= ~IFCAP_HWCSUM; 945188711Sraj ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 946188711Sraj tsec_offload_setup(sc); 947188711Sraj TSEC_GLOBAL_UNLOCK(sc); 948188711Sraj } 949188711Sraj#ifdef DEVICE_POLLING 950188711Sraj if (mask & IFCAP_POLLING) { 951188711Sraj if (ifr->ifr_reqcap & IFCAP_POLLING) { 952188711Sraj error = ether_poll_register(tsec_poll, ifp); 953188711Sraj if (error) 954188711Sraj return (error); 955188711Sraj 956188711Sraj TSEC_GLOBAL_LOCK(sc); 957188711Sraj /* Disable interrupts */ 958188711Sraj tsec_intrs_ctl(sc, 0); 959188711Sraj ifp->if_capenable |= IFCAP_POLLING; 960188711Sraj TSEC_GLOBAL_UNLOCK(sc); 961188711Sraj } else { 962188711Sraj error = ether_poll_deregister(ifp); 963188711Sraj TSEC_GLOBAL_LOCK(sc); 964188711Sraj /* Enable interrupts */ 965188711Sraj tsec_intrs_ctl(sc, 1); 966188711Sraj ifp->if_capenable &= ~IFCAP_POLLING; 967188711Sraj TSEC_GLOBAL_UNLOCK(sc); 968188711Sraj } 969188711Sraj } 970188711Sraj#endif 971188711Sraj break; 972188711Sraj 973176774Sraj default: 974176774Sraj error = ether_ioctl(ifp, command, data); 975176774Sraj } 976176774Sraj 977176774Sraj /* Flush buffers if not empty */ 978176774Sraj if (ifp->if_flags & IFF_UP) 979176774Sraj tsec_start(ifp); 980176774Sraj return (error); 981176774Sraj} 982176774Sraj 983176774Srajstatic int 984176774Srajtsec_ifmedia_upd(struct ifnet *ifp) 985176774Sraj{ 986176774Sraj struct tsec_softc *sc = ifp->if_softc; 987176774Sraj struct mii_data *mii; 988176774Sraj 989176774Sraj TSEC_TRANSMIT_LOCK(sc); 990176774Sraj 991176774Sraj mii = sc->tsec_mii; 992176774Sraj mii_mediachg(mii); 993176774Sraj 994176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 995176774Sraj return (0); 996176774Sraj} 997176774Sraj 998176774Srajstatic void 999176774Srajtsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1000176774Sraj{ 1001176774Sraj struct tsec_softc *sc = ifp->if_softc; 1002176774Sraj struct mii_data *mii; 1003176774Sraj 1004176774Sraj TSEC_TRANSMIT_LOCK(sc); 1005176774Sraj 1006176774Sraj mii = sc->tsec_mii; 1007176774Sraj mii_pollstat(mii); 1008176774Sraj 1009176774Sraj ifmr->ifm_active = mii->mii_media_active; 1010176774Sraj ifmr->ifm_status = mii->mii_media_status; 1011176774Sraj 1012176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 1013176774Sraj} 1014176774Sraj 1015176774Srajstatic int 1016176774Srajtsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1017182189Sraj uint32_t *paddr) 1018176774Sraj{ 1019176774Sraj struct mbuf *new_mbuf; 1020176774Sraj bus_dma_segment_t seg[1]; 1021188711Sraj int error, nsegs; 1022176774Sraj 1023176774Sraj KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1024176774Sraj 1025188711Sraj new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1026176774Sraj if (new_mbuf == NULL) 1027176774Sraj return (ENOBUFS); 1028176774Sraj new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1029176774Sraj 1030176774Sraj if (*mbufp) { 1031176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1032176774Sraj bus_dmamap_unload(tag, map); 1033176774Sraj } 1034176774Sraj 1035176774Sraj error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1036188712Sraj BUS_DMA_NOWAIT); 1037176774Sraj KASSERT(nsegs == 1, ("Too many segments returned!")); 1038176774Sraj if (nsegs != 1 || error) 1039176774Sraj panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1040176774Sraj 1041176774Sraj#if 0 1042176774Sraj if (error) { 1043176774Sraj printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1044176774Sraj error); 1045176774Sraj m_freem(new_mbuf); 1046176774Sraj return (ENOBUFS); 1047176774Sraj } 1048176774Sraj#endif 1049176774Sraj 1050176774Sraj#if 0 1051176774Sraj KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1052176774Sraj ("Wrong alignment of RX buffer!")); 1053176774Sraj#endif 1054176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1055176774Sraj 1056176774Sraj (*mbufp) = new_mbuf; 1057176774Sraj (*paddr) = seg->ds_addr; 1058176774Sraj return (0); 1059176774Sraj} 1060176774Sraj 1061176774Srajstatic void 1062176774Srajtsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1063176774Sraj{ 1064176774Sraj u_int32_t *paddr; 1065176774Sraj 1066176774Sraj KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1067176774Sraj paddr = arg; 1068176774Sraj *paddr = segs->ds_addr; 1069176774Sraj} 1070176774Sraj 1071176774Srajstatic int 1072176774Srajtsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1073176774Sraj bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1074176774Sraj{ 1075176774Sraj int error; 1076176774Sraj 1077176774Sraj /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1078176774Sraj error = bus_dma_tag_create(NULL, /* parent */ 1079176774Sraj PAGE_SIZE, 0, /* alignment, boundary */ 1080176774Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1081176774Sraj BUS_SPACE_MAXADDR, /* highaddr */ 1082176774Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 1083176774Sraj dsize, 1, /* maxsize, nsegments */ 1084176774Sraj dsize, 0, /* maxsegsz, flags */ 1085176774Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 1086176774Sraj dtag); /* dmat */ 1087176774Sraj 1088176774Sraj if (error) { 1089188712Sraj device_printf(dev, "failed to allocate busdma %s tag\n", 1090188712Sraj dname); 1091176774Sraj (*vaddr) = NULL; 1092176774Sraj return (ENXIO); 1093176774Sraj } 1094176774Sraj 1095176774Sraj error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1096188712Sraj dmap); 1097176774Sraj if (error) { 1098176774Sraj device_printf(dev, "failed to allocate %s DMA safe memory\n", 1099188712Sraj dname); 1100176774Sraj bus_dma_tag_destroy(*dtag); 1101176774Sraj (*vaddr) = NULL; 1102176774Sraj return (ENXIO); 1103176774Sraj } 1104176774Sraj 1105188712Sraj error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1106188712Sraj tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1107176774Sraj if (error) { 1108188712Sraj device_printf(dev, "cannot get address of the %s " 1109188712Sraj "descriptors\n", dname); 1110176774Sraj bus_dmamem_free(*dtag, *vaddr, *dmap); 1111176774Sraj bus_dma_tag_destroy(*dtag); 1112176774Sraj (*vaddr) = NULL; 1113176774Sraj return (ENXIO); 1114176774Sraj } 1115176774Sraj 1116176774Sraj return (0); 1117176774Sraj} 1118176774Sraj 1119176774Srajstatic void 1120176774Srajtsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1121176774Sraj{ 1122176774Sraj 1123176774Sraj if (vaddr == NULL) 1124176774Sraj return; 1125176774Sraj 1126176774Sraj /* Unmap descriptors from DMA memory */ 1127188712Sraj bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1128188712Sraj BUS_DMASYNC_POSTWRITE); 1129176774Sraj bus_dmamap_unload(dtag, dmap); 1130176774Sraj 1131176774Sraj /* Free descriptors memory */ 1132176774Sraj bus_dmamem_free(dtag, vaddr, dmap); 1133176774Sraj 1134176774Sraj /* Destroy descriptors tag */ 1135176774Sraj bus_dma_tag_destroy(dtag); 1136176774Sraj} 1137176774Sraj 1138176774Srajstatic void 1139176774Srajtsec_free_dma(struct tsec_softc *sc) 1140176774Sraj{ 1141176774Sraj int i; 1142176774Sraj 1143176774Sraj /* Free TX maps */ 1144176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1145176774Sraj if (sc->tx_map_data[i] != NULL) 1146188712Sraj bus_dmamap_destroy(sc->tsec_tx_mtag, 1147188712Sraj sc->tx_map_data[i]); 1148188712Sraj /* Destroy tag for TX mbufs */ 1149176774Sraj bus_dma_tag_destroy(sc->tsec_tx_mtag); 1150176774Sraj 1151176774Sraj /* Free RX mbufs and maps */ 1152176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1153176774Sraj if (sc->rx_data[i].mbuf) { 1154176774Sraj /* Unload buffer from DMA */ 1155176774Sraj bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1156176774Sraj BUS_DMASYNC_POSTREAD); 1157188712Sraj bus_dmamap_unload(sc->tsec_rx_mtag, 1158188712Sraj sc->rx_data[i].map); 1159176774Sraj 1160176774Sraj /* Free buffer */ 1161176774Sraj m_freem(sc->rx_data[i].mbuf); 1162176774Sraj } 1163176774Sraj /* Destroy map for this buffer */ 1164176774Sraj if (sc->rx_data[i].map != NULL) 1165176774Sraj bus_dmamap_destroy(sc->tsec_rx_mtag, 1166176774Sraj sc->rx_data[i].map); 1167176774Sraj } 1168188712Sraj /* Destroy tag for RX mbufs */ 1169176774Sraj bus_dma_tag_destroy(sc->tsec_rx_mtag); 1170176774Sraj 1171176774Sraj /* Unload TX/RX descriptors */ 1172176774Sraj tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1173176774Sraj sc->tsec_tx_vaddr); 1174176774Sraj tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1175176774Sraj sc->tsec_rx_vaddr); 1176176774Sraj} 1177176774Sraj 1178176774Srajstatic void 1179176774Srajtsec_stop(struct tsec_softc *sc) 1180176774Sraj{ 1181176774Sraj struct ifnet *ifp; 1182176774Sraj struct mbuf *m0; 1183176774Sraj bus_dmamap_t *mapp; 1184176774Sraj uint32_t tmpval; 1185176774Sraj 1186176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1187176774Sraj 1188176774Sraj ifp = sc->tsec_ifp; 1189176774Sraj 1190188712Sraj /* Disable interface and watchdog timer */ 1191182187Sraj callout_stop(&sc->tsec_callout); 1192176774Sraj ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1193182187Sraj sc->tsec_watchdog = 0; 1194176774Sraj 1195176774Sraj /* Disable all interrupts and stop DMA */ 1196176774Sraj tsec_intrs_ctl(sc, 0); 1197176774Sraj tsec_dma_ctl(sc, 0); 1198176774Sraj 1199176774Sraj /* Remove pending data from TX queue */ 1200176774Sraj while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1201176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1202176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1203176774Sraj 1204188711Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1205188711Sraj BUS_DMASYNC_POSTWRITE); 1206176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1207176774Sraj 1208176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1209176774Sraj m_freem(m0); 1210176774Sraj } 1211176774Sraj 1212188711Sraj /* Disable RX and TX */ 1213176774Sraj tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1214176774Sraj tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1215176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1216176774Sraj DELAY(10); 1217176774Sraj} 1218176774Sraj 1219188711Srajstatic void 1220188711Srajtsec_tick(void *arg) 1221176774Sraj{ 1222176774Sraj struct tsec_softc *sc = arg; 1223188711Sraj struct ifnet *ifp; 1224188711Sraj int link; 1225188711Sraj 1226188711Sraj TSEC_GLOBAL_LOCK(sc); 1227188711Sraj 1228188711Sraj tsec_watchdog(sc); 1229188711Sraj 1230188711Sraj ifp = sc->tsec_ifp; 1231188711Sraj link = sc->tsec_link; 1232188711Sraj 1233188711Sraj mii_tick(sc->tsec_mii); 1234188711Sraj 1235188711Sraj if (link == 0 && sc->tsec_link == 1 && 1236188711Sraj (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1237188711Sraj tsec_start_locked(ifp); 1238188711Sraj 1239188711Sraj /* Schedule another timeout one second from now. */ 1240188711Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1241188711Sraj 1242188711Sraj TSEC_GLOBAL_UNLOCK(sc); 1243188711Sraj} 1244188711Sraj 1245188711Sraj/* 1246188711Sraj * This is the core RX routine. It replenishes mbufs in the descriptor and 1247188711Sraj * sends data which have been dma'ed into host memory to upper layer. 1248188711Sraj * 1249188711Sraj * Loops at most count times if count is > 0, or until done if count < 0. 1250188711Sraj */ 1251188711Srajstatic void 1252188711Srajtsec_receive_intr_locked(struct tsec_softc *sc, int count) 1253188711Sraj{ 1254176774Sraj struct tsec_desc *rx_desc; 1255176774Sraj struct ifnet *ifp; 1256176774Sraj struct rx_data_type *rx_data; 1257176774Sraj struct mbuf *m; 1258176774Sraj device_t dev; 1259176774Sraj uint32_t i; 1260188711Sraj int c; 1261176774Sraj uint16_t flags; 1262176774Sraj 1263188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1264188711Sraj 1265176774Sraj ifp = sc->tsec_ifp; 1266176774Sraj rx_data = sc->rx_data; 1267176774Sraj dev = sc->dev; 1268176774Sraj 1269188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1270188711Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1271176774Sraj 1272188711Sraj for (c = 0; ; c++) { 1273188711Sraj if (count >= 0 && count-- == 0) 1274188711Sraj break; 1275176774Sraj 1276176774Sraj rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1277176774Sraj flags = rx_desc->flags; 1278176774Sraj 1279176774Sraj /* Check if there is anything to receive */ 1280188711Sraj if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1281176774Sraj /* 1282176774Sraj * Avoid generating another interrupt 1283176774Sraj */ 1284176774Sraj if (flags & TSEC_RXBD_E) 1285176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 1286176774Sraj TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1287176774Sraj /* 1288176774Sraj * We didn't consume current descriptor and have to 1289176774Sraj * return it to the queue 1290176774Sraj */ 1291176774Sraj TSEC_BACK_CUR_RX_DESC(sc); 1292176774Sraj break; 1293176774Sraj } 1294176774Sraj 1295176774Sraj if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1296176774Sraj TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1297182189Sraj 1298176774Sraj rx_desc->length = 0; 1299188711Sraj rx_desc->flags = (rx_desc->flags & 1300188711Sraj ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1301188711Sraj 1302188711Sraj if (sc->frame != NULL) { 1303188711Sraj m_free(sc->frame); 1304188711Sraj sc->frame = NULL; 1305188711Sraj } 1306188711Sraj 1307176774Sraj continue; 1308176774Sraj } 1309176774Sraj 1310176774Sraj /* Ok... process frame */ 1311176774Sraj i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1312176774Sraj m = rx_data[i].mbuf; 1313188711Sraj m->m_len = rx_desc->length; 1314176774Sraj 1315188711Sraj if (sc->frame != NULL) { 1316188711Sraj if ((flags & TSEC_RXBD_L) != 0) 1317188711Sraj m->m_len -= m_length(sc->frame, NULL); 1318188711Sraj 1319188711Sraj m->m_flags &= ~M_PKTHDR; 1320188711Sraj m_cat(sc->frame, m); 1321188711Sraj } else { 1322188711Sraj sc->frame = m; 1323188711Sraj } 1324188711Sraj 1325188711Sraj m = NULL; 1326188711Sraj 1327188711Sraj if ((flags & TSEC_RXBD_L) != 0) { 1328188711Sraj m = sc->frame; 1329188711Sraj sc->frame = NULL; 1330188711Sraj } 1331188711Sraj 1332176774Sraj if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1333176774Sraj &rx_data[i].mbuf, &rx_data[i].paddr)) { 1334176774Sraj ifp->if_ierrors++; 1335188713Sraj /* 1336188713Sraj * We ran out of mbufs; didn't consume current 1337188713Sraj * descriptor and have to return it to the queue. 1338188713Sraj */ 1339188713Sraj TSEC_BACK_CUR_RX_DESC(sc); 1340188713Sraj break; 1341176774Sraj } 1342188711Sraj 1343188711Sraj /* Attach new buffer to descriptor and clear flags */ 1344176774Sraj rx_desc->bufptr = rx_data[i].paddr; 1345176774Sraj rx_desc->length = 0; 1346176774Sraj rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1347176774Sraj TSEC_RXBD_E | TSEC_RXBD_I; 1348176774Sraj 1349188711Sraj if (m != NULL) { 1350188711Sraj m->m_pkthdr.rcvif = ifp; 1351176774Sraj 1352188711Sraj m_fixhdr(m); 1353188711Sraj m_adj(m, -ETHER_CRC_LEN); 1354176774Sraj 1355188711Sraj if (sc->is_etsec) 1356188711Sraj tsec_offload_process_frame(sc, m); 1357176774Sraj 1358188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1359188711Sraj (*ifp->if_input)(ifp, m); 1360188711Sraj TSEC_RECEIVE_LOCK(sc); 1361188711Sraj } 1362188711Sraj } 1363176774Sraj 1364188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1365188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1366176774Sraj} 1367176774Sraj 1368182189Srajvoid 1369188711Srajtsec_receive_intr(void *arg) 1370176774Sraj{ 1371176774Sraj struct tsec_softc *sc = arg; 1372188711Sraj 1373188711Sraj TSEC_RECEIVE_LOCK(sc); 1374188711Sraj 1375188711Sraj#ifdef DEVICE_POLLING 1376188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1377188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1378188711Sraj return; 1379188711Sraj } 1380188711Sraj#endif 1381188711Sraj 1382188711Sraj /* Confirm the interrupt was received by driver */ 1383188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1384188711Sraj tsec_receive_intr_locked(sc, -1); 1385188711Sraj 1386188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1387188711Sraj} 1388188711Sraj 1389188711Srajstatic void 1390188711Srajtsec_transmit_intr_locked(struct tsec_softc *sc) 1391188711Sraj{ 1392176774Sraj struct tsec_desc *tx_desc; 1393176774Sraj struct ifnet *ifp; 1394176774Sraj struct mbuf *m0; 1395176774Sraj bus_dmamap_t *mapp; 1396176774Sraj int send = 0; 1397176774Sraj 1398188711Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 1399188711Sraj 1400176774Sraj ifp = sc->tsec_ifp; 1401176774Sraj 1402176774Sraj /* Update collision statistics */ 1403176774Sraj ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1404176774Sraj 1405176774Sraj /* Reset collision counters in hardware */ 1406176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1407176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1408176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1409176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1410176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1411176774Sraj 1412182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1413182189Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1414176774Sraj 1415176774Sraj while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1416176774Sraj tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1417176774Sraj if (tx_desc->flags & TSEC_TXBD_R) { 1418176774Sraj TSEC_BACK_DIRTY_TX_DESC(sc); 1419176774Sraj break; 1420176774Sraj } 1421176774Sraj 1422176774Sraj if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1423176774Sraj continue; 1424176774Sraj 1425176774Sraj /* 1426176774Sraj * This is the last buf in this packet, so unmap and free it. 1427176774Sraj */ 1428176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1429176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1430176774Sraj 1431188712Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1432188712Sraj BUS_DMASYNC_POSTWRITE); 1433176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1434176774Sraj 1435176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1436176774Sraj m_freem(m0); 1437176774Sraj 1438176774Sraj ifp->if_opackets++; 1439176774Sraj send = 1; 1440176774Sraj } 1441188711Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1442188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1443176774Sraj 1444176774Sraj if (send) { 1445176774Sraj /* Now send anything that was pending */ 1446176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1447176774Sraj tsec_start_locked(ifp); 1448176774Sraj 1449188711Sraj /* Stop wathdog if all sent */ 1450176774Sraj if (TSEC_EMPTYQ_TX_MBUF(sc)) 1451182187Sraj sc->tsec_watchdog = 0; 1452176774Sraj } 1453176774Sraj} 1454176774Sraj 1455182189Srajvoid 1456188711Srajtsec_transmit_intr(void *arg) 1457176774Sraj{ 1458176774Sraj struct tsec_softc *sc = arg; 1459188711Sraj 1460188711Sraj TSEC_TRANSMIT_LOCK(sc); 1461188711Sraj 1462188711Sraj#ifdef DEVICE_POLLING 1463188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1464188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1465188711Sraj return; 1466188711Sraj } 1467188711Sraj#endif 1468188711Sraj /* Confirm the interrupt was received by driver */ 1469188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1470188711Sraj tsec_transmit_intr_locked(sc); 1471188711Sraj 1472188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1473188711Sraj} 1474188711Sraj 1475188711Srajstatic void 1476188711Srajtsec_error_intr_locked(struct tsec_softc *sc, int count) 1477188711Sraj{ 1478176774Sraj struct ifnet *ifp; 1479176774Sraj uint32_t eflags; 1480176774Sraj 1481188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1482188711Sraj 1483176774Sraj ifp = sc->tsec_ifp; 1484176774Sraj 1485176774Sraj eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1486176774Sraj 1487176774Sraj /* Clear events bits in hardware */ 1488176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1489176774Sraj TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1490176774Sraj TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1491176774Sraj TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1492176774Sraj 1493176774Sraj /* Check transmitter errors */ 1494176774Sraj if (eflags & TSEC_IEVENT_TXE) { 1495176774Sraj ifp->if_oerrors++; 1496176774Sraj 1497176774Sraj if (eflags & TSEC_IEVENT_LC) 1498176774Sraj ifp->if_collisions++; 1499176774Sraj 1500176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1501176774Sraj } 1502176774Sraj 1503176774Sraj /* Check receiver errors */ 1504176774Sraj if (eflags & TSEC_IEVENT_BSY) { 1505176774Sraj ifp->if_ierrors++; 1506176774Sraj ifp->if_iqdrops++; 1507176774Sraj 1508176774Sraj /* Get data from RX buffers */ 1509188711Sraj tsec_receive_intr_locked(sc, count); 1510176774Sraj 1511176774Sraj /* Make receiver again active */ 1512176774Sraj TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1513176774Sraj } 1514188711Sraj 1515188711Sraj if (ifp->if_flags & IFF_DEBUG) 1516188711Sraj if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1517188711Sraj eflags); 1518188711Sraj 1519188711Sraj if (eflags & TSEC_IEVENT_EBERR) { 1520188711Sraj if_printf(ifp, "System bus error occurred during" 1521188711Sraj "DMA transaction (flags: 0x%x)\n", eflags); 1522188711Sraj tsec_init_locked(sc); 1523188711Sraj } 1524188711Sraj 1525188711Sraj if (eflags & TSEC_IEVENT_BABT) 1526188711Sraj ifp->if_oerrors++; 1527188711Sraj 1528176774Sraj if (eflags & TSEC_IEVENT_BABR) 1529176774Sraj ifp->if_ierrors++; 1530176774Sraj} 1531176774Sraj 1532188711Srajvoid 1533188711Srajtsec_error_intr(void *arg) 1534176774Sraj{ 1535188711Sraj struct tsec_softc *sc = arg; 1536176774Sraj 1537177111Sraj TSEC_GLOBAL_LOCK(sc); 1538188711Sraj tsec_error_intr_locked(sc, -1); 1539177111Sraj TSEC_GLOBAL_UNLOCK(sc); 1540176774Sraj} 1541176774Sraj 1542182189Srajint 1543176774Srajtsec_miibus_readreg(device_t dev, int phy, int reg) 1544176774Sraj{ 1545176774Sraj struct tsec_softc *sc; 1546176774Sraj uint32_t timeout; 1547176774Sraj 1548176774Sraj sc = device_get_softc(dev); 1549176774Sraj 1550176774Sraj if (device_get_unit(dev) != phy) 1551176774Sraj return (0); 1552176774Sraj 1553176774Sraj sc = tsec0_sc; 1554176774Sraj 1555176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1556176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1557176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1558176774Sraj 1559176774Sraj timeout = TSEC_READ_RETRY; 1560176774Sraj while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) & 1561176774Sraj (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1562176774Sraj DELAY(TSEC_READ_DELAY); 1563176774Sraj 1564176774Sraj if (timeout == 0) 1565176774Sraj device_printf(dev, "Timeout while reading from PHY!\n"); 1566176774Sraj 1567176774Sraj return (TSEC_READ(sc, TSEC_REG_MIIMSTAT)); 1568176774Sraj} 1569176774Sraj 1570182189Srajvoid 1571176774Srajtsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1572176774Sraj{ 1573176774Sraj struct tsec_softc *sc; 1574176774Sraj uint32_t timeout; 1575176774Sraj 1576176774Sraj sc = device_get_softc(dev); 1577176774Sraj 1578176774Sraj if (device_get_unit(dev) != phy) 1579188712Sraj device_printf(dev, "Trying to write to an alien PHY(%d)\n", 1580188712Sraj phy); 1581176774Sraj 1582176774Sraj sc = tsec0_sc; 1583176774Sraj 1584176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1585176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMCON, value); 1586176774Sraj 1587176774Sraj timeout = TSEC_READ_RETRY; 1588188712Sraj while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & 1589188712Sraj TSEC_MIIMIND_BUSY)) 1590176774Sraj DELAY(TSEC_READ_DELAY); 1591176774Sraj 1592176774Sraj if (timeout == 0) 1593176774Sraj device_printf(dev, "Timeout while writing to PHY!\n"); 1594176774Sraj} 1595176774Sraj 1596182189Srajvoid 1597176774Srajtsec_miibus_statchg(device_t dev) 1598176774Sraj{ 1599176774Sraj struct tsec_softc *sc; 1600176774Sraj struct mii_data *mii; 1601176774Sraj uint32_t ecntrl, id, tmp; 1602176774Sraj int link; 1603176774Sraj 1604176774Sraj sc = device_get_softc(dev); 1605176774Sraj mii = sc->tsec_mii; 1606176774Sraj link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1607176774Sraj 1608176774Sraj tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1609176774Sraj 1610176774Sraj if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1611176774Sraj tmp |= TSEC_MACCFG2_FULLDUPLEX; 1612176774Sraj else 1613176774Sraj tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1614176774Sraj 1615176774Sraj switch (IFM_SUBTYPE(mii->mii_media_active)) { 1616176774Sraj case IFM_1000_T: 1617176774Sraj case IFM_1000_SX: 1618176774Sraj tmp |= TSEC_MACCFG2_GMII; 1619176774Sraj sc->tsec_link = link; 1620176774Sraj break; 1621176774Sraj case IFM_100_TX: 1622176774Sraj case IFM_10_T: 1623176774Sraj tmp |= TSEC_MACCFG2_MII; 1624176774Sraj sc->tsec_link = link; 1625176774Sraj break; 1626176774Sraj case IFM_NONE: 1627176774Sraj if (link) 1628188712Sraj device_printf(dev, "No speed selected but link " 1629188712Sraj "active!\n"); 1630176774Sraj sc->tsec_link = 0; 1631176774Sraj return; 1632176774Sraj default: 1633176774Sraj sc->tsec_link = 0; 1634176774Sraj device_printf(dev, "Unknown speed (%d), link %s!\n", 1635176774Sraj IFM_SUBTYPE(mii->mii_media_active), 1636182189Sraj ((link) ? "up" : "down")); 1637176774Sraj return; 1638176774Sraj } 1639176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1640176774Sraj 1641176774Sraj /* XXX kludge - use circumstantial evidence for reduced mode. */ 1642176774Sraj id = TSEC_READ(sc, TSEC_REG_ID2); 1643176774Sraj if (id & 0xffff) { 1644176774Sraj ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1645176774Sraj ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1646176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1647176774Sraj } 1648176774Sraj} 1649188711Sraj 1650188711Srajstatic void 1651188711Srajtsec_add_sysctls(struct tsec_softc *sc) 1652188711Sraj{ 1653188711Sraj struct sysctl_ctx_list *ctx; 1654188711Sraj struct sysctl_oid_list *children; 1655188711Sraj struct sysctl_oid *tree; 1656188711Sraj 1657188711Sraj ctx = device_get_sysctl_ctx(sc->dev); 1658188711Sraj children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1659188711Sraj tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1660188711Sraj CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1661188711Sraj children = SYSCTL_CHILDREN(tree); 1662188711Sraj 1663188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1664188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1665188711Sraj "I", "IC RX time threshold (0-65535)"); 1666188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1667188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1668188711Sraj "I", "IC RX frame count threshold (0-255)"); 1669188711Sraj 1670188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1671188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1672188711Sraj "I", "IC TX time threshold (0-65535)"); 1673188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1674188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1675188711Sraj "I", "IC TX frame count threshold (0-255)"); 1676188711Sraj} 1677188711Sraj 1678188711Sraj/* 1679188711Sraj * With Interrupt Coalescing (IC) active, a transmit/receive frame 1680188711Sraj * interrupt is raised either upon: 1681188711Sraj * 1682188711Sraj * - threshold-defined period of time elapsed, or 1683188711Sraj * - threshold-defined number of frames is received/transmitted, 1684188711Sraj * whichever occurs first. 1685188711Sraj * 1686188711Sraj * The following sysctls regulate IC behaviour (for TX/RX separately): 1687188711Sraj * 1688188711Sraj * dev.tsec.<unit>.int_coal.rx_time 1689188711Sraj * dev.tsec.<unit>.int_coal.rx_count 1690188711Sraj * dev.tsec.<unit>.int_coal.tx_time 1691188711Sraj * dev.tsec.<unit>.int_coal.tx_count 1692188711Sraj * 1693188711Sraj * Values: 1694188711Sraj * 1695188711Sraj * - 0 for either time or count disables IC on the given TX/RX path 1696188711Sraj * 1697188711Sraj * - count: 1-255 (expresses frame count number; note that value of 1 is 1698188711Sraj * effectively IC off) 1699188711Sraj * 1700188711Sraj * - time: 1-65535 (value corresponds to a real time period and is 1701188711Sraj * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1702188711Sraj * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1703188711Sraj * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1704188711Sraj * TSEC reference manual. 1705188711Sraj */ 1706188711Sraj 1707188711Srajstatic int 1708188711Srajtsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1709188711Sraj{ 1710188711Sraj int error; 1711188711Sraj uint32_t time; 1712188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1713188711Sraj 1714188711Sraj time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1715188711Sraj 1716188711Sraj error = sysctl_handle_int(oidp, &time, 0, req); 1717188711Sraj if (error != 0) 1718188711Sraj return (error); 1719188711Sraj 1720188711Sraj if (time > 65535) 1721188711Sraj return (EINVAL); 1722188711Sraj 1723188711Sraj TSEC_IC_LOCK(sc); 1724188711Sraj if (arg2 == TSEC_IC_RX) { 1725188711Sraj sc->rx_ic_time = time; 1726188711Sraj tsec_set_rxic(sc); 1727188711Sraj } else { 1728188711Sraj sc->tx_ic_time = time; 1729188711Sraj tsec_set_txic(sc); 1730188711Sraj } 1731188711Sraj TSEC_IC_UNLOCK(sc); 1732188711Sraj 1733188711Sraj return (0); 1734188711Sraj} 1735188711Sraj 1736188711Srajstatic int 1737188711Srajtsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1738188711Sraj{ 1739188711Sraj int error; 1740188711Sraj uint32_t count; 1741188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1742188711Sraj 1743188711Sraj count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1744188711Sraj 1745188711Sraj error = sysctl_handle_int(oidp, &count, 0, req); 1746188711Sraj if (error != 0) 1747188711Sraj return (error); 1748188711Sraj 1749188711Sraj if (count > 255) 1750188711Sraj return (EINVAL); 1751188711Sraj 1752188711Sraj TSEC_IC_LOCK(sc); 1753188711Sraj if (arg2 == TSEC_IC_RX) { 1754188711Sraj sc->rx_ic_count = count; 1755188711Sraj tsec_set_rxic(sc); 1756188711Sraj } else { 1757188711Sraj sc->tx_ic_count = count; 1758188711Sraj tsec_set_txic(sc); 1759188711Sraj } 1760188711Sraj TSEC_IC_UNLOCK(sc); 1761188711Sraj 1762188711Sraj return (0); 1763188711Sraj} 1764188711Sraj 1765188711Srajstatic void 1766188711Srajtsec_set_rxic(struct tsec_softc *sc) 1767188711Sraj{ 1768188711Sraj uint32_t rxic_val; 1769188711Sraj 1770188711Sraj if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1771188711Sraj /* Disable RX IC */ 1772188711Sraj rxic_val = 0; 1773188711Sraj else { 1774188711Sraj rxic_val = 0x80000000; 1775188711Sraj rxic_val |= (sc->rx_ic_count << 21); 1776188711Sraj rxic_val |= sc->rx_ic_time; 1777188711Sraj } 1778188711Sraj 1779188711Sraj TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1780188711Sraj} 1781188711Sraj 1782188711Srajstatic void 1783188711Srajtsec_set_txic(struct tsec_softc *sc) 1784188711Sraj{ 1785188711Sraj uint32_t txic_val; 1786188711Sraj 1787188711Sraj if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1788188711Sraj /* Disable TX IC */ 1789188711Sraj txic_val = 0; 1790188711Sraj else { 1791188711Sraj txic_val = 0x80000000; 1792188711Sraj txic_val |= (sc->tx_ic_count << 21); 1793188711Sraj txic_val |= sc->tx_ic_time; 1794188711Sraj } 1795188711Sraj 1796188711Sraj TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1797188711Sraj} 1798188711Sraj 1799188711Srajstatic void 1800188711Srajtsec_offload_setup(struct tsec_softc *sc) 1801188711Sraj{ 1802188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1803188711Sraj uint32_t reg; 1804188711Sraj 1805188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1806188711Sraj 1807188711Sraj reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1808188711Sraj reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1809188711Sraj 1810188711Sraj if (ifp->if_capenable & IFCAP_TXCSUM) 1811188711Sraj ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1812188711Sraj else 1813188711Sraj ifp->if_hwassist = 0; 1814188711Sraj 1815188711Sraj TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1816188711Sraj 1817188711Sraj reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1818188711Sraj reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1819188711Sraj reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1820188711Sraj 1821188711Sraj if (ifp->if_capenable & IFCAP_RXCSUM) 1822188711Sraj reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1823188711Sraj TSEC_RCTRL_PRSDEP_PARSE_L234; 1824188711Sraj 1825188711Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1826188711Sraj} 1827188711Sraj 1828188711Sraj 1829188711Srajstatic void 1830188711Srajtsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1831188711Sraj{ 1832188711Sraj struct tsec_rx_fcb rx_fcb; 1833188711Sraj int csum_flags = 0; 1834188711Sraj int protocol, flags; 1835188711Sraj 1836188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1837188711Sraj 1838188711Sraj m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1839188711Sraj flags = rx_fcb.flags; 1840188711Sraj protocol = rx_fcb.protocol; 1841188711Sraj 1842188711Sraj if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1843188711Sraj csum_flags |= CSUM_IP_CHECKED; 1844188711Sraj 1845188711Sraj if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1846188711Sraj csum_flags |= CSUM_IP_VALID; 1847188711Sraj } 1848188711Sraj 1849188711Sraj if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1850188711Sraj TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1851188711Sraj (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1852188711Sraj 1853188711Sraj csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1854188711Sraj m->m_pkthdr.csum_data = 0xFFFF; 1855188711Sraj } 1856188711Sraj 1857188711Sraj m->m_pkthdr.csum_flags = csum_flags; 1858188711Sraj 1859188711Sraj if (flags & TSEC_RX_FCB_VLAN) { 1860188711Sraj m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1861188711Sraj m->m_flags |= M_VLANTAG; 1862188711Sraj } 1863188711Sraj 1864188711Sraj m_adj(m, sizeof(struct tsec_rx_fcb)); 1865188711Sraj} 1866188711Sraj 1867188711Srajstatic void 1868188711Srajtsec_setup_multicast(struct tsec_softc *sc) 1869188711Sraj{ 1870188711Sraj uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1871188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1872188711Sraj struct ifmultiaddr *ifma; 1873188711Sraj uint32_t h; 1874188711Sraj int i; 1875188711Sraj 1876188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1877188711Sraj 1878188711Sraj if (ifp->if_flags & IFF_ALLMULTI) { 1879188711Sraj for (i = 0; i < 8; i++) 1880188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1881188711Sraj 1882188711Sraj return; 1883188711Sraj } 1884188711Sraj 1885188711Sraj IF_ADDR_LOCK(ifp); 1886188711Sraj TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1887188711Sraj 1888188711Sraj if (ifma->ifma_addr->sa_family != AF_LINK) 1889188711Sraj continue; 1890188711Sraj 1891188711Sraj h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1892188711Sraj ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1893188711Sraj 1894188711Sraj hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1895188711Sraj } 1896188711Sraj IF_ADDR_UNLOCK(ifp); 1897188711Sraj 1898188711Sraj for (i = 0; i < 8; i++) 1899188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1900188711Sraj} 1901188711Sraj 1902188711Srajstatic int 1903188711Srajtsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1904188711Sraj{ 1905188711Sraj 1906188711Sraj mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1907188711Sraj 1908188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1909188711Sraj 1910188711Sraj if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1911188711Sraj TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1912188711Sraj return (mtu); 1913188711Sraj } 1914188711Sraj 1915188711Sraj return (0); 1916188711Sraj} 1917