if_tsec.c revision 188711
1176774Sraj/*- 2182189Sraj * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3182189Sraj * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski <ppk@semihalf.com> 4176774Sraj * All rights reserved. 5176774Sraj * 6176774Sraj * Redistribution and use in source and binary forms, with or without 7176774Sraj * modification, are permitted provided that the following conditions 8176774Sraj * are met: 9176774Sraj * 1. Redistributions of source code must retain the above copyright 10176774Sraj * notice, this list of conditions and the following disclaimer. 11176774Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176774Sraj * notice, this list of conditions and the following disclaimer in the 13176774Sraj * documentation and/or other materials provided with the distribution. 14176774Sraj * 15176774Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176774Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176774Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176774Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176774Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176774Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176774Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176774Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176774Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176774Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176774Sraj */ 26176774Sraj 27176774Sraj/* 28176774Sraj * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29176774Sraj */ 30176774Sraj#include <sys/cdefs.h> 31176774Sraj__FBSDID("$FreeBSD: head/sys/dev/tsec/if_tsec.c 188711 2009-02-17 14:57:05Z raj $"); 32176774Sraj 33188711Sraj#ifdef HAVE_KERNEL_OPTION_HEADERS 34188711Sraj#include "opt_device_polling.h" 35188711Sraj#endif 36188711Sraj 37176774Sraj#include <sys/param.h> 38176774Sraj#include <sys/systm.h> 39182189Sraj#include <sys/bus.h> 40176774Sraj#include <sys/endian.h> 41176774Sraj#include <sys/mbuf.h> 42176774Sraj#include <sys/kernel.h> 43176774Sraj#include <sys/module.h> 44176774Sraj#include <sys/socket.h> 45182189Sraj#include <sys/sockio.h> 46176774Sraj#include <sys/sysctl.h> 47176774Sraj 48182189Sraj#include <net/bpf.h> 49182189Sraj#include <net/ethernet.h> 50176774Sraj#include <net/if.h> 51182189Sraj#include <net/if_arp.h> 52176774Sraj#include <net/if_dl.h> 53176774Sraj#include <net/if_media.h> 54182189Sraj#include <net/if_types.h> 55182189Sraj#include <net/if_vlan_var.h> 56176774Sraj 57188711Sraj#include <netinet/in_systm.h> 58188711Sraj#include <netinet/in.h> 59188711Sraj#include <netinet/ip.h> 60188711Sraj 61176774Sraj#include <machine/bus.h> 62176774Sraj 63176774Sraj#include <dev/mii/mii.h> 64176774Sraj#include <dev/mii/miivar.h> 65176774Sraj 66176774Sraj#include <dev/tsec/if_tsec.h> 67176774Sraj#include <dev/tsec/if_tsecreg.h> 68176774Sraj 69182189Srajstatic int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70182189Sraj bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71182189Sraj const char *dname); 72182189Srajstatic void tsec_dma_ctl(struct tsec_softc *sc, int state); 73188711Srajstatic int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74188711Sraj int fcb_inserted); 75176774Srajstatic void tsec_free_dma(struct tsec_softc *sc); 76182189Srajstatic void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77176774Srajstatic int tsec_ifmedia_upd(struct ifnet *ifp); 78176774Srajstatic void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79176774Srajstatic int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80176774Sraj struct mbuf **mbufp, uint32_t *paddr); 81176774Srajstatic void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82176774Sraj int nseg, int error); 83182189Srajstatic void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84182189Srajstatic void tsec_init(void *xsc); 85182189Srajstatic void tsec_init_locked(struct tsec_softc *sc); 86182189Srajstatic int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87182189Srajstatic void tsec_reset_mac(struct tsec_softc *sc); 88182189Srajstatic void tsec_setfilter(struct tsec_softc *sc); 89182189Srajstatic void tsec_set_mac_address(struct tsec_softc *sc); 90182189Srajstatic void tsec_start(struct ifnet *ifp); 91182189Srajstatic void tsec_start_locked(struct ifnet *ifp); 92176774Srajstatic void tsec_stop(struct tsec_softc *sc); 93182189Srajstatic void tsec_tick(void *arg); 94182189Srajstatic void tsec_watchdog(struct tsec_softc *sc); 95188711Srajstatic void tsec_add_sysctls(struct tsec_softc *sc); 96188711Srajstatic int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97188711Srajstatic int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98188711Srajstatic void tsec_set_rxic(struct tsec_softc *sc); 99188711Srajstatic void tsec_set_txic(struct tsec_softc *sc); 100188711Srajstatic void tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101188711Srajstatic void tsec_transmit_intr_locked(struct tsec_softc *sc); 102188711Srajstatic void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103188711Srajstatic void tsec_offload_setup(struct tsec_softc *sc); 104188711Srajstatic void tsec_offload_process_frame(struct tsec_softc *sc, 105188711Sraj struct mbuf *m); 106188711Srajstatic void tsec_setup_multicast(struct tsec_softc *sc); 107188711Srajstatic int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108176774Sraj 109182189Srajstruct tsec_softc *tsec0_sc = NULL; /* XXX ugly hack! */ 110176774Sraj 111182189Srajdevclass_t tsec_devclass; 112182189SrajDRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 113182189SrajMODULE_DEPEND(tsec, ether, 1, 1, 1); 114182189SrajMODULE_DEPEND(tsec, miibus, 1, 1, 1); 115176774Sraj 116182189Srajint 117182189Srajtsec_attach(struct tsec_softc *sc) 118182189Sraj{ 119182189Sraj uint8_t hwaddr[ETHER_ADDR_LEN]; 120182189Sraj struct ifnet *ifp; 121182189Sraj bus_dmamap_t *map_ptr; 122182189Sraj bus_dmamap_t **map_pptr; 123182189Sraj int error = 0; 124182189Sraj int i; 125176774Sraj 126182189Sraj /* Reset all TSEC counters */ 127182189Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 128176774Sraj 129182189Sraj /* Stop DMA engine if enabled by firmware */ 130182189Sraj tsec_dma_ctl(sc, 0); 131176774Sraj 132182189Sraj /* Reset MAC */ 133182189Sraj tsec_reset_mac(sc); 134176774Sraj 135182189Sraj /* Disable interrupts for now */ 136182189Sraj tsec_intrs_ctl(sc, 0); 137176774Sraj 138188711Sraj /* Configure defaults for interrupts coalescing */ 139188711Sraj sc->rx_ic_time = 768; 140188711Sraj sc->rx_ic_count = 16; 141188711Sraj sc->tx_ic_time = 768; 142188711Sraj sc->tx_ic_count = 16; 143188711Sraj tsec_set_rxic(sc); 144188711Sraj tsec_set_txic(sc); 145188711Sraj tsec_add_sysctls(sc); 146188711Sraj 147182189Sraj /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 148188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 149188711Sraj &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 150182189Sraj (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 151188711Sraj 152182189Sraj if (error) { 153182189Sraj tsec_detach(sc); 154182189Sraj return (ENXIO); 155182189Sraj } 156176774Sraj 157182189Sraj /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 158188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 159188711Sraj &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 160182189Sraj (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 161182189Sraj if (error) { 162182189Sraj tsec_detach(sc); 163182189Sraj return (ENXIO); 164182189Sraj } 165176774Sraj 166182189Sraj /* Allocate a busdma tag for TX mbufs. */ 167182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 168182189Sraj TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 169182189Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 170182189Sraj BUS_SPACE_MAXADDR, /* highaddr */ 171182189Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 172182189Sraj MCLBYTES * (TSEC_TX_NUM_DESC - 1),/* maxsize */ 173182189Sraj TSEC_TX_NUM_DESC - 1, /* nsegments */ 174182189Sraj MCLBYTES, 0, /* maxsegsz, flags */ 175182189Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 176182189Sraj &sc->tsec_tx_mtag); /* dmat */ 177182189Sraj if (error) { 178182189Sraj device_printf(sc->dev, "failed to allocate busdma tag(tx mbufs)\n"); 179182189Sraj tsec_detach(sc); 180182189Sraj return (ENXIO); 181182189Sraj } 182182189Sraj 183182189Sraj /* Allocate a busdma tag for RX mbufs. */ 184182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 185182189Sraj TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 186182189Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 187182189Sraj BUS_SPACE_MAXADDR, /* highaddr */ 188182189Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 189182189Sraj MCLBYTES, /* maxsize */ 190182189Sraj 1, /* nsegments */ 191182189Sraj MCLBYTES, 0, /* maxsegsz, flags */ 192182189Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 193182189Sraj &sc->tsec_rx_mtag); /* dmat */ 194182189Sraj if (error) { 195182189Sraj device_printf(sc->dev, "failed to allocate busdma tag(rx mbufs)\n"); 196182189Sraj tsec_detach(sc); 197182189Sraj return (ENXIO); 198182189Sraj } 199182189Sraj 200182189Sraj /* Create TX busdma maps */ 201182189Sraj map_ptr = sc->tx_map_data; 202182189Sraj map_pptr = sc->tx_map_unused_data; 203182189Sraj 204182189Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 205182189Sraj map_pptr[i] = &map_ptr[i]; 206182189Sraj error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 207182189Sraj if (error) { 208182189Sraj device_printf(sc->dev, "failed to init TX ring\n"); 209182189Sraj tsec_detach(sc); 210182189Sraj return (ENXIO); 211182189Sraj } 212182189Sraj } 213182189Sraj 214182189Sraj /* Create RX busdma maps and zero mbuf handlers */ 215182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 216182189Sraj error = bus_dmamap_create(sc->tsec_rx_mtag, 0, &sc->rx_data[i].map); 217182189Sraj if (error) { 218182189Sraj device_printf(sc->dev, "failed to init RX ring\n"); 219182189Sraj tsec_detach(sc); 220182189Sraj return (ENXIO); 221182189Sraj } 222182189Sraj sc->rx_data[i].mbuf = NULL; 223182189Sraj } 224182189Sraj 225182189Sraj /* Create mbufs for RX buffers */ 226182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 227182189Sraj error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 228182189Sraj &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 229182189Sraj if (error) { 230182189Sraj device_printf(sc->dev, "can't load rx DMA map %d, error = " 231182189Sraj "%d\n", i, error); 232182189Sraj tsec_detach(sc); 233182189Sraj return (error); 234182189Sraj } 235182189Sraj } 236182189Sraj 237182189Sraj /* Create network interface for upper layers */ 238182189Sraj ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 239182189Sraj if (ifp == NULL) { 240182189Sraj device_printf(sc->dev, "if_alloc() failed\n"); 241182189Sraj tsec_detach(sc); 242182189Sraj return (ENOMEM); 243182189Sraj } 244182189Sraj 245182189Sraj ifp->if_softc = sc; 246182189Sraj if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 247182189Sraj ifp->if_mtu = ETHERMTU; 248188711Sraj ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 249182189Sraj ifp->if_init = tsec_init; 250182189Sraj ifp->if_start = tsec_start; 251182189Sraj ifp->if_ioctl = tsec_ioctl; 252182189Sraj 253182189Sraj IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 254182189Sraj ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 255182189Sraj IFQ_SET_READY(&ifp->if_snd); 256182189Sraj 257188711Sraj ifp->if_capabilities = IFCAP_VLAN_MTU; 258188711Sraj if (sc->is_etsec) 259188711Sraj ifp->if_capabilities |= IFCAP_HWCSUM; 260188711Sraj 261182189Sraj ifp->if_capenable = ifp->if_capabilities; 262182189Sraj 263188711Sraj#ifdef DEVICE_POLLING 264188711Sraj /* Advertise that polling is supported */ 265188711Sraj ifp->if_capabilities |= IFCAP_POLLING; 266188711Sraj#endif 267188711Sraj 268182189Sraj /* Probe PHY(s) */ 269182189Sraj error = mii_phy_probe(sc->dev, &sc->tsec_miibus, tsec_ifmedia_upd, 270182189Sraj tsec_ifmedia_sts); 271182189Sraj if (error) { 272182189Sraj device_printf(sc->dev, "MII failed to find PHY!\n"); 273182189Sraj if_free(ifp); 274182189Sraj sc->tsec_ifp = NULL; 275182189Sraj tsec_detach(sc); 276182189Sraj return (error); 277182189Sraj } 278182189Sraj sc->tsec_mii = device_get_softc(sc->tsec_miibus); 279182189Sraj 280182189Sraj /* Set MAC address */ 281182189Sraj tsec_get_hwaddr(sc, hwaddr); 282182189Sraj ether_ifattach(ifp, hwaddr); 283182189Sraj 284182189Sraj return (0); 285182189Sraj} 286182189Sraj 287182189Srajint 288182189Srajtsec_detach(struct tsec_softc *sc) 289176774Sraj{ 290176774Sraj 291188711Sraj#ifdef DEVICE_POLLING 292188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 293188711Sraj ether_poll_deregister(sc->tsec_ifp); 294188711Sraj#endif 295188711Sraj 296182189Sraj /* Stop TSEC controller and free TX queue */ 297182189Sraj if (sc->sc_rres && sc->tsec_ifp) 298182189Sraj tsec_shutdown(sc->dev); 299182189Sraj 300182189Sraj /* Detach network interface */ 301182189Sraj if (sc->tsec_ifp) { 302182189Sraj ether_ifdetach(sc->tsec_ifp); 303182189Sraj if_free(sc->tsec_ifp); 304182189Sraj sc->tsec_ifp = NULL; 305177110Sraj } 306177110Sraj 307182189Sraj /* Free DMA resources */ 308182189Sraj tsec_free_dma(sc); 309176774Sraj 310182189Sraj return (0); 311176774Sraj} 312176774Sraj 313182189Srajvoid 314182189Srajtsec_shutdown(device_t dev) 315182189Sraj{ 316182189Sraj struct tsec_softc *sc; 317182189Sraj 318182189Sraj sc = device_get_softc(dev); 319182189Sraj 320182189Sraj TSEC_GLOBAL_LOCK(sc); 321182189Sraj tsec_stop(sc); 322182189Sraj TSEC_GLOBAL_UNLOCK(sc); 323182189Sraj} 324182189Sraj 325182189Srajint 326182189Srajtsec_suspend(device_t dev) 327182189Sraj{ 328182189Sraj 329182189Sraj /* TODO not implemented! */ 330182189Sraj return (0); 331182189Sraj} 332182189Sraj 333182189Srajint 334182189Srajtsec_resume(device_t dev) 335182189Sraj{ 336182189Sraj 337182189Sraj /* TODO not implemented! */ 338182189Sraj return (0); 339182189Sraj} 340182189Sraj 341176774Srajstatic void 342176774Srajtsec_init(void *xsc) 343176774Sraj{ 344176774Sraj struct tsec_softc *sc = xsc; 345176774Sraj 346176774Sraj TSEC_GLOBAL_LOCK(sc); 347176774Sraj tsec_init_locked(sc); 348176774Sraj TSEC_GLOBAL_UNLOCK(sc); 349176774Sraj} 350176774Sraj 351176774Srajstatic void 352176774Srajtsec_init_locked(struct tsec_softc *sc) 353176774Sraj{ 354176774Sraj struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 355176774Sraj struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 356176774Sraj struct ifnet *ifp = sc->tsec_ifp; 357176774Sraj uint32_t timeout; 358176774Sraj uint32_t val; 359176774Sraj uint32_t i; 360176774Sraj 361176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 362176774Sraj tsec_stop(sc); 363176774Sraj 364176774Sraj /* 365176774Sraj * These steps are according to the MPC8555E PowerQUICCIII RM: 366176774Sraj * 14.7 Initialization/Application Information 367176774Sraj */ 368176774Sraj 369176774Sraj /* Step 1: soft reset MAC */ 370176774Sraj tsec_reset_mac(sc); 371176774Sraj 372176774Sraj /* Step 2: Initialize MACCFG2 */ 373176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, 374176774Sraj TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 375176774Sraj TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 376176774Sraj TSEC_MACCFG2_GMII | /* I/F Mode bit */ 377176774Sraj TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 378176774Sraj ); 379176774Sraj 380176774Sraj /* Step 3: Initialize ECNTRL 381176774Sraj * While the documentation states that R100M is ignored if RPM is 382176774Sraj * not set, it does seem to be needed to get the orange boxes to 383176774Sraj * work (which have a Marvell 88E1111 PHY). Go figure. 384176774Sraj */ 385176774Sraj 386176774Sraj /* 387176774Sraj * XXX kludge - use circumstancial evidence to program ECNTRL 388176774Sraj * correctly. Ideally we need some board information to guide 389176774Sraj * us here. 390176774Sraj */ 391176774Sraj i = TSEC_READ(sc, TSEC_REG_ID2); 392176774Sraj val = (i & 0xffff) 393176774Sraj ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 394176774Sraj : TSEC_ECNTRL_R100M; /* Orange + CDS */ 395176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 396176774Sraj 397176774Sraj /* Step 4: Initialize MAC station address */ 398176774Sraj tsec_set_mac_address(sc); 399176774Sraj 400176774Sraj /* 401176774Sraj * Step 5: Assign a Physical address to the TBI so as to not conflict 402176774Sraj * with the external PHY physical address 403176774Sraj */ 404176774Sraj TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 405176774Sraj 406176774Sraj /* Step 6: Reset the management interface */ 407176774Sraj TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 408176774Sraj 409176774Sraj /* Step 7: Setup the MII Mgmt clock speed */ 410176774Sraj TSEC_WRITE(tsec0_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 411176774Sraj 412176774Sraj /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 413176774Sraj timeout = TSEC_READ_RETRY; 414176774Sraj while (--timeout && (TSEC_READ(tsec0_sc, TSEC_REG_MIIMIND) & 415176774Sraj TSEC_MIIMIND_BUSY)) 416176774Sraj DELAY(TSEC_READ_DELAY); 417176774Sraj if (timeout == 0) { 418176774Sraj if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 419176774Sraj return; 420176774Sraj } 421176774Sraj 422176774Sraj /* Step 9: Setup the MII Mgmt */ 423176774Sraj mii_mediachg(sc->tsec_mii); 424176774Sraj 425176774Sraj /* Step 10: Clear IEVENT register */ 426176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 427176774Sraj 428188711Sraj /* Step 11: Enable interrupts */ 429188711Sraj#ifdef DEVICE_POLLING 430188711Sraj /* 431188711Sraj * ...only if polling is not turned on. Disable interrupts explicitly 432188711Sraj * if polling is enabled. 433188711Sraj */ 434188711Sraj if (ifp->if_capenable & IFCAP_POLLING ) 435188711Sraj tsec_intrs_ctl(sc, 0); 436188711Sraj else 437188711Sraj#endif /* DEVICE_POLLING */ 438176774Sraj tsec_intrs_ctl(sc, 1); 439176774Sraj 440176774Sraj /* Step 12: Initialize IADDRn */ 441176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 442176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 443176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 444176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 445176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 446176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 447176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 448176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 449176774Sraj 450176774Sraj /* Step 13: Initialize GADDRn */ 451176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 452176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 453176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 454176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 455176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 456176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 457176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 458176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 459176774Sraj 460176774Sraj /* Step 14: Initialize RCTRL */ 461176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 462176774Sraj 463176774Sraj /* Step 15: Initialize DMACTRL */ 464176774Sraj tsec_dma_ctl(sc, 1); 465176774Sraj 466176774Sraj /* Step 16: Initialize FIFO_PAUSE_CTRL */ 467176774Sraj TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 468176774Sraj 469176774Sraj /* 470176774Sraj * Step 17: Initialize transmit/receive descriptor rings. 471176774Sraj * Initialize TBASE and RBASE. 472176774Sraj */ 473176774Sraj TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 474176774Sraj TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 475176774Sraj 476176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 477176774Sraj tx_desc[i].bufptr = 0; 478176774Sraj tx_desc[i].length = 0; 479182189Sraj tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? TSEC_TXBD_W : 0); 480176774Sraj } 481182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 482182189Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 483176774Sraj 484176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 485176774Sraj rx_desc[i].bufptr = sc->rx_data[i].paddr; 486176774Sraj rx_desc[i].length = 0; 487176774Sraj rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 488182189Sraj ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 489176774Sraj } 490188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 491188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 492176774Sraj 493188711Sraj /* Step 18: Initialize the maximum receive buffer length */ 494188711Sraj TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 495176774Sraj 496188711Sraj /* Step 19: Configure ethernet frame sizes */ 497188711Sraj TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 498188711Sraj tsec_set_mtu(sc, ifp->if_mtu); 499188711Sraj 500188711Sraj /* Step 20: Enable Rx and RxBD sdata snooping */ 501176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 502176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 503176774Sraj 504188711Sraj /* Step 21: Reset collision counters in hardware */ 505176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 506176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 507176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 508176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 509176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 510176774Sraj 511188711Sraj /* Step 22: Mask all CAM interrupts */ 512176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 513176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 514176774Sraj 515188711Sraj /* Step 23: Enable Rx and Tx */ 516176774Sraj val = TSEC_READ(sc, TSEC_REG_MACCFG1); 517176774Sraj val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 518176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 519176774Sraj 520188711Sraj /* Step 24: Reset TSEC counters for Tx and Rx rings */ 521176774Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 522176774Sraj 523188711Sraj /* Step 25: Setup TCP/IP Off-Load engine */ 524188711Sraj if (sc->is_etsec) 525188711Sraj tsec_offload_setup(sc); 526188711Sraj 527188711Sraj /* Step 26: Setup multicast filters */ 528188711Sraj tsec_setup_multicast(sc); 529188711Sraj 530188711Sraj /* Step 27: Activate network interface */ 531176774Sraj ifp->if_drv_flags |= IFF_DRV_RUNNING; 532176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 533176774Sraj sc->tsec_if_flags = ifp->if_flags; 534182187Sraj sc->tsec_watchdog = 0; 535177111Sraj 536177111Sraj /* Schedule watchdog timeout */ 537182187Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 538176774Sraj} 539176774Sraj 540176774Srajstatic void 541176774Srajtsec_set_mac_address(struct tsec_softc *sc) 542176774Sraj{ 543176774Sraj uint32_t macbuf[2] = { 0, 0 }; 544176774Sraj char *macbufp; 545176774Sraj char *curmac; 546182189Sraj int i; 547176774Sraj 548176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 549176774Sraj 550176774Sraj KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 551182189Sraj ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, sizeof(macbuf))); 552176774Sraj 553176774Sraj macbufp = (char *)macbuf; 554176774Sraj curmac = (char *)IF_LLADDR(sc->tsec_ifp); 555176774Sraj 556176774Sraj /* Correct order of MAC address bytes */ 557176774Sraj for (i = 1; i <= ETHER_ADDR_LEN; i++) 558176774Sraj macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 559176774Sraj 560176774Sraj /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 561176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 562176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 563176774Sraj} 564176774Sraj 565176774Sraj/* 566176774Sraj * DMA control function, if argument state is: 567176774Sraj * 0 - DMA engine will be disabled 568176774Sraj * 1 - DMA engine will be enabled 569176774Sraj */ 570176774Srajstatic void 571176774Srajtsec_dma_ctl(struct tsec_softc *sc, int state) 572176774Sraj{ 573176774Sraj device_t dev; 574176774Sraj uint32_t dma_flags; 575176774Sraj uint32_t timeout; 576176774Sraj 577176774Sraj dev = sc->dev; 578176774Sraj 579176774Sraj dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 580176774Sraj 581176774Sraj switch (state) { 582176774Sraj case 0: 583176774Sraj /* Temporarily clear stop graceful stop bits. */ 584176774Sraj tsec_dma_ctl(sc, 1000); 585176774Sraj 586176774Sraj /* Set it again */ 587176774Sraj dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 588176774Sraj break; 589176774Sraj case 1000: 590176774Sraj case 1: 591176774Sraj /* Set write with response (WWR), wait (WOP) and snoop bits */ 592176774Sraj dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 593176774Sraj DMACTRL_WWR | DMACTRL_WOP); 594176774Sraj 595176774Sraj /* Clear graceful stop bits */ 596176774Sraj dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 597176774Sraj break; 598176774Sraj default: 599176774Sraj device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 600176774Sraj state); 601176774Sraj } 602176774Sraj 603176774Sraj TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 604176774Sraj 605176774Sraj switch (state) { 606176774Sraj case 0: 607176774Sraj /* Wait for DMA stop */ 608176774Sraj timeout = TSEC_READ_RETRY; 609176774Sraj while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 610176774Sraj (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 611176774Sraj DELAY(TSEC_READ_DELAY); 612176774Sraj 613176774Sraj if (timeout == 0) 614176774Sraj device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 615176774Sraj break; 616176774Sraj case 1: 617176774Sraj /* Restart transmission function */ 618176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 619176774Sraj } 620176774Sraj} 621176774Sraj 622176774Sraj/* 623176774Sraj * Interrupts control function, if argument state is: 624176774Sraj * 0 - all TSEC interrupts will be masked 625176774Sraj * 1 - all TSEC interrupts will be unmasked 626176774Sraj */ 627176774Srajstatic void 628176774Srajtsec_intrs_ctl(struct tsec_softc *sc, int state) 629176774Sraj{ 630176774Sraj device_t dev; 631176774Sraj 632176774Sraj dev = sc->dev; 633176774Sraj 634176774Sraj switch (state) { 635176774Sraj case 0: 636176774Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 637176774Sraj break; 638176774Sraj case 1: 639182189Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | TSEC_IMASK_RXCEN | 640182189Sraj TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | TSEC_IMASK_BTEN | 641182189Sraj TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | TSEC_IMASK_TXFEN | 642182189Sraj TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 643176774Sraj break; 644176774Sraj default: 645176774Sraj device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 646176774Sraj state); 647176774Sraj } 648176774Sraj} 649176774Sraj 650176774Srajstatic void 651176774Srajtsec_reset_mac(struct tsec_softc *sc) 652176774Sraj{ 653176774Sraj uint32_t maccfg1_flags; 654176774Sraj 655176774Sraj /* Set soft reset bit */ 656176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 657176774Sraj maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 658176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 659176774Sraj 660176774Sraj /* Clear soft reset bit */ 661176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 662176774Sraj maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 663176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 664176774Sraj} 665176774Sraj 666176774Srajstatic void 667177111Srajtsec_watchdog(struct tsec_softc *sc) 668176774Sraj{ 669177111Sraj struct ifnet *ifp; 670176774Sraj 671177111Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 672176774Sraj 673182187Sraj if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 674177111Sraj return; 675177111Sraj 676177111Sraj ifp = sc->tsec_ifp; 677176774Sraj ifp->if_oerrors++; 678176774Sraj if_printf(ifp, "watchdog timeout\n"); 679176774Sraj 680176774Sraj tsec_stop(sc); 681176774Sraj tsec_init_locked(sc); 682176774Sraj} 683176774Sraj 684176774Srajstatic void 685176774Srajtsec_start(struct ifnet *ifp) 686176774Sraj{ 687176774Sraj struct tsec_softc *sc = ifp->if_softc; 688176774Sraj 689176774Sraj TSEC_TRANSMIT_LOCK(sc); 690176774Sraj tsec_start_locked(ifp); 691176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 692176774Sraj} 693176774Sraj 694176774Srajstatic void 695176774Srajtsec_start_locked(struct ifnet *ifp) 696176774Sraj{ 697176774Sraj struct tsec_softc *sc; 698188711Sraj struct mbuf *m0, *mtmp; 699188711Sraj struct tsec_tx_fcb *tx_fcb; 700176774Sraj unsigned int queued = 0; 701188711Sraj int csum_flags, fcb_inserted = 0; 702176774Sraj 703176774Sraj sc = ifp->if_softc; 704176774Sraj 705176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 706176774Sraj 707176774Sraj if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 708176774Sraj IFF_DRV_RUNNING) 709176774Sraj return; 710176774Sraj 711176774Sraj if (sc->tsec_link == 0) 712176774Sraj return; 713176774Sraj 714182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, BUS_DMASYNC_POSTREAD | 715182189Sraj BUS_DMASYNC_POSTWRITE); 716176774Sraj 717176774Sraj for (;;) { 718176774Sraj /* Get packet from the queue */ 719176774Sraj IF_DEQUEUE(&ifp->if_snd, m0); 720176774Sraj if (m0 == NULL) 721176774Sraj break; 722176774Sraj 723188711Sraj /* Insert TCP/IP Off-load frame control block */ 724188711Sraj csum_flags = m0->m_pkthdr.csum_flags; 725188711Sraj if (csum_flags) { 726188711Sraj 727188711Sraj M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_DONTWAIT); 728188711Sraj if (m0 == NULL) 729188711Sraj break; 730188711Sraj 731188711Sraj tx_fcb = mtod(m0, struct tsec_tx_fcb *); 732188711Sraj tx_fcb->flags = 0; 733188711Sraj tx_fcb->l3_offset = ETHER_HDR_LEN; 734188711Sraj tx_fcb->l4_offset = sizeof(struct ip); 735188711Sraj 736188711Sraj if (csum_flags & CSUM_IP) 737188711Sraj tx_fcb->flags |= TSEC_TX_FCB_IP4 | 738188711Sraj TSEC_TX_FCB_CSUM_IP; 739188711Sraj 740188711Sraj if (csum_flags & CSUM_TCP) 741188711Sraj tx_fcb->flags |= TSEC_TX_FCB_TCP | 742188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 743188711Sraj 744188711Sraj if (csum_flags & CSUM_UDP) 745188711Sraj tx_fcb->flags |= TSEC_TX_FCB_UDP | 746188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 747188711Sraj 748188711Sraj fcb_inserted = 1; 749188711Sraj } 750188711Sraj 751176774Sraj mtmp = m_defrag(m0, M_DONTWAIT); 752176774Sraj if (mtmp) 753176774Sraj m0 = mtmp; 754176774Sraj 755188711Sraj if (tsec_encap(sc, m0, fcb_inserted)) { 756176774Sraj IF_PREPEND(&ifp->if_snd, m0); 757176774Sraj ifp->if_drv_flags |= IFF_DRV_OACTIVE; 758176774Sraj break; 759176774Sraj } 760176774Sraj queued++; 761176774Sraj BPF_MTAP(ifp, m0); 762176774Sraj } 763182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, BUS_DMASYNC_PREREAD | 764182189Sraj BUS_DMASYNC_PREWRITE); 765176774Sraj 766176774Sraj if (queued) { 767176774Sraj /* Enable transmitter and watchdog timer */ 768176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 769182187Sraj sc->tsec_watchdog = 5; 770176774Sraj } 771176774Sraj} 772176774Sraj 773176774Srajstatic int 774188711Srajtsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 775176774Sraj{ 776176774Sraj struct tsec_desc *tx_desc = NULL; 777176774Sraj struct ifnet *ifp; 778176774Sraj bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 779176774Sraj bus_dmamap_t *mapp; 780188711Sraj int csum_flag = 0, error, seg, nsegs; 781176774Sraj 782176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 783176774Sraj 784176774Sraj ifp = sc->tsec_ifp; 785176774Sraj 786176774Sraj if (TSEC_FREE_TX_DESC(sc) == 0) { 787176774Sraj /* No free descriptors */ 788176774Sraj return (-1); 789176774Sraj } 790176774Sraj 791176774Sraj /* Fetch unused map */ 792176774Sraj mapp = TSEC_ALLOC_TX_MAP(sc); 793176774Sraj 794176774Sraj /* Create mapping in DMA memory */ 795176774Sraj error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 796182189Sraj *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 797176774Sraj if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 798176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 799176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 800176774Sraj return ((error != 0) ? error : -1); 801176774Sraj } 802176774Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 803176774Sraj 804176774Sraj if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 805176774Sraj if_printf(ifp, "TX buffer has %d segments\n", nsegs); 806176774Sraj 807188711Sraj if (fcb_inserted) 808188711Sraj csum_flag = TSEC_TXBD_TOE; 809188711Sraj 810176774Sraj /* Everything is ok, now we can send buffers */ 811176774Sraj for (seg = 0; seg < nsegs; seg++) { 812176774Sraj tx_desc = TSEC_GET_CUR_TX_DESC(sc); 813176774Sraj 814176774Sraj tx_desc->length = segs[seg].ds_len; 815176774Sraj tx_desc->bufptr = segs[seg].ds_addr; 816176774Sraj 817188711Sraj /* 818188711Sraj * Set flags: 819188711Sraj * - wrap 820188711Sraj * - checksum 821188711Sraj * - ready to send 822188711Sraj * - transmit the CRC sequence after the last data byte 823188711Sraj * - interrupt after the last buffer 824188711Sraj */ 825176774Sraj tx_desc->flags = 826188711Sraj (tx_desc->flags & TSEC_TXBD_W) | 827188711Sraj ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 828188711Sraj ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 829176774Sraj } 830176774Sraj 831176774Sraj /* Save mbuf and DMA mapping for release at later stage */ 832176774Sraj TSEC_PUT_TX_MBUF(sc, m0); 833176774Sraj TSEC_PUT_TX_MAP(sc, mapp); 834176774Sraj 835176774Sraj return (0); 836176774Sraj} 837176774Sraj 838176774Srajstatic void 839176774Srajtsec_setfilter(struct tsec_softc *sc) 840176774Sraj{ 841176774Sraj struct ifnet *ifp; 842176774Sraj uint32_t flags; 843176774Sraj 844176774Sraj ifp = sc->tsec_ifp; 845176774Sraj flags = TSEC_READ(sc, TSEC_REG_RCTRL); 846176774Sraj 847176774Sraj /* Promiscuous mode */ 848176774Sraj if (ifp->if_flags & IFF_PROMISC) 849176774Sraj flags |= TSEC_RCTRL_PROM; 850176774Sraj else 851176774Sraj flags &= ~TSEC_RCTRL_PROM; 852176774Sraj 853176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 854176774Sraj} 855176774Sraj 856188711Sraj#ifdef DEVICE_POLLING 857188711Srajstatic poll_handler_t tsec_poll; 858188711Sraj 859188711Srajstatic void 860188711Srajtsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 861188711Sraj{ 862188711Sraj uint32_t ie; 863188711Sraj struct tsec_softc *sc = ifp->if_softc; 864188711Sraj 865188711Sraj TSEC_GLOBAL_LOCK(sc); 866188711Sraj if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 867188711Sraj TSEC_GLOBAL_UNLOCK(sc); 868188711Sraj return; 869188711Sraj } 870188711Sraj 871188711Sraj if (cmd == POLL_AND_CHECK_STATUS) { 872188711Sraj ie = TSEC_READ(sc, TSEC_REG_IEVENT); 873188711Sraj 874188711Sraj /* Clear all events reported */ 875188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 876188711Sraj tsec_error_intr_locked(sc, count); 877188711Sraj } 878188711Sraj 879188711Sraj tsec_transmit_intr_locked(sc); 880188711Sraj 881188711Sraj TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 882188711Sraj 883188711Sraj tsec_receive_intr_locked(sc, count); 884188711Sraj 885188711Sraj TSEC_RECEIVE_UNLOCK(sc); 886188711Sraj} 887188711Sraj#endif /* DEVICE_POLLING */ 888188711Sraj 889176774Srajstatic int 890176774Srajtsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 891176774Sraj{ 892176774Sraj struct tsec_softc *sc = ifp->if_softc; 893176774Sraj struct ifreq *ifr = (struct ifreq *)data; 894176774Sraj device_t dev; 895188711Sraj int mask, error = 0; 896176774Sraj 897176774Sraj dev = sc->dev; 898176774Sraj 899176774Sraj switch (command) { 900188711Sraj case SIOCSIFMTU: 901188711Sraj TSEC_GLOBAL_LOCK(sc); 902188711Sraj if (tsec_set_mtu(sc, ifr->ifr_mtu)) 903188711Sraj ifp->if_mtu = ifr->ifr_mtu; 904188711Sraj else 905188711Sraj error = EINVAL; 906188711Sraj TSEC_GLOBAL_UNLOCK(sc); 907188711Sraj break; 908176774Sraj case SIOCSIFFLAGS: 909176774Sraj TSEC_GLOBAL_LOCK(sc); 910176774Sraj if (ifp->if_flags & IFF_UP) { 911176774Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 912188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 913188711Sraj IFF_PROMISC) 914176774Sraj tsec_setfilter(sc); 915188711Sraj 916188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 917188711Sraj IFF_ALLMULTI) 918188711Sraj tsec_setup_multicast(sc); 919176774Sraj } else 920176774Sraj tsec_init_locked(sc); 921182189Sraj } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 922182189Sraj tsec_stop(sc); 923182189Sraj 924176774Sraj sc->tsec_if_flags = ifp->if_flags; 925176774Sraj TSEC_GLOBAL_UNLOCK(sc); 926176774Sraj break; 927188711Sraj case SIOCADDMULTI: 928188711Sraj case SIOCDELMULTI: 929188711Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 930188711Sraj TSEC_GLOBAL_LOCK(sc); 931188711Sraj tsec_setup_multicast(sc); 932188711Sraj TSEC_GLOBAL_UNLOCK(sc); 933188711Sraj } 934176774Sraj case SIOCGIFMEDIA: 935176774Sraj case SIOCSIFMEDIA: 936188711Sraj error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 937188711Sraj command); 938176774Sraj break; 939188711Sraj case SIOCSIFCAP: 940188711Sraj mask = ifp->if_capenable ^ ifr->ifr_reqcap; 941188711Sraj if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 942188711Sraj TSEC_GLOBAL_LOCK(sc); 943188711Sraj ifp->if_capenable &= ~IFCAP_HWCSUM; 944188711Sraj ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 945188711Sraj tsec_offload_setup(sc); 946188711Sraj TSEC_GLOBAL_UNLOCK(sc); 947188711Sraj } 948188711Sraj#ifdef DEVICE_POLLING 949188711Sraj if (mask & IFCAP_POLLING) { 950188711Sraj if (ifr->ifr_reqcap & IFCAP_POLLING) { 951188711Sraj error = ether_poll_register(tsec_poll, ifp); 952188711Sraj if (error) 953188711Sraj return (error); 954188711Sraj 955188711Sraj TSEC_GLOBAL_LOCK(sc); 956188711Sraj /* Disable interrupts */ 957188711Sraj tsec_intrs_ctl(sc, 0); 958188711Sraj ifp->if_capenable |= IFCAP_POLLING; 959188711Sraj TSEC_GLOBAL_UNLOCK(sc); 960188711Sraj } else { 961188711Sraj error = ether_poll_deregister(ifp); 962188711Sraj TSEC_GLOBAL_LOCK(sc); 963188711Sraj /* Enable interrupts */ 964188711Sraj tsec_intrs_ctl(sc, 1); 965188711Sraj ifp->if_capenable &= ~IFCAP_POLLING; 966188711Sraj TSEC_GLOBAL_UNLOCK(sc); 967188711Sraj } 968188711Sraj } 969188711Sraj#endif 970188711Sraj break; 971188711Sraj 972176774Sraj default: 973176774Sraj error = ether_ioctl(ifp, command, data); 974176774Sraj } 975176774Sraj 976176774Sraj /* Flush buffers if not empty */ 977176774Sraj if (ifp->if_flags & IFF_UP) 978176774Sraj tsec_start(ifp); 979176774Sraj return (error); 980176774Sraj} 981176774Sraj 982176774Srajstatic int 983176774Srajtsec_ifmedia_upd(struct ifnet *ifp) 984176774Sraj{ 985176774Sraj struct tsec_softc *sc = ifp->if_softc; 986176774Sraj struct mii_data *mii; 987176774Sraj 988176774Sraj TSEC_TRANSMIT_LOCK(sc); 989176774Sraj 990176774Sraj mii = sc->tsec_mii; 991176774Sraj mii_mediachg(mii); 992176774Sraj 993176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 994176774Sraj return (0); 995176774Sraj} 996176774Sraj 997176774Srajstatic void 998176774Srajtsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 999176774Sraj{ 1000176774Sraj struct tsec_softc *sc = ifp->if_softc; 1001176774Sraj struct mii_data *mii; 1002176774Sraj 1003176774Sraj TSEC_TRANSMIT_LOCK(sc); 1004176774Sraj 1005176774Sraj mii = sc->tsec_mii; 1006176774Sraj mii_pollstat(mii); 1007176774Sraj 1008176774Sraj ifmr->ifm_active = mii->mii_media_active; 1009176774Sraj ifmr->ifm_status = mii->mii_media_status; 1010176774Sraj 1011176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 1012176774Sraj} 1013176774Sraj 1014176774Srajstatic int 1015176774Srajtsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1016182189Sraj uint32_t *paddr) 1017176774Sraj{ 1018176774Sraj struct mbuf *new_mbuf; 1019176774Sraj bus_dma_segment_t seg[1]; 1020188711Sraj int error, nsegs; 1021176774Sraj 1022176774Sraj KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1023176774Sraj 1024188711Sraj new_mbuf = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1025176774Sraj if (new_mbuf == NULL) 1026176774Sraj return (ENOBUFS); 1027176774Sraj new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1028176774Sraj 1029176774Sraj if (*mbufp) { 1030176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1031176774Sraj bus_dmamap_unload(tag, map); 1032176774Sraj } 1033176774Sraj 1034176774Sraj error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1035182189Sraj BUS_DMA_NOWAIT); 1036176774Sraj KASSERT(nsegs == 1, ("Too many segments returned!")); 1037176774Sraj if (nsegs != 1 || error) 1038176774Sraj panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1039176774Sraj 1040176774Sraj#if 0 1041176774Sraj if (error) { 1042176774Sraj printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1043176774Sraj error); 1044176774Sraj m_freem(new_mbuf); 1045176774Sraj return (ENOBUFS); 1046176774Sraj } 1047176774Sraj#endif 1048176774Sraj 1049176774Sraj#if 0 1050176774Sraj KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1051176774Sraj ("Wrong alignment of RX buffer!")); 1052176774Sraj#endif 1053176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1054176774Sraj 1055176774Sraj (*mbufp) = new_mbuf; 1056176774Sraj (*paddr) = seg->ds_addr; 1057176774Sraj return (0); 1058176774Sraj} 1059176774Sraj 1060176774Srajstatic void 1061176774Srajtsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1062176774Sraj{ 1063176774Sraj u_int32_t *paddr; 1064176774Sraj 1065176774Sraj KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1066176774Sraj paddr = arg; 1067176774Sraj *paddr = segs->ds_addr; 1068176774Sraj} 1069176774Sraj 1070176774Srajstatic int 1071176774Srajtsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1072176774Sraj bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1073176774Sraj{ 1074176774Sraj int error; 1075176774Sraj 1076176774Sraj /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1077176774Sraj error = bus_dma_tag_create(NULL, /* parent */ 1078176774Sraj PAGE_SIZE, 0, /* alignment, boundary */ 1079176774Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1080176774Sraj BUS_SPACE_MAXADDR, /* highaddr */ 1081176774Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 1082176774Sraj dsize, 1, /* maxsize, nsegments */ 1083176774Sraj dsize, 0, /* maxsegsz, flags */ 1084176774Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 1085176774Sraj dtag); /* dmat */ 1086176774Sraj 1087176774Sraj if (error) { 1088176774Sraj device_printf(dev, "failed to allocate busdma %s tag\n", dname); 1089176774Sraj (*vaddr) = NULL; 1090176774Sraj return (ENXIO); 1091176774Sraj } 1092176774Sraj 1093176774Sraj error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1094182189Sraj dmap); 1095176774Sraj if (error) { 1096176774Sraj device_printf(dev, "failed to allocate %s DMA safe memory\n", 1097182189Sraj dname); 1098176774Sraj bus_dma_tag_destroy(*dtag); 1099176774Sraj (*vaddr) = NULL; 1100176774Sraj return (ENXIO); 1101176774Sraj } 1102176774Sraj 1103176774Sraj error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, tsec_map_dma_addr, 1104176774Sraj raddr, BUS_DMA_NOWAIT); 1105176774Sraj if (error) { 1106176774Sraj device_printf(dev, "cannot get address of the %s descriptors\n", 1107176774Sraj dname); 1108176774Sraj bus_dmamem_free(*dtag, *vaddr, *dmap); 1109176774Sraj bus_dma_tag_destroy(*dtag); 1110176774Sraj (*vaddr) = NULL; 1111176774Sraj return (ENXIO); 1112176774Sraj } 1113176774Sraj 1114176774Sraj return (0); 1115176774Sraj} 1116176774Sraj 1117176774Srajstatic void 1118176774Srajtsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1119176774Sraj{ 1120176774Sraj 1121176774Sraj if (vaddr == NULL) 1122176774Sraj return; 1123176774Sraj 1124176774Sraj /* Unmap descriptors from DMA memory */ 1125176774Sraj bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1126176774Sraj bus_dmamap_unload(dtag, dmap); 1127176774Sraj 1128176774Sraj /* Free descriptors memory */ 1129176774Sraj bus_dmamem_free(dtag, vaddr, dmap); 1130176774Sraj 1131176774Sraj /* Destroy descriptors tag */ 1132176774Sraj bus_dma_tag_destroy(dtag); 1133176774Sraj} 1134176774Sraj 1135176774Srajstatic void 1136176774Srajtsec_free_dma(struct tsec_softc *sc) 1137176774Sraj{ 1138176774Sraj int i; 1139176774Sraj 1140176774Sraj /* Free TX maps */ 1141176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1142176774Sraj if (sc->tx_map_data[i] != NULL) 1143182189Sraj bus_dmamap_destroy(sc->tsec_tx_mtag, sc->tx_map_data[i]); 1144176774Sraj /* Destroy tag for Tx mbufs */ 1145176774Sraj bus_dma_tag_destroy(sc->tsec_tx_mtag); 1146176774Sraj 1147176774Sraj /* Free RX mbufs and maps */ 1148176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1149176774Sraj if (sc->rx_data[i].mbuf) { 1150176774Sraj /* Unload buffer from DMA */ 1151176774Sraj bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1152176774Sraj BUS_DMASYNC_POSTREAD); 1153176774Sraj bus_dmamap_unload(sc->tsec_rx_mtag, sc->rx_data[i].map); 1154176774Sraj 1155176774Sraj /* Free buffer */ 1156176774Sraj m_freem(sc->rx_data[i].mbuf); 1157176774Sraj } 1158176774Sraj /* Destroy map for this buffer */ 1159176774Sraj if (sc->rx_data[i].map != NULL) 1160176774Sraj bus_dmamap_destroy(sc->tsec_rx_mtag, 1161176774Sraj sc->rx_data[i].map); 1162176774Sraj } 1163176774Sraj /* Destroy tag for Rx mbufs */ 1164176774Sraj bus_dma_tag_destroy(sc->tsec_rx_mtag); 1165176774Sraj 1166176774Sraj /* Unload TX/RX descriptors */ 1167176774Sraj tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1168176774Sraj sc->tsec_tx_vaddr); 1169176774Sraj tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1170176774Sraj sc->tsec_rx_vaddr); 1171176774Sraj} 1172176774Sraj 1173176774Srajstatic void 1174176774Srajtsec_stop(struct tsec_softc *sc) 1175176774Sraj{ 1176176774Sraj struct ifnet *ifp; 1177176774Sraj struct mbuf *m0; 1178176774Sraj bus_dmamap_t *mapp; 1179176774Sraj uint32_t tmpval; 1180176774Sraj 1181176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1182176774Sraj 1183176774Sraj ifp = sc->tsec_ifp; 1184176774Sraj 1185182187Sraj /* Stop tick engine */ 1186182187Sraj callout_stop(&sc->tsec_callout); 1187176774Sraj 1188176774Sraj /* Disable interface and watchdog timer */ 1189176774Sraj ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1190182187Sraj sc->tsec_watchdog = 0; 1191176774Sraj 1192176774Sraj /* Disable all interrupts and stop DMA */ 1193176774Sraj tsec_intrs_ctl(sc, 0); 1194176774Sraj tsec_dma_ctl(sc, 0); 1195176774Sraj 1196176774Sraj /* Remove pending data from TX queue */ 1197176774Sraj while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1198176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1199176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1200176774Sraj 1201188711Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1202188711Sraj BUS_DMASYNC_POSTWRITE); 1203176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1204176774Sraj 1205176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1206176774Sraj m_freem(m0); 1207176774Sraj } 1208176774Sraj 1209188711Sraj /* Disable RX and TX */ 1210176774Sraj tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1211176774Sraj tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1212176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1213176774Sraj DELAY(10); 1214176774Sraj} 1215176774Sraj 1216188711Srajstatic void 1217188711Srajtsec_tick(void *arg) 1218176774Sraj{ 1219176774Sraj struct tsec_softc *sc = arg; 1220188711Sraj struct ifnet *ifp; 1221188711Sraj int link; 1222188711Sraj 1223188711Sraj TSEC_GLOBAL_LOCK(sc); 1224188711Sraj 1225188711Sraj tsec_watchdog(sc); 1226188711Sraj 1227188711Sraj ifp = sc->tsec_ifp; 1228188711Sraj link = sc->tsec_link; 1229188711Sraj 1230188711Sraj mii_tick(sc->tsec_mii); 1231188711Sraj 1232188711Sraj if (link == 0 && sc->tsec_link == 1 && 1233188711Sraj (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1234188711Sraj tsec_start_locked(ifp); 1235188711Sraj 1236188711Sraj /* Schedule another timeout one second from now. */ 1237188711Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1238188711Sraj 1239188711Sraj TSEC_GLOBAL_UNLOCK(sc); 1240188711Sraj} 1241188711Sraj 1242188711Sraj/* 1243188711Sraj * This is the core RX routine. It replenishes mbufs in the descriptor and 1244188711Sraj * sends data which have been dma'ed into host memory to upper layer. 1245188711Sraj * 1246188711Sraj * Loops at most count times if count is > 0, or until done if count < 0. 1247188711Sraj */ 1248188711Srajstatic void 1249188711Srajtsec_receive_intr_locked(struct tsec_softc *sc, int count) 1250188711Sraj{ 1251176774Sraj struct tsec_desc *rx_desc; 1252176774Sraj struct ifnet *ifp; 1253176774Sraj struct rx_data_type *rx_data; 1254176774Sraj struct mbuf *m; 1255176774Sraj device_t dev; 1256176774Sraj uint32_t i; 1257188711Sraj int c; 1258176774Sraj uint16_t flags; 1259176774Sraj 1260188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1261188711Sraj 1262176774Sraj ifp = sc->tsec_ifp; 1263176774Sraj rx_data = sc->rx_data; 1264176774Sraj dev = sc->dev; 1265176774Sraj 1266188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1267188711Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1268176774Sraj 1269188711Sraj for (c = 0; ; c++) { 1270188711Sraj if (count >= 0 && count-- == 0) 1271188711Sraj break; 1272176774Sraj 1273176774Sraj rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1274176774Sraj flags = rx_desc->flags; 1275176774Sraj 1276176774Sraj /* Check if there is anything to receive */ 1277188711Sraj if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1278176774Sraj /* 1279176774Sraj * Avoid generating another interrupt 1280176774Sraj */ 1281176774Sraj if (flags & TSEC_RXBD_E) 1282176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 1283176774Sraj TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1284176774Sraj /* 1285176774Sraj * We didn't consume current descriptor and have to 1286176774Sraj * return it to the queue 1287176774Sraj */ 1288176774Sraj TSEC_BACK_CUR_RX_DESC(sc); 1289176774Sraj break; 1290176774Sraj } 1291176774Sraj 1292176774Sraj if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1293176774Sraj TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1294182189Sraj 1295176774Sraj rx_desc->length = 0; 1296188711Sraj rx_desc->flags = (rx_desc->flags & 1297188711Sraj ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1298188711Sraj 1299188711Sraj if (sc->frame != NULL) { 1300188711Sraj m_free(sc->frame); 1301188711Sraj sc->frame = NULL; 1302188711Sraj } 1303188711Sraj 1304176774Sraj continue; 1305176774Sraj } 1306176774Sraj 1307176774Sraj /* Ok... process frame */ 1308176774Sraj i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1309176774Sraj m = rx_data[i].mbuf; 1310188711Sraj m->m_len = rx_desc->length; 1311176774Sraj 1312188711Sraj if (sc->frame != NULL) { 1313188711Sraj if ((flags & TSEC_RXBD_L) != 0) 1314188711Sraj m->m_len -= m_length(sc->frame, NULL); 1315188711Sraj 1316188711Sraj m->m_flags &= ~M_PKTHDR; 1317188711Sraj m_cat(sc->frame, m); 1318188711Sraj } else { 1319188711Sraj sc->frame = m; 1320188711Sraj } 1321188711Sraj 1322188711Sraj m = NULL; 1323188711Sraj 1324188711Sraj if ((flags & TSEC_RXBD_L) != 0) { 1325188711Sraj m = sc->frame; 1326188711Sraj sc->frame = NULL; 1327188711Sraj } 1328188711Sraj 1329176774Sraj if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1330176774Sraj &rx_data[i].mbuf, &rx_data[i].paddr)) { 1331176774Sraj ifp->if_ierrors++; 1332176774Sraj continue; 1333176774Sraj } 1334188711Sraj 1335188711Sraj /* Attach new buffer to descriptor and clear flags */ 1336176774Sraj rx_desc->bufptr = rx_data[i].paddr; 1337176774Sraj rx_desc->length = 0; 1338176774Sraj rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1339176774Sraj TSEC_RXBD_E | TSEC_RXBD_I; 1340176774Sraj 1341188711Sraj if (m != NULL) { 1342188711Sraj m->m_pkthdr.rcvif = ifp; 1343176774Sraj 1344188711Sraj m_fixhdr(m); 1345188711Sraj m_adj(m, -ETHER_CRC_LEN); 1346176774Sraj 1347188711Sraj if (sc->is_etsec) 1348188711Sraj tsec_offload_process_frame(sc, m); 1349176774Sraj 1350188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1351188711Sraj (*ifp->if_input)(ifp, m); 1352188711Sraj TSEC_RECEIVE_LOCK(sc); 1353188711Sraj } 1354188711Sraj } 1355176774Sraj 1356188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1357188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1358176774Sraj} 1359176774Sraj 1360182189Srajvoid 1361188711Srajtsec_receive_intr(void *arg) 1362176774Sraj{ 1363176774Sraj struct tsec_softc *sc = arg; 1364188711Sraj 1365188711Sraj TSEC_RECEIVE_LOCK(sc); 1366188711Sraj 1367188711Sraj#ifdef DEVICE_POLLING 1368188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1369188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1370188711Sraj return; 1371188711Sraj } 1372188711Sraj#endif 1373188711Sraj 1374188711Sraj /* Confirm the interrupt was received by driver */ 1375188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1376188711Sraj tsec_receive_intr_locked(sc, -1); 1377188711Sraj 1378188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1379188711Sraj} 1380188711Sraj 1381188711Srajstatic void 1382188711Srajtsec_transmit_intr_locked(struct tsec_softc *sc) 1383188711Sraj{ 1384176774Sraj struct tsec_desc *tx_desc; 1385176774Sraj struct ifnet *ifp; 1386176774Sraj struct mbuf *m0; 1387176774Sraj bus_dmamap_t *mapp; 1388176774Sraj int send = 0; 1389176774Sraj 1390188711Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 1391188711Sraj 1392176774Sraj ifp = sc->tsec_ifp; 1393176774Sraj 1394176774Sraj /* Update collision statistics */ 1395176774Sraj ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1396176774Sraj 1397176774Sraj /* Reset collision counters in hardware */ 1398176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1399176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1400176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1401176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1402176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1403176774Sraj 1404182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1405182189Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1406176774Sraj 1407176774Sraj while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1408176774Sraj tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1409176774Sraj if (tx_desc->flags & TSEC_TXBD_R) { 1410176774Sraj TSEC_BACK_DIRTY_TX_DESC(sc); 1411176774Sraj break; 1412176774Sraj } 1413176774Sraj 1414176774Sraj if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1415176774Sraj continue; 1416176774Sraj 1417176774Sraj /* 1418176774Sraj * This is the last buf in this packet, so unmap and free it. 1419176774Sraj */ 1420176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1421176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1422176774Sraj 1423176774Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_POSTWRITE); 1424176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1425176774Sraj 1426176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1427176774Sraj m_freem(m0); 1428176774Sraj 1429176774Sraj ifp->if_opackets++; 1430176774Sraj send = 1; 1431176774Sraj } 1432188711Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1433188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1434176774Sraj 1435176774Sraj if (send) { 1436176774Sraj /* Now send anything that was pending */ 1437176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1438176774Sraj tsec_start_locked(ifp); 1439176774Sraj 1440188711Sraj /* Stop wathdog if all sent */ 1441176774Sraj if (TSEC_EMPTYQ_TX_MBUF(sc)) 1442182187Sraj sc->tsec_watchdog = 0; 1443176774Sraj } 1444176774Sraj} 1445176774Sraj 1446182189Srajvoid 1447188711Srajtsec_transmit_intr(void *arg) 1448176774Sraj{ 1449176774Sraj struct tsec_softc *sc = arg; 1450188711Sraj 1451188711Sraj TSEC_TRANSMIT_LOCK(sc); 1452188711Sraj 1453188711Sraj#ifdef DEVICE_POLLING 1454188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1455188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1456188711Sraj return; 1457188711Sraj } 1458188711Sraj#endif 1459188711Sraj /* Confirm the interrupt was received by driver */ 1460188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1461188711Sraj tsec_transmit_intr_locked(sc); 1462188711Sraj 1463188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1464188711Sraj} 1465188711Sraj 1466188711Srajstatic void 1467188711Srajtsec_error_intr_locked(struct tsec_softc *sc, int count) 1468188711Sraj{ 1469176774Sraj struct ifnet *ifp; 1470176774Sraj uint32_t eflags; 1471176774Sraj 1472188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1473188711Sraj 1474176774Sraj ifp = sc->tsec_ifp; 1475176774Sraj 1476176774Sraj eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1477176774Sraj 1478176774Sraj /* Clear events bits in hardware */ 1479176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1480176774Sraj TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1481176774Sraj TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1482176774Sraj TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1483176774Sraj 1484176774Sraj /* Check transmitter errors */ 1485176774Sraj if (eflags & TSEC_IEVENT_TXE) { 1486176774Sraj ifp->if_oerrors++; 1487176774Sraj 1488176774Sraj if (eflags & TSEC_IEVENT_LC) 1489176774Sraj ifp->if_collisions++; 1490176774Sraj 1491176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1492176774Sraj } 1493176774Sraj 1494176774Sraj /* Check receiver errors */ 1495176774Sraj if (eflags & TSEC_IEVENT_BSY) { 1496176774Sraj ifp->if_ierrors++; 1497176774Sraj ifp->if_iqdrops++; 1498176774Sraj 1499176774Sraj /* Get data from RX buffers */ 1500188711Sraj tsec_receive_intr_locked(sc, count); 1501176774Sraj 1502176774Sraj /* Make receiver again active */ 1503176774Sraj TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1504176774Sraj } 1505188711Sraj 1506188711Sraj if (ifp->if_flags & IFF_DEBUG) 1507188711Sraj if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1508188711Sraj eflags); 1509188711Sraj 1510188711Sraj if (eflags & TSEC_IEVENT_EBERR) { 1511188711Sraj if_printf(ifp, "System bus error occurred during" 1512188711Sraj "DMA transaction (flags: 0x%x)\n", eflags); 1513188711Sraj tsec_init_locked(sc); 1514188711Sraj } 1515188711Sraj 1516188711Sraj if (eflags & TSEC_IEVENT_BABT) 1517188711Sraj ifp->if_oerrors++; 1518188711Sraj 1519176774Sraj if (eflags & TSEC_IEVENT_BABR) 1520176774Sraj ifp->if_ierrors++; 1521176774Sraj} 1522176774Sraj 1523188711Srajvoid 1524188711Srajtsec_error_intr(void *arg) 1525176774Sraj{ 1526188711Sraj struct tsec_softc *sc = arg; 1527176774Sraj 1528177111Sraj TSEC_GLOBAL_LOCK(sc); 1529188711Sraj tsec_error_intr_locked(sc, -1); 1530177111Sraj TSEC_GLOBAL_UNLOCK(sc); 1531176774Sraj} 1532176774Sraj 1533182189Srajint 1534176774Srajtsec_miibus_readreg(device_t dev, int phy, int reg) 1535176774Sraj{ 1536176774Sraj struct tsec_softc *sc; 1537176774Sraj uint32_t timeout; 1538176774Sraj 1539176774Sraj sc = device_get_softc(dev); 1540176774Sraj 1541176774Sraj if (device_get_unit(dev) != phy) 1542176774Sraj return (0); 1543176774Sraj 1544176774Sraj sc = tsec0_sc; 1545176774Sraj 1546176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1547176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1548176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1549176774Sraj 1550176774Sraj timeout = TSEC_READ_RETRY; 1551176774Sraj while (--timeout && TSEC_READ(sc, TSEC_REG_MIIMIND) & 1552176774Sraj (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1553176774Sraj DELAY(TSEC_READ_DELAY); 1554176774Sraj 1555176774Sraj if (timeout == 0) 1556176774Sraj device_printf(dev, "Timeout while reading from PHY!\n"); 1557176774Sraj 1558176774Sraj return (TSEC_READ(sc, TSEC_REG_MIIMSTAT)); 1559176774Sraj} 1560176774Sraj 1561182189Srajvoid 1562176774Srajtsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1563176774Sraj{ 1564176774Sraj struct tsec_softc *sc; 1565176774Sraj uint32_t timeout; 1566176774Sraj 1567176774Sraj sc = device_get_softc(dev); 1568176774Sraj 1569176774Sraj if (device_get_unit(dev) != phy) 1570176774Sraj device_printf(dev, "Trying to write to an alien PHY(%d)\n", phy); 1571176774Sraj 1572176774Sraj sc = tsec0_sc; 1573176774Sraj 1574176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1575176774Sraj TSEC_WRITE(sc, TSEC_REG_MIIMCON, value); 1576176774Sraj 1577176774Sraj timeout = TSEC_READ_RETRY; 1578176774Sraj while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & TSEC_MIIMIND_BUSY)) 1579176774Sraj DELAY(TSEC_READ_DELAY); 1580176774Sraj 1581176774Sraj if (timeout == 0) 1582176774Sraj device_printf(dev, "Timeout while writing to PHY!\n"); 1583176774Sraj} 1584176774Sraj 1585182189Srajvoid 1586176774Srajtsec_miibus_statchg(device_t dev) 1587176774Sraj{ 1588176774Sraj struct tsec_softc *sc; 1589176774Sraj struct mii_data *mii; 1590176774Sraj uint32_t ecntrl, id, tmp; 1591176774Sraj int link; 1592176774Sraj 1593176774Sraj sc = device_get_softc(dev); 1594176774Sraj mii = sc->tsec_mii; 1595176774Sraj link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1596176774Sraj 1597176774Sraj tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1598176774Sraj 1599176774Sraj if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1600176774Sraj tmp |= TSEC_MACCFG2_FULLDUPLEX; 1601176774Sraj else 1602176774Sraj tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1603176774Sraj 1604176774Sraj switch (IFM_SUBTYPE(mii->mii_media_active)) { 1605176774Sraj case IFM_1000_T: 1606176774Sraj case IFM_1000_SX: 1607176774Sraj tmp |= TSEC_MACCFG2_GMII; 1608176774Sraj sc->tsec_link = link; 1609176774Sraj break; 1610176774Sraj case IFM_100_TX: 1611176774Sraj case IFM_10_T: 1612176774Sraj tmp |= TSEC_MACCFG2_MII; 1613176774Sraj sc->tsec_link = link; 1614176774Sraj break; 1615176774Sraj case IFM_NONE: 1616176774Sraj if (link) 1617176774Sraj device_printf(dev, "No speed selected but link active!\n"); 1618176774Sraj sc->tsec_link = 0; 1619176774Sraj return; 1620176774Sraj default: 1621176774Sraj sc->tsec_link = 0; 1622176774Sraj device_printf(dev, "Unknown speed (%d), link %s!\n", 1623176774Sraj IFM_SUBTYPE(mii->mii_media_active), 1624182189Sraj ((link) ? "up" : "down")); 1625176774Sraj return; 1626176774Sraj } 1627176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1628176774Sraj 1629176774Sraj /* XXX kludge - use circumstantial evidence for reduced mode. */ 1630176774Sraj id = TSEC_READ(sc, TSEC_REG_ID2); 1631176774Sraj if (id & 0xffff) { 1632176774Sraj ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1633176774Sraj ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1634176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1635176774Sraj } 1636176774Sraj} 1637188711Sraj 1638188711Srajstatic void 1639188711Srajtsec_add_sysctls(struct tsec_softc *sc) 1640188711Sraj{ 1641188711Sraj struct sysctl_ctx_list *ctx; 1642188711Sraj struct sysctl_oid_list *children; 1643188711Sraj struct sysctl_oid *tree; 1644188711Sraj 1645188711Sraj ctx = device_get_sysctl_ctx(sc->dev); 1646188711Sraj children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1647188711Sraj tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1648188711Sraj CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1649188711Sraj children = SYSCTL_CHILDREN(tree); 1650188711Sraj 1651188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1652188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1653188711Sraj "I", "IC RX time threshold (0-65535)"); 1654188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1655188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1656188711Sraj "I", "IC RX frame count threshold (0-255)"); 1657188711Sraj 1658188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1659188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1660188711Sraj "I", "IC TX time threshold (0-65535)"); 1661188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1662188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1663188711Sraj "I", "IC TX frame count threshold (0-255)"); 1664188711Sraj} 1665188711Sraj 1666188711Sraj/* 1667188711Sraj * With Interrupt Coalescing (IC) active, a transmit/receive frame 1668188711Sraj * interrupt is raised either upon: 1669188711Sraj * 1670188711Sraj * - threshold-defined period of time elapsed, or 1671188711Sraj * - threshold-defined number of frames is received/transmitted, 1672188711Sraj * whichever occurs first. 1673188711Sraj * 1674188711Sraj * The following sysctls regulate IC behaviour (for TX/RX separately): 1675188711Sraj * 1676188711Sraj * dev.tsec.<unit>.int_coal.rx_time 1677188711Sraj * dev.tsec.<unit>.int_coal.rx_count 1678188711Sraj * dev.tsec.<unit>.int_coal.tx_time 1679188711Sraj * dev.tsec.<unit>.int_coal.tx_count 1680188711Sraj * 1681188711Sraj * Values: 1682188711Sraj * 1683188711Sraj * - 0 for either time or count disables IC on the given TX/RX path 1684188711Sraj * 1685188711Sraj * - count: 1-255 (expresses frame count number; note that value of 1 is 1686188711Sraj * effectively IC off) 1687188711Sraj * 1688188711Sraj * - time: 1-65535 (value corresponds to a real time period and is 1689188711Sraj * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1690188711Sraj * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1691188711Sraj * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1692188711Sraj * TSEC reference manual. 1693188711Sraj */ 1694188711Sraj 1695188711Srajstatic int 1696188711Srajtsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1697188711Sraj{ 1698188711Sraj int error; 1699188711Sraj uint32_t time; 1700188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1701188711Sraj 1702188711Sraj time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1703188711Sraj 1704188711Sraj error = sysctl_handle_int(oidp, &time, 0, req); 1705188711Sraj if (error != 0) 1706188711Sraj return (error); 1707188711Sraj 1708188711Sraj if (time > 65535) 1709188711Sraj return (EINVAL); 1710188711Sraj 1711188711Sraj TSEC_IC_LOCK(sc); 1712188711Sraj if (arg2 == TSEC_IC_RX) { 1713188711Sraj sc->rx_ic_time = time; 1714188711Sraj tsec_set_rxic(sc); 1715188711Sraj } else { 1716188711Sraj sc->tx_ic_time = time; 1717188711Sraj tsec_set_txic(sc); 1718188711Sraj } 1719188711Sraj TSEC_IC_UNLOCK(sc); 1720188711Sraj 1721188711Sraj return (0); 1722188711Sraj} 1723188711Sraj 1724188711Srajstatic int 1725188711Srajtsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1726188711Sraj{ 1727188711Sraj int error; 1728188711Sraj uint32_t count; 1729188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1730188711Sraj 1731188711Sraj count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1732188711Sraj 1733188711Sraj error = sysctl_handle_int(oidp, &count, 0, req); 1734188711Sraj if (error != 0) 1735188711Sraj return (error); 1736188711Sraj 1737188711Sraj if (count > 255) 1738188711Sraj return (EINVAL); 1739188711Sraj 1740188711Sraj TSEC_IC_LOCK(sc); 1741188711Sraj if (arg2 == TSEC_IC_RX) { 1742188711Sraj sc->rx_ic_count = count; 1743188711Sraj tsec_set_rxic(sc); 1744188711Sraj } else { 1745188711Sraj sc->tx_ic_count = count; 1746188711Sraj tsec_set_txic(sc); 1747188711Sraj } 1748188711Sraj TSEC_IC_UNLOCK(sc); 1749188711Sraj 1750188711Sraj return (0); 1751188711Sraj} 1752188711Sraj 1753188711Srajstatic void 1754188711Srajtsec_set_rxic(struct tsec_softc *sc) 1755188711Sraj{ 1756188711Sraj uint32_t rxic_val; 1757188711Sraj 1758188711Sraj if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1759188711Sraj /* Disable RX IC */ 1760188711Sraj rxic_val = 0; 1761188711Sraj else { 1762188711Sraj rxic_val = 0x80000000; 1763188711Sraj rxic_val |= (sc->rx_ic_count << 21); 1764188711Sraj rxic_val |= sc->rx_ic_time; 1765188711Sraj } 1766188711Sraj 1767188711Sraj TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1768188711Sraj} 1769188711Sraj 1770188711Srajstatic void 1771188711Srajtsec_set_txic(struct tsec_softc *sc) 1772188711Sraj{ 1773188711Sraj uint32_t txic_val; 1774188711Sraj 1775188711Sraj if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1776188711Sraj /* Disable TX IC */ 1777188711Sraj txic_val = 0; 1778188711Sraj else { 1779188711Sraj txic_val = 0x80000000; 1780188711Sraj txic_val |= (sc->tx_ic_count << 21); 1781188711Sraj txic_val |= sc->tx_ic_time; 1782188711Sraj } 1783188711Sraj 1784188711Sraj TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1785188711Sraj} 1786188711Sraj 1787188711Srajstatic void 1788188711Srajtsec_offload_setup(struct tsec_softc *sc) 1789188711Sraj{ 1790188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1791188711Sraj uint32_t reg; 1792188711Sraj 1793188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1794188711Sraj 1795188711Sraj reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1796188711Sraj reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1797188711Sraj 1798188711Sraj if (ifp->if_capenable & IFCAP_TXCSUM) 1799188711Sraj ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1800188711Sraj else 1801188711Sraj ifp->if_hwassist = 0; 1802188711Sraj 1803188711Sraj TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1804188711Sraj 1805188711Sraj reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1806188711Sraj reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1807188711Sraj reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1808188711Sraj 1809188711Sraj if (ifp->if_capenable & IFCAP_RXCSUM) 1810188711Sraj reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1811188711Sraj TSEC_RCTRL_PRSDEP_PARSE_L234; 1812188711Sraj 1813188711Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1814188711Sraj} 1815188711Sraj 1816188711Sraj 1817188711Srajstatic void 1818188711Srajtsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1819188711Sraj{ 1820188711Sraj struct tsec_rx_fcb rx_fcb; 1821188711Sraj int csum_flags = 0; 1822188711Sraj int protocol, flags; 1823188711Sraj 1824188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1825188711Sraj 1826188711Sraj m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1827188711Sraj flags = rx_fcb.flags; 1828188711Sraj protocol = rx_fcb.protocol; 1829188711Sraj 1830188711Sraj if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1831188711Sraj csum_flags |= CSUM_IP_CHECKED; 1832188711Sraj 1833188711Sraj if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1834188711Sraj csum_flags |= CSUM_IP_VALID; 1835188711Sraj } 1836188711Sraj 1837188711Sraj if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1838188711Sraj TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1839188711Sraj (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1840188711Sraj 1841188711Sraj csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1842188711Sraj m->m_pkthdr.csum_data = 0xFFFF; 1843188711Sraj } 1844188711Sraj 1845188711Sraj m->m_pkthdr.csum_flags = csum_flags; 1846188711Sraj 1847188711Sraj if (flags & TSEC_RX_FCB_VLAN) { 1848188711Sraj m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1849188711Sraj m->m_flags |= M_VLANTAG; 1850188711Sraj } 1851188711Sraj 1852188711Sraj m_adj(m, sizeof(struct tsec_rx_fcb)); 1853188711Sraj} 1854188711Sraj 1855188711Srajstatic void 1856188711Srajtsec_setup_multicast(struct tsec_softc *sc) 1857188711Sraj{ 1858188711Sraj uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1859188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1860188711Sraj struct ifmultiaddr *ifma; 1861188711Sraj uint32_t h; 1862188711Sraj int i; 1863188711Sraj 1864188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1865188711Sraj 1866188711Sraj if (ifp->if_flags & IFF_ALLMULTI) { 1867188711Sraj for (i = 0; i < 8; i++) 1868188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1869188711Sraj 1870188711Sraj return; 1871188711Sraj } 1872188711Sraj 1873188711Sraj IF_ADDR_LOCK(ifp); 1874188711Sraj TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1875188711Sraj 1876188711Sraj if (ifma->ifma_addr->sa_family != AF_LINK) 1877188711Sraj continue; 1878188711Sraj 1879188711Sraj h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1880188711Sraj ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1881188711Sraj 1882188711Sraj hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1883188711Sraj } 1884188711Sraj IF_ADDR_UNLOCK(ifp); 1885188711Sraj 1886188711Sraj for (i = 0; i < 8; i++) 1887188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1888188711Sraj} 1889188711Sraj 1890188711Srajstatic int 1891188711Srajtsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1892188711Sraj{ 1893188711Sraj 1894188711Sraj mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1895188711Sraj 1896188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1897188711Sraj 1898188711Sraj if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1899188711Sraj TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1900188711Sraj return (mtu); 1901188711Sraj } 1902188711Sraj 1903188711Sraj return (0); 1904188711Sraj} 1905