1176774Sraj/*- 2209908Sraj * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski 3209908Sraj * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 4176774Sraj * All rights reserved. 5176774Sraj * 6176774Sraj * Redistribution and use in source and binary forms, with or without 7176774Sraj * modification, are permitted provided that the following conditions 8176774Sraj * are met: 9176774Sraj * 1. Redistributions of source code must retain the above copyright 10176774Sraj * notice, this list of conditions and the following disclaimer. 11176774Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176774Sraj * notice, this list of conditions and the following disclaimer in the 13176774Sraj * documentation and/or other materials provided with the distribution. 14176774Sraj * 15176774Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176774Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176774Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176774Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176774Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176774Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176774Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176774Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176774Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176774Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176774Sraj */ 26176774Sraj 27176774Sraj/* 28176774Sraj * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29176774Sraj */ 30176774Sraj#include <sys/cdefs.h> 31176774Sraj__FBSDID("$FreeBSD$"); 32176774Sraj 33188711Sraj#ifdef HAVE_KERNEL_OPTION_HEADERS 34188711Sraj#include "opt_device_polling.h" 35188711Sraj#endif 36188711Sraj 37176774Sraj#include <sys/param.h> 38176774Sraj#include <sys/systm.h> 39182189Sraj#include <sys/bus.h> 40176774Sraj#include <sys/endian.h> 41176774Sraj#include <sys/mbuf.h> 42176774Sraj#include <sys/kernel.h> 43176774Sraj#include <sys/module.h> 44176774Sraj#include <sys/socket.h> 45182189Sraj#include <sys/sockio.h> 46176774Sraj#include <sys/sysctl.h> 47176774Sraj 48182189Sraj#include <net/bpf.h> 49182189Sraj#include <net/ethernet.h> 50176774Sraj#include <net/if.h> 51182189Sraj#include <net/if_arp.h> 52176774Sraj#include <net/if_dl.h> 53176774Sraj#include <net/if_media.h> 54182189Sraj#include <net/if_types.h> 55182189Sraj#include <net/if_vlan_var.h> 56176774Sraj 57188711Sraj#include <netinet/in_systm.h> 58188711Sraj#include <netinet/in.h> 59188711Sraj#include <netinet/ip.h> 60188711Sraj 61176774Sraj#include <machine/bus.h> 62176774Sraj 63176774Sraj#include <dev/mii/mii.h> 64176774Sraj#include <dev/mii/miivar.h> 65176774Sraj 66176774Sraj#include <dev/tsec/if_tsec.h> 67176774Sraj#include <dev/tsec/if_tsecreg.h> 68176774Sraj 69182189Srajstatic int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70182189Sraj bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71182189Sraj const char *dname); 72182189Srajstatic void tsec_dma_ctl(struct tsec_softc *sc, int state); 73188711Srajstatic int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74188711Sraj int fcb_inserted); 75176774Srajstatic void tsec_free_dma(struct tsec_softc *sc); 76182189Srajstatic void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77176774Srajstatic int tsec_ifmedia_upd(struct ifnet *ifp); 78176774Srajstatic void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79176774Srajstatic int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80176774Sraj struct mbuf **mbufp, uint32_t *paddr); 81176774Srajstatic void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82176774Sraj int nseg, int error); 83182189Srajstatic void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84182189Srajstatic void tsec_init(void *xsc); 85182189Srajstatic void tsec_init_locked(struct tsec_softc *sc); 86182189Srajstatic int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87182189Srajstatic void tsec_reset_mac(struct tsec_softc *sc); 88182189Srajstatic void tsec_setfilter(struct tsec_softc *sc); 89182189Srajstatic void tsec_set_mac_address(struct tsec_softc *sc); 90182189Srajstatic void tsec_start(struct ifnet *ifp); 91182189Srajstatic void tsec_start_locked(struct ifnet *ifp); 92176774Srajstatic void tsec_stop(struct tsec_softc *sc); 93182189Srajstatic void tsec_tick(void *arg); 94182189Srajstatic void tsec_watchdog(struct tsec_softc *sc); 95188711Srajstatic void tsec_add_sysctls(struct tsec_softc *sc); 96188711Srajstatic int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97188711Srajstatic int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98188711Srajstatic void tsec_set_rxic(struct tsec_softc *sc); 99188711Srajstatic void tsec_set_txic(struct tsec_softc *sc); 100193096Sattiliostatic int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101188711Srajstatic void tsec_transmit_intr_locked(struct tsec_softc *sc); 102188711Srajstatic void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103188711Srajstatic void tsec_offload_setup(struct tsec_softc *sc); 104188711Srajstatic void tsec_offload_process_frame(struct tsec_softc *sc, 105188711Sraj struct mbuf *m); 106188711Srajstatic void tsec_setup_multicast(struct tsec_softc *sc); 107188711Srajstatic int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108176774Sraj 109182189Srajdevclass_t tsec_devclass; 110182189SrajDRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 111182189SrajMODULE_DEPEND(tsec, ether, 1, 1, 1); 112182189SrajMODULE_DEPEND(tsec, miibus, 1, 1, 1); 113176774Sraj 114182189Srajint 115182189Srajtsec_attach(struct tsec_softc *sc) 116182189Sraj{ 117182189Sraj uint8_t hwaddr[ETHER_ADDR_LEN]; 118182189Sraj struct ifnet *ifp; 119182189Sraj bus_dmamap_t *map_ptr; 120182189Sraj bus_dmamap_t **map_pptr; 121182189Sraj int error = 0; 122182189Sraj int i; 123176774Sraj 124182189Sraj /* Reset all TSEC counters */ 125182189Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 126176774Sraj 127182189Sraj /* Stop DMA engine if enabled by firmware */ 128182189Sraj tsec_dma_ctl(sc, 0); 129176774Sraj 130182189Sraj /* Reset MAC */ 131182189Sraj tsec_reset_mac(sc); 132176774Sraj 133182189Sraj /* Disable interrupts for now */ 134182189Sraj tsec_intrs_ctl(sc, 0); 135176774Sraj 136188711Sraj /* Configure defaults for interrupts coalescing */ 137188711Sraj sc->rx_ic_time = 768; 138188711Sraj sc->rx_ic_count = 16; 139188711Sraj sc->tx_ic_time = 768; 140188711Sraj sc->tx_ic_count = 16; 141188711Sraj tsec_set_rxic(sc); 142188711Sraj tsec_set_txic(sc); 143188711Sraj tsec_add_sysctls(sc); 144188711Sraj 145182189Sraj /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 146188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 147188711Sraj &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 148182189Sraj (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 149188711Sraj 150182189Sraj if (error) { 151182189Sraj tsec_detach(sc); 152182189Sraj return (ENXIO); 153182189Sraj } 154176774Sraj 155182189Sraj /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 156188711Sraj error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 157188711Sraj &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 158182189Sraj (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 159182189Sraj if (error) { 160182189Sraj tsec_detach(sc); 161182189Sraj return (ENXIO); 162182189Sraj } 163176774Sraj 164182189Sraj /* Allocate a busdma tag for TX mbufs. */ 165182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 166188712Sraj TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 167188712Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 168188712Sraj BUS_SPACE_MAXADDR, /* highaddr */ 169188712Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 170188712Sraj MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 171188712Sraj TSEC_TX_NUM_DESC - 1, /* nsegments */ 172188712Sraj MCLBYTES, 0, /* maxsegsz, flags */ 173188712Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 174188712Sraj &sc->tsec_tx_mtag); /* dmat */ 175182189Sraj if (error) { 176188712Sraj device_printf(sc->dev, "failed to allocate busdma tag " 177188712Sraj "(tx mbufs)\n"); 178182189Sraj tsec_detach(sc); 179182189Sraj return (ENXIO); 180182189Sraj } 181182189Sraj 182182189Sraj /* Allocate a busdma tag for RX mbufs. */ 183182189Sraj error = bus_dma_tag_create(NULL, /* parent */ 184188712Sraj TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 185188712Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 186188712Sraj BUS_SPACE_MAXADDR, /* highaddr */ 187188712Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 188188712Sraj MCLBYTES, /* maxsize */ 189188712Sraj 1, /* nsegments */ 190188712Sraj MCLBYTES, 0, /* maxsegsz, flags */ 191188712Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 192188712Sraj &sc->tsec_rx_mtag); /* dmat */ 193182189Sraj if (error) { 194188712Sraj device_printf(sc->dev, "failed to allocate busdma tag " 195188712Sraj "(rx mbufs)\n"); 196182189Sraj tsec_detach(sc); 197182189Sraj return (ENXIO); 198182189Sraj } 199182189Sraj 200182189Sraj /* Create TX busdma maps */ 201182189Sraj map_ptr = sc->tx_map_data; 202182189Sraj map_pptr = sc->tx_map_unused_data; 203182189Sraj 204182189Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 205182189Sraj map_pptr[i] = &map_ptr[i]; 206182189Sraj error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 207182189Sraj if (error) { 208182189Sraj device_printf(sc->dev, "failed to init TX ring\n"); 209182189Sraj tsec_detach(sc); 210182189Sraj return (ENXIO); 211182189Sraj } 212182189Sraj } 213182189Sraj 214182189Sraj /* Create RX busdma maps and zero mbuf handlers */ 215182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 216188712Sraj error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 217188712Sraj &sc->rx_data[i].map); 218182189Sraj if (error) { 219182189Sraj device_printf(sc->dev, "failed to init RX ring\n"); 220182189Sraj tsec_detach(sc); 221182189Sraj return (ENXIO); 222182189Sraj } 223182189Sraj sc->rx_data[i].mbuf = NULL; 224182189Sraj } 225182189Sraj 226182189Sraj /* Create mbufs for RX buffers */ 227182189Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 228182189Sraj error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 229182189Sraj &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 230182189Sraj if (error) { 231188712Sraj device_printf(sc->dev, "can't load rx DMA map %d, " 232188712Sraj "error = %d\n", i, error); 233182189Sraj tsec_detach(sc); 234182189Sraj return (error); 235182189Sraj } 236182189Sraj } 237182189Sraj 238182189Sraj /* Create network interface for upper layers */ 239182189Sraj ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 240182189Sraj if (ifp == NULL) { 241182189Sraj device_printf(sc->dev, "if_alloc() failed\n"); 242182189Sraj tsec_detach(sc); 243182189Sraj return (ENOMEM); 244182189Sraj } 245182189Sraj 246182189Sraj ifp->if_softc = sc; 247182189Sraj if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 248182189Sraj ifp->if_mtu = ETHERMTU; 249188711Sraj ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 250182189Sraj ifp->if_init = tsec_init; 251182189Sraj ifp->if_start = tsec_start; 252182189Sraj ifp->if_ioctl = tsec_ioctl; 253182189Sraj 254182189Sraj IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 255182189Sraj ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 256182189Sraj IFQ_SET_READY(&ifp->if_snd); 257182189Sraj 258188711Sraj ifp->if_capabilities = IFCAP_VLAN_MTU; 259188711Sraj if (sc->is_etsec) 260188711Sraj ifp->if_capabilities |= IFCAP_HWCSUM; 261188711Sraj 262182189Sraj ifp->if_capenable = ifp->if_capabilities; 263182189Sraj 264188711Sraj#ifdef DEVICE_POLLING 265188711Sraj /* Advertise that polling is supported */ 266188711Sraj ifp->if_capabilities |= IFCAP_POLLING; 267188711Sraj#endif 268188711Sraj 269213893Smarius /* Attach PHY(s) */ 270213893Smarius error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd, 271213893Smarius tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 272213893Smarius 0); 273182189Sraj if (error) { 274213893Smarius device_printf(sc->dev, "attaching PHYs failed\n"); 275182189Sraj if_free(ifp); 276182189Sraj sc->tsec_ifp = NULL; 277182189Sraj tsec_detach(sc); 278182189Sraj return (error); 279182189Sraj } 280182189Sraj sc->tsec_mii = device_get_softc(sc->tsec_miibus); 281182189Sraj 282182189Sraj /* Set MAC address */ 283182189Sraj tsec_get_hwaddr(sc, hwaddr); 284182189Sraj ether_ifattach(ifp, hwaddr); 285182189Sraj 286182189Sraj return (0); 287182189Sraj} 288182189Sraj 289182189Srajint 290182189Srajtsec_detach(struct tsec_softc *sc) 291176774Sraj{ 292176774Sraj 293236053Sthompsa if (sc->tsec_ifp != NULL) { 294188711Sraj#ifdef DEVICE_POLLING 295236053Sthompsa if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 296236053Sthompsa ether_poll_deregister(sc->tsec_ifp); 297188711Sraj#endif 298188711Sraj 299236053Sthompsa /* Stop TSEC controller and free TX queue */ 300236053Sthompsa if (sc->sc_rres) 301236053Sthompsa tsec_shutdown(sc->dev); 302182189Sraj 303236053Sthompsa /* Detach network interface */ 304182189Sraj ether_ifdetach(sc->tsec_ifp); 305182189Sraj if_free(sc->tsec_ifp); 306182189Sraj sc->tsec_ifp = NULL; 307177110Sraj } 308177110Sraj 309182189Sraj /* Free DMA resources */ 310182189Sraj tsec_free_dma(sc); 311176774Sraj 312182189Sraj return (0); 313176774Sraj} 314176774Sraj 315194101Srajint 316182189Srajtsec_shutdown(device_t dev) 317182189Sraj{ 318182189Sraj struct tsec_softc *sc; 319182189Sraj 320182189Sraj sc = device_get_softc(dev); 321182189Sraj 322182189Sraj TSEC_GLOBAL_LOCK(sc); 323182189Sraj tsec_stop(sc); 324182189Sraj TSEC_GLOBAL_UNLOCK(sc); 325194101Sraj return (0); 326182189Sraj} 327182189Sraj 328182189Srajint 329182189Srajtsec_suspend(device_t dev) 330182189Sraj{ 331182189Sraj 332182189Sraj /* TODO not implemented! */ 333182189Sraj return (0); 334182189Sraj} 335182189Sraj 336182189Srajint 337182189Srajtsec_resume(device_t dev) 338182189Sraj{ 339182189Sraj 340182189Sraj /* TODO not implemented! */ 341182189Sraj return (0); 342182189Sraj} 343182189Sraj 344176774Srajstatic void 345176774Srajtsec_init(void *xsc) 346176774Sraj{ 347176774Sraj struct tsec_softc *sc = xsc; 348176774Sraj 349176774Sraj TSEC_GLOBAL_LOCK(sc); 350176774Sraj tsec_init_locked(sc); 351176774Sraj TSEC_GLOBAL_UNLOCK(sc); 352176774Sraj} 353176774Sraj 354176774Srajstatic void 355176774Srajtsec_init_locked(struct tsec_softc *sc) 356176774Sraj{ 357176774Sraj struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 358176774Sraj struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 359176774Sraj struct ifnet *ifp = sc->tsec_ifp; 360188712Sraj uint32_t timeout, val, i; 361176774Sraj 362236054Sthompsa if (ifp->if_drv_flags & IFF_DRV_RUNNING) 363236054Sthompsa return; 364236054Sthompsa 365176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 366176774Sraj tsec_stop(sc); 367176774Sraj 368176774Sraj /* 369176774Sraj * These steps are according to the MPC8555E PowerQUICCIII RM: 370176774Sraj * 14.7 Initialization/Application Information 371176774Sraj */ 372176774Sraj 373176774Sraj /* Step 1: soft reset MAC */ 374176774Sraj tsec_reset_mac(sc); 375176774Sraj 376176774Sraj /* Step 2: Initialize MACCFG2 */ 377176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, 378176774Sraj TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 379176774Sraj TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 380176774Sraj TSEC_MACCFG2_GMII | /* I/F Mode bit */ 381176774Sraj TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 382176774Sraj ); 383176774Sraj 384176774Sraj /* Step 3: Initialize ECNTRL 385176774Sraj * While the documentation states that R100M is ignored if RPM is 386176774Sraj * not set, it does seem to be needed to get the orange boxes to 387176774Sraj * work (which have a Marvell 88E1111 PHY). Go figure. 388176774Sraj */ 389176774Sraj 390176774Sraj /* 391176774Sraj * XXX kludge - use circumstancial evidence to program ECNTRL 392176774Sraj * correctly. Ideally we need some board information to guide 393176774Sraj * us here. 394176774Sraj */ 395176774Sraj i = TSEC_READ(sc, TSEC_REG_ID2); 396176774Sraj val = (i & 0xffff) 397176774Sraj ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 398176774Sraj : TSEC_ECNTRL_R100M; /* Orange + CDS */ 399176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 400176774Sraj 401176774Sraj /* Step 4: Initialize MAC station address */ 402176774Sraj tsec_set_mac_address(sc); 403176774Sraj 404176774Sraj /* 405176774Sraj * Step 5: Assign a Physical address to the TBI so as to not conflict 406176774Sraj * with the external PHY physical address 407176774Sraj */ 408176774Sraj TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 409176774Sraj 410176774Sraj /* Step 6: Reset the management interface */ 411233015Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 412176774Sraj 413176774Sraj /* Step 7: Setup the MII Mgmt clock speed */ 414233015Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 415176774Sraj 416176774Sraj /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 417176774Sraj timeout = TSEC_READ_RETRY; 418233015Sraj while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & 419176774Sraj TSEC_MIIMIND_BUSY)) 420176774Sraj DELAY(TSEC_READ_DELAY); 421176774Sraj if (timeout == 0) { 422176774Sraj if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 423176774Sraj return; 424176774Sraj } 425176774Sraj 426176774Sraj /* Step 9: Setup the MII Mgmt */ 427176774Sraj mii_mediachg(sc->tsec_mii); 428176774Sraj 429176774Sraj /* Step 10: Clear IEVENT register */ 430176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 431176774Sraj 432188711Sraj /* Step 11: Enable interrupts */ 433188711Sraj#ifdef DEVICE_POLLING 434188711Sraj /* 435188711Sraj * ...only if polling is not turned on. Disable interrupts explicitly 436188711Sraj * if polling is enabled. 437188711Sraj */ 438188711Sraj if (ifp->if_capenable & IFCAP_POLLING ) 439188711Sraj tsec_intrs_ctl(sc, 0); 440188711Sraj else 441188711Sraj#endif /* DEVICE_POLLING */ 442176774Sraj tsec_intrs_ctl(sc, 1); 443176774Sraj 444176774Sraj /* Step 12: Initialize IADDRn */ 445176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 446176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 447176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 448176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 449176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 450176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 451176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 452176774Sraj TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 453176774Sraj 454176774Sraj /* Step 13: Initialize GADDRn */ 455176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 456176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 457176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 458176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 459176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 460176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 461176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 462176774Sraj TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 463176774Sraj 464176774Sraj /* Step 14: Initialize RCTRL */ 465176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 466176774Sraj 467176774Sraj /* Step 15: Initialize DMACTRL */ 468176774Sraj tsec_dma_ctl(sc, 1); 469176774Sraj 470176774Sraj /* Step 16: Initialize FIFO_PAUSE_CTRL */ 471176774Sraj TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 472176774Sraj 473176774Sraj /* 474176774Sraj * Step 17: Initialize transmit/receive descriptor rings. 475176774Sraj * Initialize TBASE and RBASE. 476176774Sraj */ 477176774Sraj TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 478176774Sraj TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 479176774Sraj 480176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 481176774Sraj tx_desc[i].bufptr = 0; 482176774Sraj tx_desc[i].length = 0; 483188712Sraj tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 484188712Sraj TSEC_TXBD_W : 0); 485176774Sraj } 486182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 487182189Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 488176774Sraj 489176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 490176774Sraj rx_desc[i].bufptr = sc->rx_data[i].paddr; 491176774Sraj rx_desc[i].length = 0; 492176774Sraj rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 493182189Sraj ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 494176774Sraj } 495188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 496188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 497176774Sraj 498188711Sraj /* Step 18: Initialize the maximum receive buffer length */ 499188711Sraj TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 500176774Sraj 501188711Sraj /* Step 19: Configure ethernet frame sizes */ 502188711Sraj TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 503188711Sraj tsec_set_mtu(sc, ifp->if_mtu); 504188711Sraj 505188711Sraj /* Step 20: Enable Rx and RxBD sdata snooping */ 506176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 507176774Sraj TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 508176774Sraj 509188711Sraj /* Step 21: Reset collision counters in hardware */ 510176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 511176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 512176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 513176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 514176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 515176774Sraj 516188711Sraj /* Step 22: Mask all CAM interrupts */ 517176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 518176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 519176774Sraj 520188711Sraj /* Step 23: Enable Rx and Tx */ 521176774Sraj val = TSEC_READ(sc, TSEC_REG_MACCFG1); 522176774Sraj val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 523176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 524176774Sraj 525188711Sraj /* Step 24: Reset TSEC counters for Tx and Rx rings */ 526176774Sraj TSEC_TX_RX_COUNTERS_INIT(sc); 527176774Sraj 528188711Sraj /* Step 25: Setup TCP/IP Off-Load engine */ 529188711Sraj if (sc->is_etsec) 530188711Sraj tsec_offload_setup(sc); 531188711Sraj 532188711Sraj /* Step 26: Setup multicast filters */ 533188711Sraj tsec_setup_multicast(sc); 534188711Sraj 535188711Sraj /* Step 27: Activate network interface */ 536176774Sraj ifp->if_drv_flags |= IFF_DRV_RUNNING; 537176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 538176774Sraj sc->tsec_if_flags = ifp->if_flags; 539182187Sraj sc->tsec_watchdog = 0; 540177111Sraj 541177111Sraj /* Schedule watchdog timeout */ 542182187Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 543176774Sraj} 544176774Sraj 545176774Srajstatic void 546176774Srajtsec_set_mac_address(struct tsec_softc *sc) 547176774Sraj{ 548176774Sraj uint32_t macbuf[2] = { 0, 0 }; 549188712Sraj char *macbufp, *curmac; 550182189Sraj int i; 551176774Sraj 552176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 553176774Sraj 554176774Sraj KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 555188712Sraj ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, 556188712Sraj sizeof(macbuf))); 557176774Sraj 558176774Sraj macbufp = (char *)macbuf; 559176774Sraj curmac = (char *)IF_LLADDR(sc->tsec_ifp); 560176774Sraj 561176774Sraj /* Correct order of MAC address bytes */ 562176774Sraj for (i = 1; i <= ETHER_ADDR_LEN; i++) 563176774Sraj macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 564176774Sraj 565176774Sraj /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 566176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 567176774Sraj TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 568176774Sraj} 569176774Sraj 570176774Sraj/* 571176774Sraj * DMA control function, if argument state is: 572176774Sraj * 0 - DMA engine will be disabled 573176774Sraj * 1 - DMA engine will be enabled 574176774Sraj */ 575176774Srajstatic void 576176774Srajtsec_dma_ctl(struct tsec_softc *sc, int state) 577176774Sraj{ 578176774Sraj device_t dev; 579188712Sraj uint32_t dma_flags, timeout; 580176774Sraj 581176774Sraj dev = sc->dev; 582176774Sraj 583176774Sraj dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 584176774Sraj 585176774Sraj switch (state) { 586176774Sraj case 0: 587176774Sraj /* Temporarily clear stop graceful stop bits. */ 588176774Sraj tsec_dma_ctl(sc, 1000); 589176774Sraj 590176774Sraj /* Set it again */ 591176774Sraj dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 592176774Sraj break; 593176774Sraj case 1000: 594176774Sraj case 1: 595176774Sraj /* Set write with response (WWR), wait (WOP) and snoop bits */ 596176774Sraj dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 597176774Sraj DMACTRL_WWR | DMACTRL_WOP); 598176774Sraj 599176774Sraj /* Clear graceful stop bits */ 600176774Sraj dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 601176774Sraj break; 602176774Sraj default: 603176774Sraj device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 604176774Sraj state); 605176774Sraj } 606176774Sraj 607176774Sraj TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 608176774Sraj 609176774Sraj switch (state) { 610176774Sraj case 0: 611176774Sraj /* Wait for DMA stop */ 612176774Sraj timeout = TSEC_READ_RETRY; 613176774Sraj while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 614176774Sraj (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 615176774Sraj DELAY(TSEC_READ_DELAY); 616176774Sraj 617176774Sraj if (timeout == 0) 618176774Sraj device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 619176774Sraj break; 620176774Sraj case 1: 621176774Sraj /* Restart transmission function */ 622176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 623176774Sraj } 624176774Sraj} 625176774Sraj 626176774Sraj/* 627176774Sraj * Interrupts control function, if argument state is: 628176774Sraj * 0 - all TSEC interrupts will be masked 629176774Sraj * 1 - all TSEC interrupts will be unmasked 630176774Sraj */ 631176774Srajstatic void 632176774Srajtsec_intrs_ctl(struct tsec_softc *sc, int state) 633176774Sraj{ 634176774Sraj device_t dev; 635176774Sraj 636176774Sraj dev = sc->dev; 637176774Sraj 638176774Sraj switch (state) { 639176774Sraj case 0: 640176774Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 641176774Sraj break; 642176774Sraj case 1: 643188712Sraj TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 644188712Sraj TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 645188712Sraj TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 646188712Sraj TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 647176774Sraj break; 648176774Sraj default: 649176774Sraj device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 650176774Sraj state); 651176774Sraj } 652176774Sraj} 653176774Sraj 654176774Srajstatic void 655176774Srajtsec_reset_mac(struct tsec_softc *sc) 656176774Sraj{ 657176774Sraj uint32_t maccfg1_flags; 658176774Sraj 659176774Sraj /* Set soft reset bit */ 660176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 661176774Sraj maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 662176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 663176774Sraj 664176774Sraj /* Clear soft reset bit */ 665176774Sraj maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 666176774Sraj maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 667176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 668176774Sraj} 669176774Sraj 670176774Srajstatic void 671177111Srajtsec_watchdog(struct tsec_softc *sc) 672176774Sraj{ 673177111Sraj struct ifnet *ifp; 674176774Sraj 675177111Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 676176774Sraj 677182187Sraj if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 678177111Sraj return; 679177111Sraj 680177111Sraj ifp = sc->tsec_ifp; 681176774Sraj ifp->if_oerrors++; 682176774Sraj if_printf(ifp, "watchdog timeout\n"); 683176774Sraj 684176774Sraj tsec_stop(sc); 685176774Sraj tsec_init_locked(sc); 686176774Sraj} 687176774Sraj 688176774Srajstatic void 689176774Srajtsec_start(struct ifnet *ifp) 690176774Sraj{ 691176774Sraj struct tsec_softc *sc = ifp->if_softc; 692176774Sraj 693176774Sraj TSEC_TRANSMIT_LOCK(sc); 694176774Sraj tsec_start_locked(ifp); 695176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 696176774Sraj} 697176774Sraj 698176774Srajstatic void 699176774Srajtsec_start_locked(struct ifnet *ifp) 700176774Sraj{ 701176774Sraj struct tsec_softc *sc; 702188711Sraj struct mbuf *m0, *mtmp; 703188711Sraj struct tsec_tx_fcb *tx_fcb; 704176774Sraj unsigned int queued = 0; 705188711Sraj int csum_flags, fcb_inserted = 0; 706176774Sraj 707176774Sraj sc = ifp->if_softc; 708176774Sraj 709176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 710176774Sraj 711176774Sraj if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 712176774Sraj IFF_DRV_RUNNING) 713176774Sraj return; 714176774Sraj 715176774Sraj if (sc->tsec_link == 0) 716176774Sraj return; 717176774Sraj 718188712Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 719188712Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 720176774Sraj 721199580Sraj while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 722176774Sraj /* Get packet from the queue */ 723199580Sraj IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 724176774Sraj if (m0 == NULL) 725176774Sraj break; 726176774Sraj 727188711Sraj /* Insert TCP/IP Off-load frame control block */ 728188711Sraj csum_flags = m0->m_pkthdr.csum_flags; 729188711Sraj if (csum_flags) { 730188711Sraj 731248078Smarius M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT); 732188711Sraj if (m0 == NULL) 733188711Sraj break; 734188711Sraj 735188711Sraj tx_fcb = mtod(m0, struct tsec_tx_fcb *); 736188711Sraj tx_fcb->flags = 0; 737188711Sraj tx_fcb->l3_offset = ETHER_HDR_LEN; 738188711Sraj tx_fcb->l4_offset = sizeof(struct ip); 739188711Sraj 740188711Sraj if (csum_flags & CSUM_IP) 741188711Sraj tx_fcb->flags |= TSEC_TX_FCB_IP4 | 742188711Sraj TSEC_TX_FCB_CSUM_IP; 743188711Sraj 744188711Sraj if (csum_flags & CSUM_TCP) 745188711Sraj tx_fcb->flags |= TSEC_TX_FCB_TCP | 746188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 747188711Sraj 748188711Sraj if (csum_flags & CSUM_UDP) 749188711Sraj tx_fcb->flags |= TSEC_TX_FCB_UDP | 750188711Sraj TSEC_TX_FCB_CSUM_TCP_UDP; 751188711Sraj 752188711Sraj fcb_inserted = 1; 753188711Sraj } 754188711Sraj 755248078Smarius mtmp = m_defrag(m0, M_NOWAIT); 756176774Sraj if (mtmp) 757176774Sraj m0 = mtmp; 758176774Sraj 759188711Sraj if (tsec_encap(sc, m0, fcb_inserted)) { 760199580Sraj IFQ_DRV_PREPEND(&ifp->if_snd, m0); 761176774Sraj ifp->if_drv_flags |= IFF_DRV_OACTIVE; 762176774Sraj break; 763176774Sraj } 764176774Sraj queued++; 765176774Sraj BPF_MTAP(ifp, m0); 766176774Sraj } 767188712Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 768188712Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 769176774Sraj 770176774Sraj if (queued) { 771176774Sraj /* Enable transmitter and watchdog timer */ 772176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 773182187Sraj sc->tsec_watchdog = 5; 774176774Sraj } 775176774Sraj} 776176774Sraj 777176774Srajstatic int 778188711Srajtsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 779176774Sraj{ 780176774Sraj struct tsec_desc *tx_desc = NULL; 781176774Sraj struct ifnet *ifp; 782176774Sraj bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 783176774Sraj bus_dmamap_t *mapp; 784188711Sraj int csum_flag = 0, error, seg, nsegs; 785176774Sraj 786176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 787176774Sraj 788176774Sraj ifp = sc->tsec_ifp; 789176774Sraj 790176774Sraj if (TSEC_FREE_TX_DESC(sc) == 0) { 791176774Sraj /* No free descriptors */ 792176774Sraj return (-1); 793176774Sraj } 794176774Sraj 795176774Sraj /* Fetch unused map */ 796176774Sraj mapp = TSEC_ALLOC_TX_MAP(sc); 797176774Sraj 798176774Sraj /* Create mapping in DMA memory */ 799176774Sraj error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 800188712Sraj *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 801176774Sraj if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 802176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 803176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 804176774Sraj return ((error != 0) ? error : -1); 805176774Sraj } 806176774Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 807176774Sraj 808176774Sraj if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 809176774Sraj if_printf(ifp, "TX buffer has %d segments\n", nsegs); 810176774Sraj 811188711Sraj if (fcb_inserted) 812188711Sraj csum_flag = TSEC_TXBD_TOE; 813188711Sraj 814176774Sraj /* Everything is ok, now we can send buffers */ 815176774Sraj for (seg = 0; seg < nsegs; seg++) { 816176774Sraj tx_desc = TSEC_GET_CUR_TX_DESC(sc); 817176774Sraj 818176774Sraj tx_desc->length = segs[seg].ds_len; 819176774Sraj tx_desc->bufptr = segs[seg].ds_addr; 820176774Sraj 821188711Sraj /* 822188711Sraj * Set flags: 823188711Sraj * - wrap 824188711Sraj * - checksum 825188711Sraj * - ready to send 826188711Sraj * - transmit the CRC sequence after the last data byte 827188711Sraj * - interrupt after the last buffer 828188711Sraj */ 829176774Sraj tx_desc->flags = 830188711Sraj (tx_desc->flags & TSEC_TXBD_W) | 831188711Sraj ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 832188711Sraj ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 833176774Sraj } 834176774Sraj 835176774Sraj /* Save mbuf and DMA mapping for release at later stage */ 836176774Sraj TSEC_PUT_TX_MBUF(sc, m0); 837176774Sraj TSEC_PUT_TX_MAP(sc, mapp); 838176774Sraj 839176774Sraj return (0); 840176774Sraj} 841176774Sraj 842176774Srajstatic void 843176774Srajtsec_setfilter(struct tsec_softc *sc) 844176774Sraj{ 845176774Sraj struct ifnet *ifp; 846176774Sraj uint32_t flags; 847176774Sraj 848176774Sraj ifp = sc->tsec_ifp; 849176774Sraj flags = TSEC_READ(sc, TSEC_REG_RCTRL); 850176774Sraj 851176774Sraj /* Promiscuous mode */ 852176774Sraj if (ifp->if_flags & IFF_PROMISC) 853176774Sraj flags |= TSEC_RCTRL_PROM; 854176774Sraj else 855176774Sraj flags &= ~TSEC_RCTRL_PROM; 856176774Sraj 857176774Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 858176774Sraj} 859176774Sraj 860188711Sraj#ifdef DEVICE_POLLING 861188711Srajstatic poll_handler_t tsec_poll; 862188711Sraj 863193096Sattiliostatic int 864188711Srajtsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 865188711Sraj{ 866188711Sraj uint32_t ie; 867188711Sraj struct tsec_softc *sc = ifp->if_softc; 868193096Sattilio int rx_npkts; 869188711Sraj 870193096Sattilio rx_npkts = 0; 871193096Sattilio 872188711Sraj TSEC_GLOBAL_LOCK(sc); 873188711Sraj if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 874188711Sraj TSEC_GLOBAL_UNLOCK(sc); 875193096Sattilio return (rx_npkts); 876188711Sraj } 877188711Sraj 878188711Sraj if (cmd == POLL_AND_CHECK_STATUS) { 879188715Sraj tsec_error_intr_locked(sc, count); 880188711Sraj 881188711Sraj /* Clear all events reported */ 882188715Sraj ie = TSEC_READ(sc, TSEC_REG_IEVENT); 883188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 884188711Sraj } 885188711Sraj 886188711Sraj tsec_transmit_intr_locked(sc); 887188711Sraj 888188711Sraj TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 889188711Sraj 890193096Sattilio rx_npkts = tsec_receive_intr_locked(sc, count); 891188711Sraj 892188711Sraj TSEC_RECEIVE_UNLOCK(sc); 893193096Sattilio 894193096Sattilio return (rx_npkts); 895188711Sraj} 896188711Sraj#endif /* DEVICE_POLLING */ 897188711Sraj 898176774Srajstatic int 899176774Srajtsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 900176774Sraj{ 901176774Sraj struct tsec_softc *sc = ifp->if_softc; 902176774Sraj struct ifreq *ifr = (struct ifreq *)data; 903176774Sraj device_t dev; 904188711Sraj int mask, error = 0; 905176774Sraj 906176774Sraj dev = sc->dev; 907176774Sraj 908176774Sraj switch (command) { 909188711Sraj case SIOCSIFMTU: 910188711Sraj TSEC_GLOBAL_LOCK(sc); 911188711Sraj if (tsec_set_mtu(sc, ifr->ifr_mtu)) 912188711Sraj ifp->if_mtu = ifr->ifr_mtu; 913188711Sraj else 914188711Sraj error = EINVAL; 915188711Sraj TSEC_GLOBAL_UNLOCK(sc); 916188711Sraj break; 917176774Sraj case SIOCSIFFLAGS: 918176774Sraj TSEC_GLOBAL_LOCK(sc); 919176774Sraj if (ifp->if_flags & IFF_UP) { 920176774Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 921188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 922188711Sraj IFF_PROMISC) 923176774Sraj tsec_setfilter(sc); 924188711Sraj 925188711Sraj if ((sc->tsec_if_flags ^ ifp->if_flags) & 926188711Sraj IFF_ALLMULTI) 927188711Sraj tsec_setup_multicast(sc); 928176774Sraj } else 929176774Sraj tsec_init_locked(sc); 930182189Sraj } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 931182189Sraj tsec_stop(sc); 932182189Sraj 933176774Sraj sc->tsec_if_flags = ifp->if_flags; 934176774Sraj TSEC_GLOBAL_UNLOCK(sc); 935176774Sraj break; 936188711Sraj case SIOCADDMULTI: 937188711Sraj case SIOCDELMULTI: 938188711Sraj if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 939188711Sraj TSEC_GLOBAL_LOCK(sc); 940188711Sraj tsec_setup_multicast(sc); 941188711Sraj TSEC_GLOBAL_UNLOCK(sc); 942188711Sraj } 943176774Sraj case SIOCGIFMEDIA: 944176774Sraj case SIOCSIFMEDIA: 945188711Sraj error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 946188711Sraj command); 947176774Sraj break; 948188711Sraj case SIOCSIFCAP: 949188711Sraj mask = ifp->if_capenable ^ ifr->ifr_reqcap; 950188711Sraj if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 951188711Sraj TSEC_GLOBAL_LOCK(sc); 952188711Sraj ifp->if_capenable &= ~IFCAP_HWCSUM; 953188711Sraj ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 954188711Sraj tsec_offload_setup(sc); 955188711Sraj TSEC_GLOBAL_UNLOCK(sc); 956188711Sraj } 957188711Sraj#ifdef DEVICE_POLLING 958188711Sraj if (mask & IFCAP_POLLING) { 959188711Sraj if (ifr->ifr_reqcap & IFCAP_POLLING) { 960188711Sraj error = ether_poll_register(tsec_poll, ifp); 961188711Sraj if (error) 962188711Sraj return (error); 963188711Sraj 964188711Sraj TSEC_GLOBAL_LOCK(sc); 965188711Sraj /* Disable interrupts */ 966188711Sraj tsec_intrs_ctl(sc, 0); 967188711Sraj ifp->if_capenable |= IFCAP_POLLING; 968188711Sraj TSEC_GLOBAL_UNLOCK(sc); 969188711Sraj } else { 970188711Sraj error = ether_poll_deregister(ifp); 971188711Sraj TSEC_GLOBAL_LOCK(sc); 972188711Sraj /* Enable interrupts */ 973188711Sraj tsec_intrs_ctl(sc, 1); 974188711Sraj ifp->if_capenable &= ~IFCAP_POLLING; 975188711Sraj TSEC_GLOBAL_UNLOCK(sc); 976188711Sraj } 977188711Sraj } 978188711Sraj#endif 979188719Sraj break; 980188711Sraj 981176774Sraj default: 982176774Sraj error = ether_ioctl(ifp, command, data); 983176774Sraj } 984176774Sraj 985176774Sraj /* Flush buffers if not empty */ 986176774Sraj if (ifp->if_flags & IFF_UP) 987176774Sraj tsec_start(ifp); 988176774Sraj return (error); 989176774Sraj} 990176774Sraj 991176774Srajstatic int 992176774Srajtsec_ifmedia_upd(struct ifnet *ifp) 993176774Sraj{ 994176774Sraj struct tsec_softc *sc = ifp->if_softc; 995176774Sraj struct mii_data *mii; 996176774Sraj 997176774Sraj TSEC_TRANSMIT_LOCK(sc); 998176774Sraj 999176774Sraj mii = sc->tsec_mii; 1000176774Sraj mii_mediachg(mii); 1001176774Sraj 1002176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 1003176774Sraj return (0); 1004176774Sraj} 1005176774Sraj 1006176774Srajstatic void 1007176774Srajtsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1008176774Sraj{ 1009176774Sraj struct tsec_softc *sc = ifp->if_softc; 1010176774Sraj struct mii_data *mii; 1011176774Sraj 1012176774Sraj TSEC_TRANSMIT_LOCK(sc); 1013176774Sraj 1014176774Sraj mii = sc->tsec_mii; 1015176774Sraj mii_pollstat(mii); 1016176774Sraj 1017176774Sraj ifmr->ifm_active = mii->mii_media_active; 1018176774Sraj ifmr->ifm_status = mii->mii_media_status; 1019176774Sraj 1020176774Sraj TSEC_TRANSMIT_UNLOCK(sc); 1021176774Sraj} 1022176774Sraj 1023176774Srajstatic int 1024176774Srajtsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1025182189Sraj uint32_t *paddr) 1026176774Sraj{ 1027176774Sraj struct mbuf *new_mbuf; 1028176774Sraj bus_dma_segment_t seg[1]; 1029188711Sraj int error, nsegs; 1030176774Sraj 1031176774Sraj KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1032176774Sraj 1033248078Smarius new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1034176774Sraj if (new_mbuf == NULL) 1035176774Sraj return (ENOBUFS); 1036176774Sraj new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1037176774Sraj 1038176774Sraj if (*mbufp) { 1039176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1040176774Sraj bus_dmamap_unload(tag, map); 1041176774Sraj } 1042176774Sraj 1043176774Sraj error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1044188712Sraj BUS_DMA_NOWAIT); 1045176774Sraj KASSERT(nsegs == 1, ("Too many segments returned!")); 1046176774Sraj if (nsegs != 1 || error) 1047176774Sraj panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1048176774Sraj 1049176774Sraj#if 0 1050176774Sraj if (error) { 1051176774Sraj printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1052176774Sraj error); 1053176774Sraj m_freem(new_mbuf); 1054176774Sraj return (ENOBUFS); 1055176774Sraj } 1056176774Sraj#endif 1057176774Sraj 1058176774Sraj#if 0 1059176774Sraj KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1060176774Sraj ("Wrong alignment of RX buffer!")); 1061176774Sraj#endif 1062176774Sraj bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1063176774Sraj 1064176774Sraj (*mbufp) = new_mbuf; 1065176774Sraj (*paddr) = seg->ds_addr; 1066176774Sraj return (0); 1067176774Sraj} 1068176774Sraj 1069176774Srajstatic void 1070176774Srajtsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1071176774Sraj{ 1072176774Sraj u_int32_t *paddr; 1073176774Sraj 1074176774Sraj KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1075176774Sraj paddr = arg; 1076176774Sraj *paddr = segs->ds_addr; 1077176774Sraj} 1078176774Sraj 1079176774Srajstatic int 1080176774Srajtsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1081176774Sraj bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1082176774Sraj{ 1083176774Sraj int error; 1084176774Sraj 1085176774Sraj /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1086176774Sraj error = bus_dma_tag_create(NULL, /* parent */ 1087176774Sraj PAGE_SIZE, 0, /* alignment, boundary */ 1088176774Sraj BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1089176774Sraj BUS_SPACE_MAXADDR, /* highaddr */ 1090176774Sraj NULL, NULL, /* filtfunc, filtfuncarg */ 1091176774Sraj dsize, 1, /* maxsize, nsegments */ 1092176774Sraj dsize, 0, /* maxsegsz, flags */ 1093176774Sraj NULL, NULL, /* lockfunc, lockfuncarg */ 1094176774Sraj dtag); /* dmat */ 1095176774Sraj 1096176774Sraj if (error) { 1097188712Sraj device_printf(dev, "failed to allocate busdma %s tag\n", 1098188712Sraj dname); 1099176774Sraj (*vaddr) = NULL; 1100176774Sraj return (ENXIO); 1101176774Sraj } 1102176774Sraj 1103176774Sraj error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1104188712Sraj dmap); 1105176774Sraj if (error) { 1106176774Sraj device_printf(dev, "failed to allocate %s DMA safe memory\n", 1107188712Sraj dname); 1108176774Sraj bus_dma_tag_destroy(*dtag); 1109176774Sraj (*vaddr) = NULL; 1110176774Sraj return (ENXIO); 1111176774Sraj } 1112176774Sraj 1113188712Sraj error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1114188712Sraj tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1115176774Sraj if (error) { 1116188712Sraj device_printf(dev, "cannot get address of the %s " 1117188712Sraj "descriptors\n", dname); 1118176774Sraj bus_dmamem_free(*dtag, *vaddr, *dmap); 1119176774Sraj bus_dma_tag_destroy(*dtag); 1120176774Sraj (*vaddr) = NULL; 1121176774Sraj return (ENXIO); 1122176774Sraj } 1123176774Sraj 1124176774Sraj return (0); 1125176774Sraj} 1126176774Sraj 1127176774Srajstatic void 1128176774Srajtsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1129176774Sraj{ 1130176774Sraj 1131176774Sraj if (vaddr == NULL) 1132176774Sraj return; 1133176774Sraj 1134176774Sraj /* Unmap descriptors from DMA memory */ 1135188712Sraj bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1136188712Sraj BUS_DMASYNC_POSTWRITE); 1137176774Sraj bus_dmamap_unload(dtag, dmap); 1138176774Sraj 1139176774Sraj /* Free descriptors memory */ 1140176774Sraj bus_dmamem_free(dtag, vaddr, dmap); 1141176774Sraj 1142176774Sraj /* Destroy descriptors tag */ 1143176774Sraj bus_dma_tag_destroy(dtag); 1144176774Sraj} 1145176774Sraj 1146176774Srajstatic void 1147176774Srajtsec_free_dma(struct tsec_softc *sc) 1148176774Sraj{ 1149176774Sraj int i; 1150176774Sraj 1151176774Sraj /* Free TX maps */ 1152176774Sraj for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1153176774Sraj if (sc->tx_map_data[i] != NULL) 1154188712Sraj bus_dmamap_destroy(sc->tsec_tx_mtag, 1155188712Sraj sc->tx_map_data[i]); 1156188712Sraj /* Destroy tag for TX mbufs */ 1157176774Sraj bus_dma_tag_destroy(sc->tsec_tx_mtag); 1158176774Sraj 1159176774Sraj /* Free RX mbufs and maps */ 1160176774Sraj for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1161176774Sraj if (sc->rx_data[i].mbuf) { 1162176774Sraj /* Unload buffer from DMA */ 1163176774Sraj bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1164176774Sraj BUS_DMASYNC_POSTREAD); 1165188712Sraj bus_dmamap_unload(sc->tsec_rx_mtag, 1166188712Sraj sc->rx_data[i].map); 1167176774Sraj 1168176774Sraj /* Free buffer */ 1169176774Sraj m_freem(sc->rx_data[i].mbuf); 1170176774Sraj } 1171176774Sraj /* Destroy map for this buffer */ 1172176774Sraj if (sc->rx_data[i].map != NULL) 1173176774Sraj bus_dmamap_destroy(sc->tsec_rx_mtag, 1174176774Sraj sc->rx_data[i].map); 1175176774Sraj } 1176188712Sraj /* Destroy tag for RX mbufs */ 1177176774Sraj bus_dma_tag_destroy(sc->tsec_rx_mtag); 1178176774Sraj 1179176774Sraj /* Unload TX/RX descriptors */ 1180176774Sraj tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1181176774Sraj sc->tsec_tx_vaddr); 1182176774Sraj tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1183176774Sraj sc->tsec_rx_vaddr); 1184176774Sraj} 1185176774Sraj 1186176774Srajstatic void 1187176774Srajtsec_stop(struct tsec_softc *sc) 1188176774Sraj{ 1189176774Sraj struct ifnet *ifp; 1190176774Sraj struct mbuf *m0; 1191176774Sraj bus_dmamap_t *mapp; 1192176774Sraj uint32_t tmpval; 1193176774Sraj 1194176774Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1195176774Sraj 1196176774Sraj ifp = sc->tsec_ifp; 1197176774Sraj 1198188712Sraj /* Disable interface and watchdog timer */ 1199182187Sraj callout_stop(&sc->tsec_callout); 1200176774Sraj ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1201182187Sraj sc->tsec_watchdog = 0; 1202176774Sraj 1203176774Sraj /* Disable all interrupts and stop DMA */ 1204176774Sraj tsec_intrs_ctl(sc, 0); 1205176774Sraj tsec_dma_ctl(sc, 0); 1206176774Sraj 1207176774Sraj /* Remove pending data from TX queue */ 1208176774Sraj while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1209176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1210176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1211176774Sraj 1212188711Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1213188711Sraj BUS_DMASYNC_POSTWRITE); 1214176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1215176774Sraj 1216176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1217176774Sraj m_freem(m0); 1218176774Sraj } 1219176774Sraj 1220188711Sraj /* Disable RX and TX */ 1221176774Sraj tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1222176774Sraj tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1223176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1224176774Sraj DELAY(10); 1225176774Sraj} 1226176774Sraj 1227188711Srajstatic void 1228188711Srajtsec_tick(void *arg) 1229176774Sraj{ 1230176774Sraj struct tsec_softc *sc = arg; 1231188711Sraj struct ifnet *ifp; 1232188711Sraj int link; 1233188711Sraj 1234188711Sraj TSEC_GLOBAL_LOCK(sc); 1235188711Sraj 1236188711Sraj tsec_watchdog(sc); 1237188711Sraj 1238188711Sraj ifp = sc->tsec_ifp; 1239188711Sraj link = sc->tsec_link; 1240188711Sraj 1241188711Sraj mii_tick(sc->tsec_mii); 1242188711Sraj 1243188711Sraj if (link == 0 && sc->tsec_link == 1 && 1244188711Sraj (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1245188711Sraj tsec_start_locked(ifp); 1246188711Sraj 1247188711Sraj /* Schedule another timeout one second from now. */ 1248188711Sraj callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1249188711Sraj 1250188711Sraj TSEC_GLOBAL_UNLOCK(sc); 1251188711Sraj} 1252188711Sraj 1253188711Sraj/* 1254188711Sraj * This is the core RX routine. It replenishes mbufs in the descriptor and 1255188711Sraj * sends data which have been dma'ed into host memory to upper layer. 1256188711Sraj * 1257188711Sraj * Loops at most count times if count is > 0, or until done if count < 0. 1258188711Sraj */ 1259193096Sattiliostatic int 1260188711Srajtsec_receive_intr_locked(struct tsec_softc *sc, int count) 1261188711Sraj{ 1262176774Sraj struct tsec_desc *rx_desc; 1263176774Sraj struct ifnet *ifp; 1264176774Sraj struct rx_data_type *rx_data; 1265176774Sraj struct mbuf *m; 1266176774Sraj device_t dev; 1267176774Sraj uint32_t i; 1268193096Sattilio int c, rx_npkts; 1269176774Sraj uint16_t flags; 1270176774Sraj 1271188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1272188711Sraj 1273176774Sraj ifp = sc->tsec_ifp; 1274176774Sraj rx_data = sc->rx_data; 1275176774Sraj dev = sc->dev; 1276193096Sattilio rx_npkts = 0; 1277176774Sraj 1278188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1279188711Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1280176774Sraj 1281188711Sraj for (c = 0; ; c++) { 1282188711Sraj if (count >= 0 && count-- == 0) 1283188711Sraj break; 1284176774Sraj 1285176774Sraj rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1286176774Sraj flags = rx_desc->flags; 1287176774Sraj 1288176774Sraj /* Check if there is anything to receive */ 1289188711Sraj if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1290176774Sraj /* 1291176774Sraj * Avoid generating another interrupt 1292176774Sraj */ 1293176774Sraj if (flags & TSEC_RXBD_E) 1294176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, 1295176774Sraj TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1296176774Sraj /* 1297176774Sraj * We didn't consume current descriptor and have to 1298176774Sraj * return it to the queue 1299176774Sraj */ 1300176774Sraj TSEC_BACK_CUR_RX_DESC(sc); 1301176774Sraj break; 1302176774Sraj } 1303176774Sraj 1304176774Sraj if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1305176774Sraj TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1306182189Sraj 1307176774Sraj rx_desc->length = 0; 1308188711Sraj rx_desc->flags = (rx_desc->flags & 1309188711Sraj ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1310188711Sraj 1311188711Sraj if (sc->frame != NULL) { 1312188711Sraj m_free(sc->frame); 1313188711Sraj sc->frame = NULL; 1314188711Sraj } 1315188711Sraj 1316176774Sraj continue; 1317176774Sraj } 1318176774Sraj 1319176774Sraj /* Ok... process frame */ 1320176774Sraj i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1321176774Sraj m = rx_data[i].mbuf; 1322188711Sraj m->m_len = rx_desc->length; 1323176774Sraj 1324188711Sraj if (sc->frame != NULL) { 1325188711Sraj if ((flags & TSEC_RXBD_L) != 0) 1326188711Sraj m->m_len -= m_length(sc->frame, NULL); 1327188711Sraj 1328188711Sraj m->m_flags &= ~M_PKTHDR; 1329188711Sraj m_cat(sc->frame, m); 1330188711Sraj } else { 1331188711Sraj sc->frame = m; 1332188711Sraj } 1333188711Sraj 1334188711Sraj m = NULL; 1335188711Sraj 1336188711Sraj if ((flags & TSEC_RXBD_L) != 0) { 1337188711Sraj m = sc->frame; 1338188711Sraj sc->frame = NULL; 1339188711Sraj } 1340188711Sraj 1341176774Sraj if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1342176774Sraj &rx_data[i].mbuf, &rx_data[i].paddr)) { 1343176774Sraj ifp->if_ierrors++; 1344188713Sraj /* 1345188713Sraj * We ran out of mbufs; didn't consume current 1346188713Sraj * descriptor and have to return it to the queue. 1347188713Sraj */ 1348188713Sraj TSEC_BACK_CUR_RX_DESC(sc); 1349188713Sraj break; 1350176774Sraj } 1351188711Sraj 1352188711Sraj /* Attach new buffer to descriptor and clear flags */ 1353176774Sraj rx_desc->bufptr = rx_data[i].paddr; 1354176774Sraj rx_desc->length = 0; 1355176774Sraj rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1356176774Sraj TSEC_RXBD_E | TSEC_RXBD_I; 1357176774Sraj 1358188711Sraj if (m != NULL) { 1359188711Sraj m->m_pkthdr.rcvif = ifp; 1360176774Sraj 1361188711Sraj m_fixhdr(m); 1362188711Sraj m_adj(m, -ETHER_CRC_LEN); 1363176774Sraj 1364188711Sraj if (sc->is_etsec) 1365188711Sraj tsec_offload_process_frame(sc, m); 1366176774Sraj 1367188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1368188711Sraj (*ifp->if_input)(ifp, m); 1369188711Sraj TSEC_RECEIVE_LOCK(sc); 1370193096Sattilio rx_npkts++; 1371188711Sraj } 1372188711Sraj } 1373176774Sraj 1374188711Sraj bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1375188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1376188718Sraj 1377188718Sraj /* 1378188718Sraj * Make sure TSEC receiver is not halted. 1379188718Sraj * 1380188718Sraj * Various conditions can stop the TSEC receiver, but not all are 1381188718Sraj * signaled and handled by error interrupt, so make sure the receiver 1382188718Sraj * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1383188718Sraj * halted, and is harmless if already running. 1384188718Sraj */ 1385188718Sraj TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1386193096Sattilio return (rx_npkts); 1387176774Sraj} 1388176774Sraj 1389182189Srajvoid 1390188711Srajtsec_receive_intr(void *arg) 1391176774Sraj{ 1392176774Sraj struct tsec_softc *sc = arg; 1393188711Sraj 1394188711Sraj TSEC_RECEIVE_LOCK(sc); 1395188711Sraj 1396188711Sraj#ifdef DEVICE_POLLING 1397188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1398188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1399188711Sraj return; 1400188711Sraj } 1401188711Sraj#endif 1402188711Sraj 1403188711Sraj /* Confirm the interrupt was received by driver */ 1404188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1405188711Sraj tsec_receive_intr_locked(sc, -1); 1406188711Sraj 1407188711Sraj TSEC_RECEIVE_UNLOCK(sc); 1408188711Sraj} 1409188711Sraj 1410188711Srajstatic void 1411188711Srajtsec_transmit_intr_locked(struct tsec_softc *sc) 1412188711Sraj{ 1413176774Sraj struct tsec_desc *tx_desc; 1414176774Sraj struct ifnet *ifp; 1415176774Sraj struct mbuf *m0; 1416176774Sraj bus_dmamap_t *mapp; 1417176774Sraj int send = 0; 1418176774Sraj 1419188711Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); 1420188711Sraj 1421176774Sraj ifp = sc->tsec_ifp; 1422176774Sraj 1423176774Sraj /* Update collision statistics */ 1424176774Sraj ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1425176774Sraj 1426176774Sraj /* Reset collision counters in hardware */ 1427176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1428176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1429176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1430176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1431176774Sraj TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1432176774Sraj 1433182189Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1434182189Sraj BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1435176774Sraj 1436176774Sraj while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1437176774Sraj tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1438176774Sraj if (tx_desc->flags & TSEC_TXBD_R) { 1439176774Sraj TSEC_BACK_DIRTY_TX_DESC(sc); 1440176774Sraj break; 1441176774Sraj } 1442176774Sraj 1443176774Sraj if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1444176774Sraj continue; 1445176774Sraj 1446176774Sraj /* 1447176774Sraj * This is the last buf in this packet, so unmap and free it. 1448176774Sraj */ 1449176774Sraj m0 = TSEC_GET_TX_MBUF(sc); 1450176774Sraj mapp = TSEC_GET_TX_MAP(sc); 1451176774Sraj 1452188712Sraj bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1453188712Sraj BUS_DMASYNC_POSTWRITE); 1454176774Sraj bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1455176774Sraj 1456176774Sraj TSEC_FREE_TX_MAP(sc, mapp); 1457176774Sraj m_freem(m0); 1458176774Sraj 1459176774Sraj ifp->if_opackets++; 1460176774Sraj send = 1; 1461176774Sraj } 1462188711Sraj bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1463188711Sraj BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1464176774Sraj 1465176774Sraj if (send) { 1466176774Sraj /* Now send anything that was pending */ 1467176774Sraj ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1468176774Sraj tsec_start_locked(ifp); 1469176774Sraj 1470188711Sraj /* Stop wathdog if all sent */ 1471176774Sraj if (TSEC_EMPTYQ_TX_MBUF(sc)) 1472182187Sraj sc->tsec_watchdog = 0; 1473176774Sraj } 1474176774Sraj} 1475176774Sraj 1476182189Srajvoid 1477188711Srajtsec_transmit_intr(void *arg) 1478176774Sraj{ 1479176774Sraj struct tsec_softc *sc = arg; 1480188711Sraj 1481188711Sraj TSEC_TRANSMIT_LOCK(sc); 1482188711Sraj 1483188711Sraj#ifdef DEVICE_POLLING 1484188711Sraj if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1485188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1486188711Sraj return; 1487188711Sraj } 1488188711Sraj#endif 1489188711Sraj /* Confirm the interrupt was received by driver */ 1490188711Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1491188711Sraj tsec_transmit_intr_locked(sc); 1492188711Sraj 1493188711Sraj TSEC_TRANSMIT_UNLOCK(sc); 1494188711Sraj} 1495188711Sraj 1496188711Srajstatic void 1497188711Srajtsec_error_intr_locked(struct tsec_softc *sc, int count) 1498188711Sraj{ 1499176774Sraj struct ifnet *ifp; 1500176774Sraj uint32_t eflags; 1501176774Sraj 1502188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1503188711Sraj 1504176774Sraj ifp = sc->tsec_ifp; 1505176774Sraj 1506176774Sraj eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1507176774Sraj 1508176774Sraj /* Clear events bits in hardware */ 1509176774Sraj TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1510176774Sraj TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1511176774Sraj TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1512176774Sraj TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1513176774Sraj 1514176774Sraj /* Check transmitter errors */ 1515176774Sraj if (eflags & TSEC_IEVENT_TXE) { 1516176774Sraj ifp->if_oerrors++; 1517176774Sraj 1518176774Sraj if (eflags & TSEC_IEVENT_LC) 1519176774Sraj ifp->if_collisions++; 1520176774Sraj 1521176774Sraj TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1522176774Sraj } 1523176774Sraj 1524176774Sraj /* Check receiver errors */ 1525176774Sraj if (eflags & TSEC_IEVENT_BSY) { 1526176774Sraj ifp->if_ierrors++; 1527176774Sraj ifp->if_iqdrops++; 1528176774Sraj 1529176774Sraj /* Get data from RX buffers */ 1530188711Sraj tsec_receive_intr_locked(sc, count); 1531176774Sraj } 1532188711Sraj 1533188711Sraj if (ifp->if_flags & IFF_DEBUG) 1534188711Sraj if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1535188711Sraj eflags); 1536188711Sraj 1537188711Sraj if (eflags & TSEC_IEVENT_EBERR) { 1538188711Sraj if_printf(ifp, "System bus error occurred during" 1539188711Sraj "DMA transaction (flags: 0x%x)\n", eflags); 1540188711Sraj tsec_init_locked(sc); 1541188711Sraj } 1542188711Sraj 1543188711Sraj if (eflags & TSEC_IEVENT_BABT) 1544188711Sraj ifp->if_oerrors++; 1545188711Sraj 1546176774Sraj if (eflags & TSEC_IEVENT_BABR) 1547176774Sraj ifp->if_ierrors++; 1548176774Sraj} 1549176774Sraj 1550188711Srajvoid 1551188711Srajtsec_error_intr(void *arg) 1552176774Sraj{ 1553188711Sraj struct tsec_softc *sc = arg; 1554176774Sraj 1555177111Sraj TSEC_GLOBAL_LOCK(sc); 1556188711Sraj tsec_error_intr_locked(sc, -1); 1557177111Sraj TSEC_GLOBAL_UNLOCK(sc); 1558176774Sraj} 1559176774Sraj 1560182189Srajint 1561176774Srajtsec_miibus_readreg(device_t dev, int phy, int reg) 1562176774Sraj{ 1563176774Sraj struct tsec_softc *sc; 1564176774Sraj uint32_t timeout; 1565176774Sraj 1566233015Sraj sc = device_get_softc(dev); 1567176774Sraj 1568233015Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1569233015Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, 0); 1570233015Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1571176774Sraj 1572176774Sraj timeout = TSEC_READ_RETRY; 1573233015Sraj while (--timeout && TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & 1574176774Sraj (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1575176774Sraj DELAY(TSEC_READ_DELAY); 1576176774Sraj 1577176774Sraj if (timeout == 0) 1578176774Sraj device_printf(dev, "Timeout while reading from PHY!\n"); 1579176774Sraj 1580233015Sraj return (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMSTAT)); 1581176774Sraj} 1582176774Sraj 1583194101Srajint 1584176774Srajtsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1585176774Sraj{ 1586176774Sraj struct tsec_softc *sc; 1587176774Sraj uint32_t timeout; 1588176774Sraj 1589233015Sraj sc = device_get_softc(dev); 1590176774Sraj 1591233015Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1592233015Sraj TSEC_WRITE(sc->phy_sc, TSEC_REG_MIIMCON, value); 1593176774Sraj 1594176774Sraj timeout = TSEC_READ_RETRY; 1595233015Sraj while (--timeout && (TSEC_READ(sc->phy_sc, TSEC_REG_MIIMIND) & 1596188712Sraj TSEC_MIIMIND_BUSY)) 1597176774Sraj DELAY(TSEC_READ_DELAY); 1598176774Sraj 1599176774Sraj if (timeout == 0) 1600176774Sraj device_printf(dev, "Timeout while writing to PHY!\n"); 1601194101Sraj 1602194101Sraj return (0); 1603176774Sraj} 1604176774Sraj 1605182189Srajvoid 1606176774Srajtsec_miibus_statchg(device_t dev) 1607176774Sraj{ 1608176774Sraj struct tsec_softc *sc; 1609176774Sraj struct mii_data *mii; 1610176774Sraj uint32_t ecntrl, id, tmp; 1611176774Sraj int link; 1612176774Sraj 1613176774Sraj sc = device_get_softc(dev); 1614176774Sraj mii = sc->tsec_mii; 1615176774Sraj link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1616176774Sraj 1617176774Sraj tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1618176774Sraj 1619176774Sraj if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1620176774Sraj tmp |= TSEC_MACCFG2_FULLDUPLEX; 1621176774Sraj else 1622176774Sraj tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1623176774Sraj 1624176774Sraj switch (IFM_SUBTYPE(mii->mii_media_active)) { 1625176774Sraj case IFM_1000_T: 1626176774Sraj case IFM_1000_SX: 1627176774Sraj tmp |= TSEC_MACCFG2_GMII; 1628176774Sraj sc->tsec_link = link; 1629176774Sraj break; 1630176774Sraj case IFM_100_TX: 1631176774Sraj case IFM_10_T: 1632176774Sraj tmp |= TSEC_MACCFG2_MII; 1633176774Sraj sc->tsec_link = link; 1634176774Sraj break; 1635176774Sraj case IFM_NONE: 1636176774Sraj if (link) 1637188712Sraj device_printf(dev, "No speed selected but link " 1638188712Sraj "active!\n"); 1639176774Sraj sc->tsec_link = 0; 1640176774Sraj return; 1641176774Sraj default: 1642176774Sraj sc->tsec_link = 0; 1643176774Sraj device_printf(dev, "Unknown speed (%d), link %s!\n", 1644176774Sraj IFM_SUBTYPE(mii->mii_media_active), 1645182189Sraj ((link) ? "up" : "down")); 1646176774Sraj return; 1647176774Sraj } 1648176774Sraj TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1649176774Sraj 1650176774Sraj /* XXX kludge - use circumstantial evidence for reduced mode. */ 1651176774Sraj id = TSEC_READ(sc, TSEC_REG_ID2); 1652176774Sraj if (id & 0xffff) { 1653176774Sraj ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1654176774Sraj ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1655176774Sraj TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1656176774Sraj } 1657176774Sraj} 1658188711Sraj 1659188711Srajstatic void 1660188711Srajtsec_add_sysctls(struct tsec_softc *sc) 1661188711Sraj{ 1662188711Sraj struct sysctl_ctx_list *ctx; 1663188711Sraj struct sysctl_oid_list *children; 1664188711Sraj struct sysctl_oid *tree; 1665188711Sraj 1666188711Sraj ctx = device_get_sysctl_ctx(sc->dev); 1667188711Sraj children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1668188711Sraj tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1669188711Sraj CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1670188711Sraj children = SYSCTL_CHILDREN(tree); 1671188711Sraj 1672188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1673188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1674188711Sraj "I", "IC RX time threshold (0-65535)"); 1675188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1676188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1677188711Sraj "I", "IC RX frame count threshold (0-255)"); 1678188711Sraj 1679188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1680188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1681188711Sraj "I", "IC TX time threshold (0-65535)"); 1682188711Sraj SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1683188711Sraj CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1684188711Sraj "I", "IC TX frame count threshold (0-255)"); 1685188711Sraj} 1686188711Sraj 1687188711Sraj/* 1688188711Sraj * With Interrupt Coalescing (IC) active, a transmit/receive frame 1689188711Sraj * interrupt is raised either upon: 1690188711Sraj * 1691188711Sraj * - threshold-defined period of time elapsed, or 1692188711Sraj * - threshold-defined number of frames is received/transmitted, 1693188711Sraj * whichever occurs first. 1694188711Sraj * 1695188711Sraj * The following sysctls regulate IC behaviour (for TX/RX separately): 1696188711Sraj * 1697188711Sraj * dev.tsec.<unit>.int_coal.rx_time 1698188711Sraj * dev.tsec.<unit>.int_coal.rx_count 1699188711Sraj * dev.tsec.<unit>.int_coal.tx_time 1700188711Sraj * dev.tsec.<unit>.int_coal.tx_count 1701188711Sraj * 1702188711Sraj * Values: 1703188711Sraj * 1704188711Sraj * - 0 for either time or count disables IC on the given TX/RX path 1705188711Sraj * 1706188711Sraj * - count: 1-255 (expresses frame count number; note that value of 1 is 1707188711Sraj * effectively IC off) 1708188711Sraj * 1709188711Sraj * - time: 1-65535 (value corresponds to a real time period and is 1710188711Sraj * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1711188711Sraj * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1712188711Sraj * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1713188711Sraj * TSEC reference manual. 1714188711Sraj */ 1715188711Srajstatic int 1716188711Srajtsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1717188711Sraj{ 1718188711Sraj int error; 1719188711Sraj uint32_t time; 1720188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1721188711Sraj 1722188711Sraj time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1723188711Sraj 1724188711Sraj error = sysctl_handle_int(oidp, &time, 0, req); 1725188711Sraj if (error != 0) 1726188711Sraj return (error); 1727188711Sraj 1728188711Sraj if (time > 65535) 1729188711Sraj return (EINVAL); 1730188711Sraj 1731188711Sraj TSEC_IC_LOCK(sc); 1732188711Sraj if (arg2 == TSEC_IC_RX) { 1733188711Sraj sc->rx_ic_time = time; 1734188711Sraj tsec_set_rxic(sc); 1735188711Sraj } else { 1736188711Sraj sc->tx_ic_time = time; 1737188711Sraj tsec_set_txic(sc); 1738188711Sraj } 1739188711Sraj TSEC_IC_UNLOCK(sc); 1740188711Sraj 1741188711Sraj return (0); 1742188711Sraj} 1743188711Sraj 1744188711Srajstatic int 1745188711Srajtsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1746188711Sraj{ 1747188711Sraj int error; 1748188711Sraj uint32_t count; 1749188711Sraj struct tsec_softc *sc = (struct tsec_softc *)arg1; 1750188711Sraj 1751188711Sraj count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1752188711Sraj 1753188711Sraj error = sysctl_handle_int(oidp, &count, 0, req); 1754188711Sraj if (error != 0) 1755188711Sraj return (error); 1756188711Sraj 1757188711Sraj if (count > 255) 1758188711Sraj return (EINVAL); 1759188711Sraj 1760188711Sraj TSEC_IC_LOCK(sc); 1761188711Sraj if (arg2 == TSEC_IC_RX) { 1762188711Sraj sc->rx_ic_count = count; 1763188711Sraj tsec_set_rxic(sc); 1764188711Sraj } else { 1765188711Sraj sc->tx_ic_count = count; 1766188711Sraj tsec_set_txic(sc); 1767188711Sraj } 1768188711Sraj TSEC_IC_UNLOCK(sc); 1769188711Sraj 1770188711Sraj return (0); 1771188711Sraj} 1772188711Sraj 1773188711Srajstatic void 1774188711Srajtsec_set_rxic(struct tsec_softc *sc) 1775188711Sraj{ 1776188711Sraj uint32_t rxic_val; 1777188711Sraj 1778188711Sraj if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1779188711Sraj /* Disable RX IC */ 1780188711Sraj rxic_val = 0; 1781188711Sraj else { 1782188711Sraj rxic_val = 0x80000000; 1783188711Sraj rxic_val |= (sc->rx_ic_count << 21); 1784188711Sraj rxic_val |= sc->rx_ic_time; 1785188711Sraj } 1786188711Sraj 1787188711Sraj TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1788188711Sraj} 1789188711Sraj 1790188711Srajstatic void 1791188711Srajtsec_set_txic(struct tsec_softc *sc) 1792188711Sraj{ 1793188711Sraj uint32_t txic_val; 1794188711Sraj 1795188711Sraj if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1796188711Sraj /* Disable TX IC */ 1797188711Sraj txic_val = 0; 1798188711Sraj else { 1799188711Sraj txic_val = 0x80000000; 1800188711Sraj txic_val |= (sc->tx_ic_count << 21); 1801188711Sraj txic_val |= sc->tx_ic_time; 1802188711Sraj } 1803188711Sraj 1804188711Sraj TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1805188711Sraj} 1806188711Sraj 1807188711Srajstatic void 1808188711Srajtsec_offload_setup(struct tsec_softc *sc) 1809188711Sraj{ 1810188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1811188711Sraj uint32_t reg; 1812188711Sraj 1813188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1814188711Sraj 1815188711Sraj reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1816188711Sraj reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1817188711Sraj 1818188711Sraj if (ifp->if_capenable & IFCAP_TXCSUM) 1819188711Sraj ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1820188711Sraj else 1821188711Sraj ifp->if_hwassist = 0; 1822188711Sraj 1823188711Sraj TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1824188711Sraj 1825188711Sraj reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1826188711Sraj reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1827188711Sraj reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1828188711Sraj 1829188711Sraj if (ifp->if_capenable & IFCAP_RXCSUM) 1830188711Sraj reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1831188711Sraj TSEC_RCTRL_PRSDEP_PARSE_L234; 1832188711Sraj 1833188711Sraj TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1834188711Sraj} 1835188711Sraj 1836188711Sraj 1837188711Srajstatic void 1838188711Srajtsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1839188711Sraj{ 1840188711Sraj struct tsec_rx_fcb rx_fcb; 1841188711Sraj int csum_flags = 0; 1842188711Sraj int protocol, flags; 1843188711Sraj 1844188711Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); 1845188711Sraj 1846188711Sraj m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1847188711Sraj flags = rx_fcb.flags; 1848188711Sraj protocol = rx_fcb.protocol; 1849188711Sraj 1850188711Sraj if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1851188711Sraj csum_flags |= CSUM_IP_CHECKED; 1852188711Sraj 1853188711Sraj if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1854188711Sraj csum_flags |= CSUM_IP_VALID; 1855188711Sraj } 1856188711Sraj 1857188711Sraj if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1858188711Sraj TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1859188711Sraj (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1860188711Sraj 1861188711Sraj csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1862188711Sraj m->m_pkthdr.csum_data = 0xFFFF; 1863188711Sraj } 1864188711Sraj 1865188711Sraj m->m_pkthdr.csum_flags = csum_flags; 1866188711Sraj 1867188711Sraj if (flags & TSEC_RX_FCB_VLAN) { 1868188711Sraj m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1869188711Sraj m->m_flags |= M_VLANTAG; 1870188711Sraj } 1871188711Sraj 1872188711Sraj m_adj(m, sizeof(struct tsec_rx_fcb)); 1873188711Sraj} 1874188711Sraj 1875188711Srajstatic void 1876188711Srajtsec_setup_multicast(struct tsec_softc *sc) 1877188711Sraj{ 1878188711Sraj uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1879188711Sraj struct ifnet *ifp = sc->tsec_ifp; 1880188711Sraj struct ifmultiaddr *ifma; 1881188711Sraj uint32_t h; 1882188711Sraj int i; 1883188711Sraj 1884188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1885188711Sraj 1886188711Sraj if (ifp->if_flags & IFF_ALLMULTI) { 1887188711Sraj for (i = 0; i < 8; i++) 1888188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1889188711Sraj 1890188711Sraj return; 1891188711Sraj } 1892188711Sraj 1893195049Srwatson if_maddr_rlock(ifp); 1894188711Sraj TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1895188711Sraj 1896188711Sraj if (ifma->ifma_addr->sa_family != AF_LINK) 1897188711Sraj continue; 1898188711Sraj 1899188711Sraj h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1900188711Sraj ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1901188711Sraj 1902188711Sraj hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1903188711Sraj } 1904195049Srwatson if_maddr_runlock(ifp); 1905188711Sraj 1906188711Sraj for (i = 0; i < 8; i++) 1907188711Sraj TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1908188711Sraj} 1909188711Sraj 1910188711Srajstatic int 1911188711Srajtsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1912188711Sraj{ 1913188711Sraj 1914188711Sraj mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1915188711Sraj 1916188711Sraj TSEC_GLOBAL_LOCK_ASSERT(sc); 1917188711Sraj 1918188711Sraj if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1919188711Sraj TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1920188711Sraj return (mtu); 1921188711Sraj } 1922188711Sraj 1923188711Sraj return (0); 1924188711Sraj} 1925