1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35/* 36 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 37 * register space. These registers can be accessed in the following way: 38 * - PCI config registers are always accessible through PCI config space 39 * - Full 512K space mapped into memory using PCI memory mapped access 40 * - 256-byte I/O space mapped through PCI I/O access 41 * - Full 512K space mapped through indirect I/O using PCI I/O access 42 * It's possible to use either memory mapped mode or I/O mode to access 43 * the registers, but memory mapped is usually the easiest. All registers 44 * are 32 bits wide and must be accessed using 32-bit operations. 45 */ 46 47/* 48 * Adaptec PCI vendor ID. 49 */ 50#define AD_VENDORID 0x9004 51 52/* 53 * AIC-6915 PCI device ID. 54 */ 55#define AD_DEVICEID_STARFIRE 0x6915 56 57/* 58 * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 59 * the exact kind of NIC on which the ASIC is mounted. Currently there 60 * are six different variations. Note: the Adaptec manual lists code 0x28 61 * for two different NICs: the 62044 and the 69011/TX. This is a typo: 62 * the code for the 62044 is really 0x18. 63 * 64 * Note that there also appears to be an 0x19 code for a newer rev 65 * 62044 card. 66 */ 67#define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ 68#define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ 69#define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ 70#define AD_SUBSYSID_62044_REV0 0x0018 /* quad port 10/100baseTX 64-bit */ 71#define AD_SUBSYSID_62044_REV1 0x0019 /* quad port 10/100baseTX 64-bit */ 72#define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ 73#define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ 74 75/* 76 * Starfire internal register space map. The entire register space 77 * is available using PCI memory mapped mode. The SF_RMAP_INTREG 78 * space is available using PCI I/O mode. The entire space can be 79 * accessed using indirect I/O using the indirect I/O addr and 80 * indirect I/O data registers located within the SF_RMAP_INTREG space. 81 */ 82#define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ 83#define SF_RMAP_ROMADDR_MAX 0x3FFFF 84 85#define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ 86#define SF_RMAP_EXGPIO_MAX 0x3FFFF 87 88#define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ 89#define SF_RMAP_INTREG_MAX 0x500FF 90#define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ 91#define SF_RMAP_GENREG_MAX 0x5FFFF 92 93#define SF_RMAP_FIFO_BASE 0x60000 94#define SF_RMAP_FIFO_MAX 0x6FFFF 95 96#define SF_RMAP_STS_BASE 0x70000 97#define SF_RMAP_STS_MAX 0x70083 98 99#define SF_RMAP_RSVD_BASE 0x70084 100#define SF_RMAP_RSVD_MAX 0x7FFFF 101 102/* 103 * PCI config header registers, 0x0000 to 0x003F 104 */ 105#define SF_PCI_VENDOR_ID 0x0000 106#define SF_PCI_DEVICE_ID 0x0002 107#define SF_PCI_COMMAND 0x0004 108#define SF_PCI_STATUS 0x0006 109#define SF_PCI_REVID 0x0008 110#define SF_PCI_CLASSCODE 0x0009 111#define SF_PCI_CACHELEN 0x000C 112#define SF_PCI_LATENCY_TIMER 0x000D 113#define SF_PCI_HEADER_TYPE 0x000E 114#define SF_PCI_LOMEM 0x0010 115#define SF_PCI_LOIO 0x0014 116#define SF_PCI_SUBVEN_ID 0x002C 117#define SF_PCI_SYBSYS_ID 0x002E 118#define SF_PCI_BIOSROM 0x0030 119#define SF_PCI_INTLINE 0x003C 120#define SF_PCI_INTPIN 0x003D 121#define SF_PCI_MINGNT 0x003E 122#define SF_PCI_MINLAT 0x003F 123 124/* 125 * PCI registers, 0x0040 to 0x006F 126 */ 127#define SF_PCI_DEVCFG 0x0040 128#define SF_BACCTL 0x0044 129#define SF_PCI_MON1 0x0048 130#define SF_PCI_MON2 0x004C 131#define SF_PCI_CAPID 0x0050 /* 8 bits */ 132#define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ 133#define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ 134#define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ 135#define SF_PCI_PME_EVENT 0x0058 136#define SF_PCI_EECTL 0x0060 137#define SF_PCI_COMPLIANCE 0x0064 138#define SF_INDIRECTIO_ADDR 0x0068 139#define SF_INDIRECTIO_DATA 0x006C 140 141#define SF_PCIDEVCFG_RESET 0x00000001 142#define SF_PCIDEVCFG_FORCE64 0x00000002 143#define SF_PCIDEVCFG_SYSTEM64 0x00000004 144#define SF_PCIDEVCFG_RSVD0 0x00000008 145#define SF_PCIDEVCFG_INCR_INB 0x00000010 146#define SF_PCIDEVCFG_ABTONPERR 0x00000020 147#define SF_PCIDEVCFG_STPONPERR 0x00000040 148#define SF_PCIDEVCFG_MR_ENB 0x00000080 149#define SF_PCIDEVCFG_FIFOTHR 0x00000F00 150#define SF_PCIDEVCFG_STPONCA 0x00001000 151#define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ 152#define SF_PCIDEVCFG_LATSTP 0x00004000 153#define SF_PCIDEVCFG_BYTE_ENB 0x00008000 154#define SF_PCIDEVCFG_EECSWIDTH 0x00070000 155#define SF_PCIDEVCFG_STPMWCA 0x00080000 156#define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 157#define SF_PCIDEVCFG_INTR_ENB 0x00800000 158#define SF_PCIDEVCFG_DPR_ENB 0x01000000 159#define SF_PCIDEVCFG_RSVD1 0x02000000 160#define SF_PCIDEVCFG_RSVD2 0x04000000 161#define SF_PCIDEVCFG_STA_ENB 0x08000000 162#define SF_PCIDEVCFG_RTA_ENB 0x10000000 163#define SF_PCIDEVCFG_RMA_ENB 0x20000000 164#define SF_PCIDEVCFG_SSE_ENB 0x40000000 165#define SF_PCIDEVCFG_DPE_ENB 0x80000000 166 167#define SF_BACCTL_BACDMA_ENB 0x00000001 168#define SF_BACCTL_PREFER_RXDMA 0x00000002 169#define SF_BACCTL_PREFER_TXDMA 0x00000004 170#define SF_BACCTL_SINGLE_DMA 0x00000008 171#define SF_BACCTL_SWAPMODE_DATA 0x00000030 172#define SF_BACCTL_SWAPMODE_DESC 0x000000C0 173 174#define SF_SWAPMODE_LE 0x00000000 175#define SF_SWAPMODE_BE 0x00000010 176 177#define SF_PSTATE_MASK 0x0003 178#define SF_PSTATE_D0 0x0000 179#define SF_PSTATE_D1 0x0001 180#define SF_PSTATE_D2 0x0002 181#define SF_PSTATE_D3 0x0003 182#define SF_PME_EN 0x0010 183#define SF_PME_STATUS 0x8000 184 185 186/* 187 * Ethernet registers 0x0070 to 0x00FF 188 */ 189#define SF_GEN_ETH_CTL 0x0070 190#define SF_TIMER_CTL 0x0074 191#define SF_CURTIME 0x0078 192#define SF_ISR 0x0080 193#define SF_ISR_SHADOW 0x0084 194#define SF_IMR 0x0088 195#define SF_GPIO 0x008C 196#define SF_TXDQ_CTL 0x0090 197#define SF_TXDQ_ADDR_HIPRIO 0x0094 198#define SF_TXDQ_ADDR_LOPRIO 0x0098 199#define SF_TXDQ_ADDR_HI 0x009C 200#define SF_TXDQ_PRODIDX 0x00A0 201#define SF_TXDQ_CONSIDX 0x00A4 202#define SF_TXDMA_STS1 0x00A8 203#define SF_TXDMA_STS2 0x00AC 204#define SF_TX_FRAMCTL 0x00B0 205#define SF_CQ_ADDR_HI 0x00B4 206#define SF_TXCQ_CTL 0x00B8 207#define SF_RXCQ_CTL_1 0x00BC 208#define SF_RXCQ_CTL_2 0x00C0 209#define SF_CQ_CONSIDX 0x00C4 210#define SF_CQ_PRODIDX 0x00C8 211#define SF_CQ_RXQ2 0x00CC 212#define SF_RXDMA_CTL 0x00D0 213#define SF_RXDQ_CTL_1 0x00D4 214#define SF_RXDQ_CTL_2 0x00D8 215#define SF_RXDQ_ADDR_HI 0x00DC 216#define SF_RXDQ_ADDR_Q1 0x00E0 217#define SF_RXDQ_ADDR_Q2 0x00E4 218#define SF_RXDQ_PTR_Q1 0x00E8 219#define SF_RXDQ_PTR_Q2 0x00EC 220#define SF_RXDMA_STS 0x00F0 221#define SF_RXFILT 0x00F4 222#define SF_RX_FRAMETEST_OUT 0x00F8 223 224/* Ethernet control register */ 225#define SF_ETHCTL_RX_ENB 0x00000001 226#define SF_ETHCTL_TX_ENB 0x00000002 227#define SF_ETHCTL_RXDMA_ENB 0x00000004 228#define SF_ETHCTL_TXDMA_ENB 0x00000008 229#define SF_ETHCTL_RXGFP_ENB 0x00000010 230#define SF_ETHCTL_TXGFP_ENB 0x00000020 231#define SF_ETHCTL_SOFTINTR 0x00000800 232 233/* Timer control register */ 234#define SF_TIMER_IMASK_INTERVAL 0x0000001F 235#define SF_TIMER_IMASK_MODE 0x00000060 236#define SF_TIMER_SMALLFRAME_BYP 0x00000100 237#define SF_TIMER_SMALLRX_FRAME 0x00000600 238#define SF_TIMER_TIMES_TEN 0x00000800 239#define SF_TIMER_RXHIPRIO_BYP 0x00001000 240#define SF_TIMER_TX_DMADONE_DLY 0x00002000 241#define SF_TIMER_TX_QDONE_DLY 0x00004000 242#define SF_TIMER_TX_FRDONE_DLY 0x00008000 243#define SF_TIMER_GENTIMER 0x00FF0000 244#define SF_TIMER_ONESHOT 0x01000000 245#define SF_TIMER_GENTIMER_RES 0x02000000 246#define SF_TIMER_TIMEST_RES 0x04000000 247#define SF_TIMER_RXQ2DONE_DLY 0x10000000 248#define SF_TIMER_EARLYRX2_DLY 0x20000000 249#define SF_TIMER_RXQ1DONE_DLY 0x40000000 250#define SF_TIMER_EARLYRX1_DLY 0x80000000 251 252/* Timer resolution is 0.8us * 128. */ 253#define SF_IM_MIN 0 254#define SF_IM_MAX 0x1F /* 3.276ms */ 255#define SF_IM_DEFAULT 1 /* 102.4us */ 256 257/* Interrupt status register */ 258#define SF_ISR_PCIINT_ASSERTED 0x00000001 259#define SF_ISR_GFP_TX 0x00000002 260#define SF_ISR_GFP_RX 0x00000004 261#define SF_ISR_TX_BADID_HIPRIO 0x00000008 262#define SF_ISR_TX_BADID_LOPRIO 0x00000010 263#define SF_ISR_NO_TX_CSUM 0x00000020 264#define SF_ISR_RXDQ2_NOBUFS 0x00000040 265#define SF_ISR_RXGFP_NORESP 0x00000080 266#define SF_ISR_RXDQ1_DMADONE 0x00000100 267#define SF_ISR_RXDQ2_DMADONE 0x00000200 268#define SF_ISR_RXDQ1_EARLY 0x00000400 269#define SF_ISR_RXDQ2_EARLY 0x00000800 270#define SF_ISR_TX_QUEUEDONE 0x00001000 271#define SF_ISR_TX_DMADONE 0x00002000 272#define SF_ISR_TX_TXDONE 0x00004000 273#define SF_ISR_NORMALINTR 0x00008000 274#define SF_ISR_RXDQ1_NOBUFS 0x00010000 275#define SF_ISR_RXCQ2_NOBUFS 0x00020000 276#define SF_ISR_TX_LOFIFO 0x00040000 277#define SF_ISR_DMAERR 0x00080000 278#define SF_ISR_PCIINT 0x00100000 279#define SF_ISR_TXCQ_NOBUFS 0x00200000 280#define SF_ISR_RXCQ1_NOBUFS 0x00400000 281#define SF_ISR_SOFTINTR 0x00800000 282#define SF_ISR_GENTIMER 0x01000000 283#define SF_ISR_ABNORMALINTR 0x02000000 284#define SF_ISR_RSVD0 0x04000000 285#define SF_ISR_STATSOFLOW 0x08000000 286#define SF_ISR_GPIO 0xF0000000 287 288/* 289 * Shadow interrupt status register. Unlike the normal IRQ register, 290 * reading bits here does not automatically cause them to reset. 291 */ 292#define SF_SISR_PCIINT_ASSERTED 0x00000001 293#define SF_SISR_GFP_TX 0x00000002 294#define SF_SISR_GFP_RX 0x00000004 295#define SF_SISR_TX_BADID_HIPRIO 0x00000008 296#define SF_SISR_TX_BADID_LOPRIO 0x00000010 297#define SF_SISR_NO_TX_CSUM 0x00000020 298#define SF_SISR_RXDQ2_NOBUFS 0x00000040 299#define SF_SISR_RXGFP_NORESP 0x00000080 300#define SF_SISR_RXDQ1_DMADONE 0x00000100 301#define SF_SISR_RXDQ2_DMADONE 0x00000200 302#define SF_SISR_RXDQ1_EARLY 0x00000400 303#define SF_SISR_RXDQ2_EARLY 0x00000800 304#define SF_SISR_TX_QUEUEDONE 0x00001000 305#define SF_SISR_TX_DMADONE 0x00002000 306#define SF_SISR_TX_TXDONE 0x00004000 307#define SF_SISR_NORMALINTR 0x00008000 308#define SF_SISR_RXDQ1_NOBUFS 0x00010000 309#define SF_SISR_RXCQ2_NOBUFS 0x00020000 310#define SF_SISR_TX_LOFIFO 0x00040000 311#define SF_SISR_DMAERR 0x00080000 312#define SF_SISR_PCIINT 0x00100000 313#define SF_SISR_TXCQ_NOBUFS 0x00200000 314#define SF_SISR_RXCQ1_NOBUFS 0x00400000 315#define SF_SISR_SOFTINTR 0x00800000 316#define SF_SISR_GENTIMER 0x01000000 317#define SF_SISR_ABNORMALINTR 0x02000000 318#define SF_SISR_RSVD0 0x04000000 319#define SF_SISR_STATSOFLOW 0x08000000 320#define SF_SISR_GPIO 0xF0000000 321 322/* Interrupt mask register */ 323#define SF_IMR_PCIINT_ASSERTED 0x00000001 324#define SF_IMR_GFP_TX 0x00000002 325#define SF_IMR_GFP_RX 0x00000004 326#define SF_IMR_TX_BADID_HIPRIO 0x00000008 327#define SF_IMR_TX_BADID_LOPRIO 0x00000010 328#define SF_IMR_NO_TX_CSUM 0x00000020 329#define SF_IMR_RXDQ2_NOBUFS 0x00000040 330#define SF_IMR_RXGFP_NORESP 0x00000080 331#define SF_IMR_RXDQ1_DMADONE 0x00000100 332#define SF_IMR_RXDQ2_DMADONE 0x00000200 333#define SF_IMR_RXDQ1_EARLY 0x00000400 334#define SF_IMR_RXDQ2_EARLY 0x00000800 335#define SF_IMR_TX_QUEUEDONE 0x00001000 336#define SF_IMR_TX_DMADONE 0x00002000 337#define SF_IMR_TX_TXDONE 0x00004000 338#define SF_IMR_NORMALINTR 0x00008000 339#define SF_IMR_RXDQ1_NOBUFS 0x00010000 340#define SF_IMR_RXCQ2_NOBUFS 0x00020000 341#define SF_IMR_TX_LOFIFO 0x00040000 342#define SF_IMR_DMAERR 0x00080000 343#define SF_IMR_PCIINT 0x00100000 344#define SF_IMR_TXCQ_NOBUFS 0x00200000 345#define SF_IMR_RXCQ1_NOBUFS 0x00400000 346#define SF_IMR_SOFTINTR 0x00800000 347#define SF_IMR_GENTIMER 0x01000000 348#define SF_IMR_ABNORMALINTR 0x02000000 349#define SF_IMR_RSVD0 0x04000000 350#define SF_IMR_STATSOFLOW 0x08000000 351#define SF_IMR_GPIO 0xF0000000 352 353#define SF_INTRS \ 354 (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \ 355 SF_IMR_TX_DMADONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \ 356 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ 357 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \ 358 SF_IMR_TX_LOFIFO|SF_IMR_DMAERR|SF_IMR_RXGFP_NORESP| \ 359 SF_IMR_NO_TX_CSUM) 360 361/* TX descriptor queue control registers */ 362#define SF_TXDQCTL_DESCTYPE 0x00000007 363#define SF_TXDQCTL_NODMACMP 0x00000008 364#define SF_TXDQCTL_MINSPACE 0x00000070 365#define SF_TXDQCTL_64BITADDR 0x00000080 366#define SF_TXDQCTL_BURSTLEN 0x00003F00 367#define SF_TXDQCTL_SKIPLEN 0x001F0000 368#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 369 370#define SF_TXDMA_HIPRIO_THRESH 2 371#define SF_TXDDMA_BURST (128 / 32) 372 373#define SF_TXBUFDESC_TYPE0 0x00000000 374#define SF_TXBUFDESC_TYPE1 0x00000001 375#define SF_TXBUFDESC_TYPE2 0x00000002 376#define SF_TXBUFDESC_TYPE3 0x00000003 377#define SF_TXBUFDESC_TYPE4 0x00000004 378 379#define SF_TXMINSPACE_UNLIMIT 0x00000000 380#define SF_TXMINSPACE_32BYTES 0x00000010 381#define SF_TXMINSPACE_64BYTES 0x00000020 382#define SF_TXMINSPACE_128BYTES 0x00000030 383#define SF_TXMINSPACE_256BYTES 0x00000040 384 385#define SF_TXSKIPLEN_0BYTES 0x00000000 386#define SF_TXSKIPLEN_8BYTES 0x00010000 387#define SF_TXSKIPLEN_16BYTES 0x00020000 388#define SF_TXSKIPLEN_24BYTES 0x00030000 389#define SF_TXSKIPLEN_32BYTES 0x00040000 390 391/* TX frame control register */ 392#define SF_TXFRMCTL_TXTHRESH 0x000000FF 393#define SF_TXFRMCTL_CPLAFTERTX 0x00000100 394#define SF_TXFRMCRL_DEBUG 0x0000FE00 395#define SF_TXFRMCTL_STATUS 0x01FF0000 396#define SF_TXFRMCTL_MAC_TXIF 0xFE000000 397 398/* TX completion queue control register */ 399#define SF_TXCQ_THRESH 0x0000000F 400#define SF_TXCQ_COMMON 0x00000010 401#define SF_TXCQ_SIZE 0x00000020 402#define SF_TXCQ_WRITEENB 0x00000040 403#define SF_TXCQ_USE_64BIT 0x00000080 404#define SF_TXCQ_ADDR 0xFFFFFF00 405 406/* RX completion queue control register */ 407#define SF_RXCQ_THRESH 0x0000000F 408#define SF_RXCQ_TYPE 0x00000030 409#define SF_RXCQ_WRITEENB 0x00000040 410#define SF_RXCQ_USE_64BIT 0x00000080 411#define SF_RXCQ_ADDR 0xFFFFFF00 412 413#define SF_RXCQTYPE_0 0x00000000 414#define SF_RXCQTYPE_1 0x00000010 415#define SF_RXCQTYPE_2 0x00000020 416#define SF_RXCQTYPE_3 0x00000030 417 418/* TX descriptor queue producer index register */ 419#define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 420#define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 421 422/* TX descriptor queue consumer index register */ 423#define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 424#define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 425 426/* Completion queue consumer index register */ 427#define SF_CQ_CONSIDX_RXQ1 0x000003FF 428#define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 429#define SF_CQ_CONSIDX_TXQ 0x03FF0000 430#define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 431 432/* Completion queue producer index register */ 433#define SF_CQ_PRODIDX_RXQ1 0x000003FF 434#define SF_CQ_PRODIDX_TXQ 0x03FF0000 435 436/* RX completion queue 2 consumer/producer index register */ 437#define SF_CQ_RXQ2_CONSIDX 0x000003FF 438#define SF_CQ_RXQ2_RXTHRMODE 0x00008000 439#define SF_CQ_RXQ2_PRODIDX 0x03FF0000 440 441#define SF_CQ_RXTHRMODE_INT_ON 0x00008000 442#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 443#define SF_CQ_TXTHRMODE_INT_ON 0x80000000 444#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 445 446/* RX DMA control register */ 447#define SF_RXDMA_BURSTSIZE 0x0000007F 448#define SF_RXDMA_FPTESTMODE 0x00000080 449#define SF_RXDMA_HIPRIOTHRESH 0x00000F00 450#define SF_RXDMA_RXEARLYTHRESH 0x0001F000 451#define SF_RXDMA_DMACRC 0x00040000 452#define SF_RXDMA_USEBKUPQUEUE 0x00080000 453#define SF_RXDMA_QUEUEMODE 0x00700000 454#define SF_RXDMA_RXCQ2_ON 0x00800000 455#define SF_RXDMA_CSUMMODE 0x03000000 456#define SF_RXDMA_DMAPAUSEPKTS 0x04000000 457#define SF_RXDMA_DMACTLPKTS 0x08000000 458#define SF_RXDMA_DMACRXERRPKTS 0x10000000 459#define SF_RXDMA_DMABADPKTS 0x20000000 460#define SF_RXDMA_DMARUNTS 0x40000000 461#define SF_RXDMA_REPORTBADPKTS 0x80000000 462#define SF_RXDMA_HIGHPRIO_THRESH 6 463#define SF_RXDMA_BURST (64 / 32) 464 465#define SF_RXDQMODE_Q1ONLY 0x00100000 466#define SF_RXDQMODE_Q2_ON_FP 0x00200000 467#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 468#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 469#define SF_RXDQMODE_SPLITHDR 0x00500000 470 471#define SF_RXCSUMMODE_IGNORE 0x00000000 472#define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 473#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 474#define SF_RXCSUMMODE_RSVD 0x03000000 475 476/* RX descriptor queue control registers */ 477#define SF_RXDQCTL_MINDESCTHR 0x0000007F 478#define SF_RXDQCTL_Q1_WE 0x00000080 479#define SF_RXDQCTL_DESCSPACE 0x00000700 480#define SF_RXDQCTL_64BITDADDR 0x00000800 481#define SF_RXDQCTL_64BITBADDR 0x00001000 482#define SF_RXDQCTL_VARIABLE 0x00002000 483#define SF_RXDQCTL_ENTRIES 0x00004000 484#define SF_RXDQCTL_PREFETCH 0x00008000 485#define SF_RXDQCTL_BUFLEN 0xFFFF0000 486 487#define SF_DESCSPACE_4BYTES 0x00000000 488#define SF_DESCSPACE_8BYTES 0x00000100 489#define SF_DESCSPACE_16BYTES 0x00000200 490#define SF_DESCSPACE_32BYTES 0x00000300 491#define SF_DESCSPACE_64BYTES 0x00000400 492#define SF_DESCSPACE_128_BYTES 0x00000500 493 494/* RX buffer consumer/producer index registers */ 495#define SF_RXDQ_PRODIDX 0x000007FF 496#define SF_RXDQ_CONSIDX 0x07FF0000 497 498/* RX filter control register */ 499#define SF_RXFILT_PROMISC 0x00000001 500#define SF_RXFILT_ALLMULTI 0x00000002 501#define SF_RXFILT_BROAD 0x00000004 502#define SF_RXFILT_HASHPRIO 0x00000008 503#define SF_RXFILT_HASHMODE 0x00000030 504#define SF_RXFILT_PERFMODE 0x000000C0 505#define SF_RXFILT_VLANMODE 0x00000300 506#define SF_RXFILT_WAKEMODE 0x00000C00 507#define SF_RXFILT_MULTI_NOBROAD 0x00001000 508#define SF_RXFILT_MIN_VLANPRIO 0x0000E000 509#define SF_RXFILT_PEFECTPRIO 0xFFFF0000 510 511/* Hash filtering mode */ 512#define SF_HASHMODE_OFF 0x00000000 513#define SF_HASHMODE_WITHVLAN 0x00000010 514#define SF_HASHMODE_ANYVLAN 0x00000020 515#define SF_HASHMODE_ANY 0x00000030 516 517/* Perfect filtering mode */ 518#define SF_PERFMODE_OFF 0x00000000 519#define SF_PERFMODE_NORMAL 0x00000040 520#define SF_PERFMODE_INVERSE 0x00000080 521#define SF_PERFMODE_VLAN 0x000000C0 522 523/* VLAN mode */ 524#define SF_VLANMODE_OFF 0x00000000 525#define SF_VLANMODE_NOSTRIP 0x00000100 526#define SF_VLANMODE_STRIP 0x00000200 527#define SF_VLANMODE_RSVD 0x00000300 528 529/* Wakeup mode */ 530#define SF_WAKEMODE_OFF 0x00000000 531#define SF_WAKEMODE_FILTER 0x00000400 532#define SF_WAKEMODE_FP 0x00000800 533#define SF_WAKEMODE_HIPRIO 0x00000C00 534 535/* 536 * Extra PCI registers 0x0100 to 0x0FFF 537 */ 538#define SF_PCI_TARGSTAT 0x0100 539#define SF_PCI_MASTSTAT1 0x0104 540#define SF_PCI_MASTSTAT2 0x0108 541#define SF_PCI_DMAHOSTADDR_LO 0x010C 542#define SF_BAC_DMADIAG0 0x0110 543#define SF_BAC_DMADIAG1 0x0114 544#define SF_BAC_DMADIAG2 0x0118 545#define SF_BAC_DMADIAG3 0x011C 546#define SF_PAR0 0x0120 547#define SF_PAR1 0x0124 548#define SF_PCICB_FUNCEVENT 0x0130 549#define SF_PCICB_FUNCEVENT_MASK 0x0134 550#define SF_PCICB_FUNCSTATE 0x0138 551#define SF_PCICB_FUNCFORCE 0x013C 552 553/* 554 * Serial EEPROM registers 0x1000 to 0x1FFF 555 * Presumeably the EEPROM is mapped into this 8K window. 556 */ 557#define SF_EEADDR_BASE 0x1000 558#define SF_EEADDR_MAX 0x1FFF 559 560#define SF_EE_NODEADDR 14 561 562/* 563 * MII registers registers 0x2000 to 0x3FFF 564 * There are 32 sets of 32 registers, one set for each possible 565 * PHY address. Each 32 bit register is split into a 16-bit data 566 * port and a couple of status bits. 567 */ 568 569#define SF_MIIADDR_BASE 0x2000 570#define SF_MIIADDR_MAX 0x3FFF 571#define SF_MII_BLOCKS 32 572 573#define SF_MII_DATAVALID 0x80000000 574#define SF_MII_BUSY 0x40000000 575#define SF_MII_DATAPORT 0x0000FFFF 576 577#define SF_PHY_REG(phy, reg) \ 578 (SF_MIIADDR_BASE + ((phy) * SF_MII_BLOCKS * sizeof(uint32_t)) + \ 579 ((reg) * sizeof(uint32_t))) 580 581/* 582 * Ethernet extra registers 0x4000 to 0x4FFF 583 */ 584#define SF_TESTMODE 0x4000 585#define SF_RX_FRAMEPROC_CTL 0x4004 586#define SF_TX_FRAMEPROC_CTL 0x4008 587 588/* 589 * MAC registers 0x5000 to 0x5FFF 590 */ 591#define SF_MACCFG_1 0x5000 592#define SF_MACCFG_2 0x5004 593#define SF_BKTOBKIPG 0x5008 594#define SF_NONBKTOBKIPG 0x500C 595#define SF_COLRETRY 0x5010 596#define SF_MAXLEN 0x5014 597#define SF_TXNIBBLECNT 0x5018 598#define SF_TXBYTECNT 0x501C 599#define SF_RETXCNT 0x5020 600#define SF_RANDNUM 0x5024 601#define SF_RANDNUM_MASK 0x5028 602#define SF_TOTALTXCNT 0x5034 603#define SF_RXBYTECNT 0x5040 604#define SF_TXPAUSETIMER 0x5060 605#define SF_VLANTYPE 0x5064 606#define SF_MIISTATUS 0x5070 607 608#define SF_MACCFG1_HUGEFRAMES 0x00000001 609#define SF_MACCFG1_FULLDUPLEX 0x00000002 610#define SF_MACCFG1_AUTOPAD 0x00000004 611#define SF_MACCFG1_HDJAM 0x00000008 612#define SF_MACCFG1_DELAYCRC 0x00000010 613#define SF_MACCFG1_NOBACKOFF 0x00000020 614#define SF_MACCFG1_LENGTHCHECK 0x00000040 615#define SF_MACCFG1_PUREPREAMBLE 0x00000080 616#define SF_MACCFG1_PASSALLRX 0x00000100 617#define SF_MACCFG1_PREAM_DETCNT 0x00000200 618#define SF_MACCFG1_RX_FLOWENB 0x00000400 619#define SF_MACCFG1_TX_FLOWENB 0x00000800 620#define SF_MACCFG1_TESTMODE 0x00003000 621#define SF_MACCFG1_MIILOOPBK 0x00004000 622#define SF_MACCFG1_SOFTRESET 0x00008000 623 624#define SF_MACCFG2_AUTOVLANPAD 0x00000020 625 626/* 627 * There are the recommended IPG nibble counter settings 628 * specified in the Adaptec manual for full duplex and 629 * half duplex operation. 630 */ 631#define SF_IPGT_FDX 0x15 632#define SF_IPGT_HDX 0x11 633 634/* 635 * RX filter registers 0x6000 to 0x6FFF 636 */ 637#define SF_RXFILT_PERFECT_BASE 0x6000 638#define SF_RXFILT_PERFECT_MAX 0x60FF 639#define SF_RXFILT_PERFECT_SKIP 0x0010 640#define SF_RXFILT_PERFECT_CNT 0x0010 641 642#define SF_RXFILT_HASH_BASE 0x6100 643#define SF_RXFILT_HASH_MAX 0x62FF 644#define SF_RXFILT_HASH_SKIP 0x0010 645#define SF_RXFILT_HASH_CNT 0x001F 646#define SF_RXFILT_HASH_ADDROFF 0x0000 647#define SF_RXFILT_HASH_PRIOOFF 0x0004 648#define SF_RXFILT_HASH_VLANOFF 0x0008 649 650/* 651 * Statistics registers 0x7000 to 0x7FFF 652 */ 653#define SF_STATS_BASE 0x7000 654#define SF_STATS_END 0x7FFF 655 656#define SF_STATS_TX_FRAMES 0x0000 657#define SF_STATS_TX_SINGLE_COL 0x0004 658#define SF_STATS_TX_MULTI_COL 0x0008 659#define SF_STATS_TX_CRC_ERRS 0x000C 660#define SF_STATS_TX_BYTES 0x0010 661#define SF_STATS_TX_DEFERRED 0x0014 662#define SF_STATS_TX_LATE_COL 0x0018 663#define SF_STATS_TX_PAUSE 0x001C 664#define SF_STATS_TX_CTL_FRAME 0x0020 665#define SF_STATS_TX_EXCESS_COL 0x0024 666#define SF_STATS_TX_EXCESS_DEF 0x0028 667#define SF_STATS_TX_MULTI 0x002C 668#define SF_STATS_TX_BCAST 0x0030 669#define SF_STATS_TX_FRAME_LOST 0x0034 670#define SF_STATS_RX_FRAMES 0x0038 671#define SF_STATS_RX_CRC_ERRS 0x003C 672#define SF_STATS_RX_ALIGN_ERRS 0x0040 673#define SF_STATS_RX_BYTES 0x0044 674#define SF_STATS_RX_PAUSE 0x0048 675#define SF_STATS_RX_CTL_FRAME 0x004C 676#define SF_STATS_RX_UNSUP_FRAME 0x0050 677#define SF_STATS_RX_GIANTS 0x0054 678#define SF_STATS_RX_RUNTS 0x0058 679#define SF_STATS_RX_JABBER 0x005C 680#define SF_STATS_RX_FRAGMENTS 0x0060 681#define SF_STATS_RX_64 0x0064 682#define SF_STATS_RX_65_127 0x0068 683#define SF_STATS_RX_128_255 0x006C 684#define SF_STATS_RX_256_511 0x0070 685#define SF_STATS_RX_512_1023 0x0074 686#define SF_STATS_RX_1024_1518 0x0078 687#define SF_STATS_RX_FRAME_LOST 0x007C 688#define SF_STATS_TX_UNDERRUN 0x0080 689 690/* 691 * TX frame processor instruction space 0x8000 to 0x9FFF 692 */ 693#define SF_TXGFP_MEM_BASE 0x8000 694#define SF_TXGFP_MEM_END 0x8FFF 695 696/* Number of bytes of an GFP instruction. */ 697#define SF_GFP_INST_BYTES 6 698/* 699 * RX frame processor instruction space 0xA000 to 0xBFFF 700 */ 701#define SF_RXGFP_MEM_BASE 0xA000 702#define SF_RXGFP_MEM_END 0xBFFF 703 704/* 705 * Ethernet FIFO access space 0xC000 to 0xDFFF 706 */ 707 708/* 709 * Reserved 0xE000 to 0xFFFF 710 */ 711 712/* 713 * Descriptor data structures. 714 */ 715 716/* 717 * RX buffer descriptor type 0, 32-bit addressing. 718 */ 719struct sf_rx_bufdesc_type0 { 720 uint32_t sf_addrlo; 721#define SF_RX_DESC_VALID 0x00000001 722#define SF_RX_DESC_END 0x00000002 723}; 724 725/* 726 * RX buffer descriptor type 1, 64-bit addressing. 727 */ 728struct sf_rx_bufdesc_type1 { 729 uint64_t sf_addr; 730}; 731 732/* 733 * RX completion descriptor, type 0 (short). 734 */ 735struct sf_rx_cmpdesc_type0 { 736 uint32_t sf_rx_status1; 737#define SF_RX_CMPDESC_LEN 0x0000ffff 738#define SF_RX_CMPDESC_EIDX 0x07ff0000 739#define SF_RX_CMPDESC_STAT1 0x38000000 740#define SF_RX_CMPDESC_ID 0x40000000 741}; 742 743/* 744 * RX completion descriptor, type 1 (basic). Includes vlan ID 745 * if this is a vlan-addressed packet, plus extended status. 746 */ 747struct sf_rx_cmpdesc_type1 { 748 uint32_t sf_rx_status1; 749 uint32_t sf_rx_status2; 750#define SF_RX_CMPDESC_VLAN 0x0000ffff 751#define SF_RX_CMPDESC_STAT2 0xffff0000 752}; 753 754/* 755 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 756 * checksum instead of vlan tag, plus extended status. 757 */ 758struct sf_rx_cmpdesc_type2 { 759 uint32_t sf_rx_status1; 760 uint32_t sf_rx_status2; 761#define SF_RX_CMPDESC_CSUM2 0x0000ffff 762}; 763 764/* 765 * RX completion descriptor type 3 (full). Includes timestamp, partial 766 * TCP/IP checksum, vlan tag plus priority, two extended status fields. 767 */ 768struct sf_rx_cmpdesc_type3 { 769 uint32_t sf_rx_status1; 770 uint32_t sf_rx_status2; 771 uint32_t sf_rx_status3; 772#define SF_RX_CMPDESC_CSUM3 0xffff0000 773#define SF_RX_CMPDESC_VLANPRI 0x0000ffff 774 uint32_t sf_rx_timestamp; 775}; 776 777#define SF_RXSTAT1_QUEUE 0x08000000 778#define SF_RXSTAT1_FIFOFULL 0x10000000 779#define SF_RXSTAT1_OK 0x20000000 780 781#define SF_RXSTAT2_FRAMETYPE_MASK 0x00070000 782#define SF_RXSTAT2_FRAMETYPE_UNKN 0x00000000 783#define SF_RXSTAT2_FRAMETYPE_IPV4 0x00010000 784#define SF_RXSTAT2_FRAMETYPE_IPV6 0x00020000 785#define SF_RXSTAT2_FRAMETYPE_IPX 0x00030000 786#define SF_RXSTAT2_FRAMETYPE_ICMP 0x00040000 787#define SF_RXSTAT2_FRAMETYPE_UNSPRT 0x00050000 788#define SF_RXSTAT2_UDP 0x00080000 789#define SF_RXSTAT2_TCP 0x00100000 790#define SF_RXSTAT2_FRAG 0x00200000 791#define SF_RXSTAT2_PCSUM_OK 0x00400000 /* partial checksum ok */ 792#define SF_RXSTAT2_CSUM_BAD 0x00800000 /* TCP/IP checksum bad */ 793#define SF_RXSTAT2_CSUM_OK 0x01000000 /* TCP/IP checksum ok */ 794#define SF_RXSTAT2_VLAN 0x02000000 795#define SF_RXSTAT2_BADRXCODE 0x04000000 796#define SF_RXSTAT2_DRIBBLE 0x08000000 797#define SF_RXSTAT2_ISL_CRCERR 0x10000000 798#define SF_RXSTAT2_CRCERR 0x20000000 799#define SF_RXSTAT2_HASH 0x40000000 800#define SF_RXSTAT2_PERFECT 0x80000000 801#define SF_RXSTAT2_MASK 0xFFFF0000 802 803#define SF_RXSTAT3_ISL 0x00008000 804#define SF_RXSTAT3_PAUSE 0x00004000 805#define SF_RXSTAT3_CONTROL 0x00002000 806#define SF_RXSTAT3_HEADER 0x00001000 807#define SF_RXSTAT3_TRAILER 0x00000800 808#define SF_RXSTAT3_START_IDX_MASK 0x000007FF 809 810struct sf_frag { 811 uint32_t sf_addr; 812 uint16_t sf_fraglen; 813 uint16_t sf_pktlen; 814}; 815 816struct sf_frag_msdos { 817 uint16_t sf_pktlen; 818 uint16_t sf_fraglen; 819 uint32_t sf_addr; 820}; 821 822/* 823 * TX frame descriptor type 0, 32-bit addressing. One descriptor can 824 * be used to map multiple packet fragments. Note that the number of 825 * fragments can be variable depending on how the descriptor spacing 826 * is specified in the TX descriptor queue control register. 827 * We always use a spacing of 128 bytes, and a skipfield length of 8 828 * bytes: this means 16 bytes for the descriptor, including the skipfield, 829 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 830 * which allows for 14 fragments per descriptor. The total size of the 831 * transmit buffer queue is limited to 16384 bytes, so with a spacing of 832 * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 833 */ 834struct sf_tx_bufdesc_type0 { 835 uint32_t sf_tx_ctrl; 836#define SF_TX_DESC_CRCEN 0x01000000 837#define SF_TX_DESC_CALTCP 0x02000000 838#define SF_TX_DESC_END 0x04000000 839#define SF_TX_DESC_INTR 0x08000000 840#define SF_TX_DESC_ID 0xb0000000 841 uint32_t sf_tx_frag; 842 /* 843 * Depending on descriptor spacing/skip field length it 844 * can have fixed number of struct sf_frag. 845 * struct sf_frag sf_frags[14]; 846 */ 847}; 848 849/* 850 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 851 * maps a single fragment. 852 */ 853struct sf_tx_bufdesc_type1 { 854 uint32_t sf_tx_ctrl; 855#define SF_TX_DESC_FRAGLEN 0x0000ffff 856#define SF_TX_DESC_FRAGCNT 0x00ff0000 857 uint32_t sf_addrlo; 858}; 859 860/* 861 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 862 * maps a single fragment. 863 */ 864struct sf_tx_bufdesc_type2 { 865 uint32_t sf_tx_ctrl; 866 uint32_t sf_tx_reserved; 867 uint64_t sf_addr; 868}; 869 870/* TX buffer descriptor type 3 is not defined. */ 871 872/* 873 * TX frame descriptor type 4, 32-bit addressing. This is a special 874 * case of the type 0 descriptor, identical except that the fragment 875 * address and length fields are ordered differently. This is done 876 * to optimize copies in MS-DOS and OS/2 drivers. 877 */ 878struct sf_tx_bufdesc_type4 { 879 uint32_t sf_tx_ctrl; 880 uint32_t sf_tx_frag; 881 /* 882 * Depending on descriptor spacing/skip field length it 883 * can have fixed number of struct sf_frag_msdos. 884 * 885 * struct sf_frag_msdos sf_frags[14]; 886 */ 887}; 888 889/* 890 * Transmit completion queue descriptor formats. 891 */ 892 893/* 894 * Transmit DMA completion descriptor, type 0. 895 */ 896#define SF_TXCMPTYPE_DMA 0x80000000 897#define SF_TXCMPTYPE_TX 0xa0000000 898struct sf_tx_cmpdesc_type0 { 899 uint32_t sf_tx_status1; 900#define SF_TX_CMPDESC_IDX 0x00007fff 901#define SF_TX_CMPDESC_HIPRI 0x00008000 902#define SF_TX_CMPDESC_STAT 0x1fff0000 903#define SF_TX_CMPDESC_TYPE 0xe0000000 904}; 905 906/* 907 * Transmit completion descriptor, type 1. 908 */ 909struct sf_tx_cmpdesc_type1 { 910 uint32_t sf_tx_status1; 911 uint32_t sf_tx_status2; 912}; 913 914#define SF_TXSTAT_CRCERR 0x00010000 915#define SF_TXSTAT_LENCHECKERR 0x00020000 916#define SF_TXSTAT_LENRANGEERR 0x00040000 917#define SF_TXSTAT_TX_OK 0x00080000 918#define SF_TXSTAT_TX_DEFERED 0x00100000 919#define SF_TXSTAT_EXCESS_DEFER 0x00200000 920#define SF_TXSTAT_EXCESS_COLL 0x00400000 921#define SF_TXSTAT_LATE_COLL 0x00800000 922#define SF_TXSTAT_TOOBIG 0x01000000 923#define SF_TXSTAT_TX_UNDERRUN 0x02000000 924#define SF_TXSTAT_CTLFRAME_OK 0x04000000 925#define SF_TXSTAT_PAUSEFRAME_OK 0x08000000 926#define SF_TXSTAT_PAUSED 0x10000000 927 928/* Statistics counters. */ 929struct sf_stats { 930 uint64_t sf_tx_frames; 931 uint32_t sf_tx_single_colls; 932 uint32_t sf_tx_multi_colls; 933 uint32_t sf_tx_crcerrs; 934 uint64_t sf_tx_bytes; 935 uint32_t sf_tx_deferred; 936 uint32_t sf_tx_late_colls; 937 uint32_t sf_tx_pause_frames; 938 uint32_t sf_tx_control_frames; 939 uint32_t sf_tx_excess_colls; 940 uint32_t sf_tx_excess_defer; 941 uint32_t sf_tx_mcast_frames; 942 uint32_t sf_tx_bcast_frames; 943 uint32_t sf_tx_frames_lost; 944 uint64_t sf_rx_frames; 945 uint32_t sf_rx_crcerrs; 946 uint32_t sf_rx_alignerrs; 947 uint64_t sf_rx_bytes; 948 uint32_t sf_rx_pause_frames; 949 uint32_t sf_rx_control_frames; 950 uint32_t sf_rx_unsup_control_frames; 951 uint32_t sf_rx_giants; 952 uint32_t sf_rx_runts; 953 uint32_t sf_rx_jabbererrs; 954 uint32_t sf_rx_fragments; 955 uint64_t sf_rx_pkts_64; 956 uint64_t sf_rx_pkts_65_127; 957 uint64_t sf_rx_pkts_128_255; 958 uint64_t sf_rx_pkts_256_511; 959 uint64_t sf_rx_pkts_512_1023; 960 uint64_t sf_rx_pkts_1024_1518; 961 uint32_t sf_rx_frames_lost; 962 uint32_t sf_tx_underruns; 963 uint32_t sf_tx_gfp_stall; 964 uint32_t sf_rx_gfp_stall; 965}; 966 967/* 968 * register space access macros 969 */ 970#define CSR_WRITE_4(sc, reg, val) \ 971 bus_write_4((sc)->sf_res, reg, val) 972 973#define CSR_READ_4(sc, reg) \ 974 bus_read_4((sc)->sf_res, reg) 975 976#define CSR_READ_1(sc, reg) \ 977 bus_read_1((sc)->sf_res, reg) 978 979 980struct sf_type { 981 uint16_t sf_vid; 982 uint16_t sf_did; 983 char *sf_name; 984 uint16_t sf_sdid; 985 char *sf_sname; 986}; 987 988/* Use Tx descriptor type 2 : 64bit buffer descriptor */ 989#define sf_tx_rdesc sf_tx_bufdesc_type2 990/* Use Rx descriptor type 1 : 64bit buffer descriptor */ 991#define sf_rx_rdesc sf_rx_bufdesc_type1 992/* Use Tx completion type 0 */ 993#define sf_tx_rcdesc sf_tx_cmpdesc_type0 994/* Use Rx completion type 2 : checksum */ 995#define sf_rx_rcdesc sf_rx_cmpdesc_type2 996 997#define SF_TX_DLIST_CNT 256 998#define SF_RX_DLIST_CNT 256 999#define SF_TX_CLIST_CNT 1024 1000#define SF_RX_CLIST_CNT 1024 1001#define SF_TX_DLIST_SIZE (sizeof(struct sf_tx_rdesc) * SF_TX_DLIST_CNT) 1002#define SF_TX_CLIST_SIZE (sizeof(struct sf_tx_rcdesc) * SF_TX_CLIST_CNT) 1003#define SF_RX_DLIST_SIZE (sizeof(struct sf_rx_rdesc) * SF_RX_DLIST_CNT) 1004#define SF_RX_CLIST_SIZE (sizeof(struct sf_rx_rcdesc) * SF_RX_CLIST_CNT) 1005#define SF_RING_ALIGN 256 1006#define SF_RX_ALIGN sizeof(uint32_t) 1007#define SF_MAXTXSEGS 16 1008 1009#define SF_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff) 1010#define SF_ADDR_HI(x) ((uint64_t)(x) >> 32) 1011#define SF_TX_DLIST_ADDR(sc, i) \ 1012 ((sc)->sf_rdata.sf_tx_ring_paddr + sizeof(struct sf_tx_rdesc) * (i)) 1013#define SF_TX_CLIST_ADDR(sc, i) \ 1014 ((sc)->sf_rdata.sf_tx_cring_paddr + sizeof(struct sf_tx_crdesc) * (i)) 1015#define SF_RX_DLIST_ADDR(sc, i) \ 1016 ((sc)->sf_rdata.sf_rx_ring_paddr + sizeof(struct sf_rx_rdesc) * (i)) 1017#define SF_RX_CLIST_ADDR(sc, i) \ 1018 ((sc)->sf_rdata.sf_rx_cring_paddr + sizeof(struct sf_rx_rcdesc) * (i)) 1019 1020#define SF_INC(x, y) (x) = ((x) + 1) % y 1021 1022#define SF_MAX_FRAMELEN 1536 1023#define SF_TX_THRESHOLD_UNIT 16 1024#define SF_MAX_TX_THRESHOLD (SF_MAX_FRAMELEN / SF_TX_THRESHOLD_UNIT) 1025#define SF_MIN_TX_THRESHOLD (128 / SF_TX_THRESHOLD_UNIT) 1026 1027struct sf_txdesc { 1028 struct mbuf *tx_m; 1029 int ndesc; 1030 bus_dmamap_t tx_dmamap; 1031}; 1032 1033struct sf_rxdesc { 1034 struct mbuf *rx_m; 1035 bus_dmamap_t rx_dmamap; 1036}; 1037 1038struct sf_chain_data { 1039 bus_dma_tag_t sf_parent_tag; 1040 bus_dma_tag_t sf_tx_tag; 1041 struct sf_txdesc sf_txdesc[SF_TX_DLIST_CNT]; 1042 bus_dma_tag_t sf_rx_tag; 1043 struct sf_rxdesc sf_rxdesc[SF_RX_DLIST_CNT]; 1044 bus_dma_tag_t sf_tx_ring_tag; 1045 bus_dma_tag_t sf_rx_ring_tag; 1046 bus_dma_tag_t sf_tx_cring_tag; 1047 bus_dma_tag_t sf_rx_cring_tag; 1048 bus_dmamap_t sf_tx_ring_map; 1049 bus_dmamap_t sf_rx_ring_map; 1050 bus_dmamap_t sf_rx_sparemap; 1051 bus_dmamap_t sf_tx_cring_map; 1052 bus_dmamap_t sf_rx_cring_map; 1053 int sf_tx_prod; 1054 int sf_tx_cnt; 1055 int sf_txc_cons; 1056 int sf_rxc_cons; 1057}; 1058 1059struct sf_ring_data { 1060 struct sf_tx_rdesc *sf_tx_ring; 1061 bus_addr_t sf_tx_ring_paddr; 1062 struct sf_tx_rcdesc *sf_tx_cring; 1063 bus_addr_t sf_tx_cring_paddr; 1064 struct sf_rx_rdesc *sf_rx_ring; 1065 bus_addr_t sf_rx_ring_paddr; 1066 struct sf_rx_rcdesc *sf_rx_cring; 1067 bus_addr_t sf_rx_cring_paddr; 1068}; 1069 1070 1071struct sf_softc { 1072 struct ifnet *sf_ifp; /* interface info */ 1073 device_t sf_dev; /* device info */ 1074 void *sf_intrhand; /* interrupt handler cookie */ 1075 struct resource *sf_irq; /* irq resource descriptor */ 1076 struct resource *sf_res; /* mem/ioport resource */ 1077 int sf_restype; 1078 int sf_rid; 1079 struct sf_type *sf_info; /* Starfire adapter info */ 1080 device_t sf_miibus; 1081 struct sf_chain_data sf_cdata; 1082 struct sf_ring_data sf_rdata; 1083 int sf_if_flags; 1084 struct callout sf_co; 1085 int sf_watchdog_timer; 1086 int sf_link; 1087 int sf_suspended; 1088 int sf_detach; 1089 uint32_t sf_txthresh; 1090 int sf_int_mod; 1091 struct sf_stats sf_statistics; 1092 struct mtx sf_mtx; 1093#ifdef DEVICE_POLLING 1094 int rxcycles; 1095#endif /* DEVICE_POLLING */ 1096}; 1097 1098 1099#define SF_LOCK(_sc) mtx_lock(&(_sc)->sf_mtx) 1100#define SF_UNLOCK(_sc) mtx_unlock(&(_sc)->sf_mtx) 1101#define SF_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sf_mtx, MA_OWNED) 1102 1103#define SF_TIMEOUT 1000 1104