1252206Sdavidcs/* 2252206Sdavidcs * Copyright (c) 2013-2014 Qlogic Corporation 3252206Sdavidcs * All rights reserved. 4252206Sdavidcs * 5252206Sdavidcs * Redistribution and use in source and binary forms, with or without 6252206Sdavidcs * modification, are permitted provided that the following conditions 7252206Sdavidcs * are met: 8252206Sdavidcs * 9252206Sdavidcs * 1. Redistributions of source code must retain the above copyright 10252206Sdavidcs * notice, this list of conditions and the following disclaimer. 11252206Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12252206Sdavidcs * notice, this list of conditions and the following disclaimer in the 13252206Sdavidcs * documentation and/or other materials provided with the distribution. 14252206Sdavidcs * 15252206Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16252206Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17252206Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18252206Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19252206Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20252206Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21252206Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22252206Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23252206Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24252206Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25252206Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26252206Sdavidcs * 27252206Sdavidcs * $FreeBSD$ 28252206Sdavidcs */ 29252206Sdavidcs/* 30252206Sdavidcs * File: qls_hw.h 31252206Sdavidcs * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32252206Sdavidcs */ 33252206Sdavidcs#ifndef _QLS_HW_H_ 34252206Sdavidcs#define _QLS_HW_H_ 35252206Sdavidcs 36252206Sdavidcs#define Q8_MAX_NUM_MULTICAST_ADDRS 32 37252206Sdavidcs#define Q8_MAC_ADDR_LEN 6 38252206Sdavidcs 39252206Sdavidcs#define BIT_0 (0x1 << 0) 40252206Sdavidcs#define BIT_1 (0x1 << 1) 41252206Sdavidcs#define BIT_2 (0x1 << 2) 42252206Sdavidcs#define BIT_3 (0x1 << 3) 43252206Sdavidcs#define BIT_4 (0x1 << 4) 44252206Sdavidcs#define BIT_5 (0x1 << 5) 45252206Sdavidcs#define BIT_6 (0x1 << 6) 46252206Sdavidcs#define BIT_7 (0x1 << 7) 47252206Sdavidcs#define BIT_8 (0x1 << 8) 48252206Sdavidcs#define BIT_9 (0x1 << 9) 49252206Sdavidcs#define BIT_10 (0x1 << 10) 50252206Sdavidcs#define BIT_11 (0x1 << 11) 51252206Sdavidcs#define BIT_12 (0x1 << 12) 52252206Sdavidcs#define BIT_13 (0x1 << 13) 53252206Sdavidcs#define BIT_14 (0x1 << 14) 54252206Sdavidcs#define BIT_15 (0x1 << 15) 55252206Sdavidcs#define BIT_16 (0x1 << 16) 56252206Sdavidcs#define BIT_17 (0x1 << 17) 57252206Sdavidcs#define BIT_18 (0x1 << 18) 58252206Sdavidcs#define BIT_19 (0x1 << 19) 59252206Sdavidcs#define BIT_20 (0x1 << 20) 60252206Sdavidcs#define BIT_21 (0x1 << 21) 61252206Sdavidcs#define BIT_22 (0x1 << 22) 62252206Sdavidcs#define BIT_23 (0x1 << 23) 63252206Sdavidcs#define BIT_24 (0x1 << 24) 64252206Sdavidcs#define BIT_25 (0x1 << 25) 65252206Sdavidcs#define BIT_11 (0x1 << 11) 66252206Sdavidcs#define BIT_12 (0x1 << 12) 67252206Sdavidcs#define BIT_13 (0x1 << 13) 68252206Sdavidcs#define BIT_14 (0x1 << 14) 69252206Sdavidcs#define BIT_15 (0x1 << 15) 70252206Sdavidcs#define BIT_16 (0x1 << 16) 71252206Sdavidcs#define BIT_17 (0x1 << 17) 72252206Sdavidcs#define BIT_18 (0x1 << 18) 73252206Sdavidcs#define BIT_19 (0x1 << 19) 74252206Sdavidcs#define BIT_20 (0x1 << 20) 75252206Sdavidcs#define BIT_21 (0x1 << 21) 76252206Sdavidcs#define BIT_22 (0x1 << 22) 77252206Sdavidcs#define BIT_23 (0x1 << 23) 78252206Sdavidcs#define BIT_24 (0x1 << 24) 79252206Sdavidcs#define BIT_25 (0x1 << 25) 80252206Sdavidcs#define BIT_26 (0x1 << 26) 81252206Sdavidcs#define BIT_27 (0x1 << 27) 82252206Sdavidcs#define BIT_28 (0x1 << 28) 83252206Sdavidcs#define BIT_29 (0x1 << 29) 84252206Sdavidcs#define BIT_30 (0x1 << 30) 85252206Sdavidcs#define BIT_31 (0x1 << 31) 86252206Sdavidcs 87252206Sdavidcs 88252206Sdavidcs/* 89252206Sdavidcs * Firmware Interface 90252206Sdavidcs */ 91252206Sdavidcs 92252206Sdavidcs/********************************************************************* 93252206Sdavidcs * Work Queue Register Map 94252206Sdavidcs *********************************************************************/ 95252206Sdavidcs#define Q81_WRKQ_INDEX_REG 0x00 96252206Sdavidcs#define Q81_WRKQ_CONS_INDEX_MASK 0xFFFF0000 97252206Sdavidcs#define Q81_WRKQ_PROD_INDEX_MASK 0x0000FFFF 98252206Sdavidcs#define Q81_WRKQ_VALID_REG 0x04 99252206Sdavidcs#define Q81_WRKQ_VALID_ONQ BIT_25 100252206Sdavidcs#define Q81_WRKQ_VALID_V BIT_4 101252206Sdavidcs 102252206Sdavidcs/********************************************************************* 103252206Sdavidcs * Completion Queue Register Map 104252206Sdavidcs *********************************************************************/ 105252206Sdavidcs#define Q81_COMPQ_INDEX_REG 0x00 106252206Sdavidcs#define Q81_COMPQ_PROD_INDEX_MASK 0xFFFF0000 107252206Sdavidcs#define Q81_COMPQ_CONS_INDEX_MASK 0x0000FFFF 108252206Sdavidcs#define Q81_COMPQ_VALID_REG 0x04 109252206Sdavidcs#define Q81_COMPQ_VALID_V BIT_4 110252206Sdavidcs#define Q81_LRGBQ_INDEX_REG 0x18 111252206Sdavidcs#define Q81_LRGBQ_CONS_INDEX_MASK 0xFFFF0000 112252206Sdavidcs#define Q81_LRGBQ_PROD_INDEX_MASK 0x0000FFFF 113252206Sdavidcs#define Q81_SMBQ_INDEX_REG 0x1C 114252206Sdavidcs#define Q81_SMBQ_CONS_INDEX_MASK 0xFFFF0000 115252206Sdavidcs#define Q81_SMBQ_PROD_INDEX_MASK 0x0000FFFF 116252206Sdavidcs 117252206Sdavidcs/********************************************************************* 118252206Sdavidcs * Control Register Definitions 119252206Sdavidcs * (Access, Function Specific, Shared via Semaphore, Control by MPI FW) 120252206Sdavidcs *********************************************************************/ 121252206Sdavidcs#define Q81_CTL_PROC_ADDR 0x00 /* R/W - Y - */ 122252206Sdavidcs#define Q81_CTL_PROC_DATA 0x04 /* R/W - Y - */ 123252206Sdavidcs#define Q81_CTL_SYSTEM 0x08 /* MWR - - - */ 124252206Sdavidcs#define Q81_CTL_RESET 0x0C /* MWR Y - - */ 125252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC 0x10 /* MWR Y - - */ 126252206Sdavidcs#define Q81_CTL_HOST_CMD_STATUS 0x14 /* R/W Y - - */ 127252206Sdavidcs#define Q81_CTL_LED 0x18 /* R/W Y - Y */ 128252206Sdavidcs#define Q81_CTL_ICB_ACCESS_ADDR_LO 0x20 /* R/W - Y - */ 129252206Sdavidcs#define Q81_CTL_ICB_ACCESS_ADDR_HI 0x24 /* R/W - Y - */ 130252206Sdavidcs#define Q81_CTL_CONFIG 0x28 /* MWR - - - */ 131252206Sdavidcs#define Q81_CTL_STATUS 0x30 /* MWR Y - - */ 132252206Sdavidcs#define Q81_CTL_INTR_ENABLE 0x34 /* MWR Y - - */ 133252206Sdavidcs#define Q81_CTL_INTR_MASK 0x38 /* MWR Y - - */ 134252206Sdavidcs#define Q81_CTL_INTR_STATUS1 0x3C /* RO Y - - */ 135252206Sdavidcs#define Q81_CTL_INTR_STATUS2 0x40 /* RO Y - - */ 136252206Sdavidcs#define Q81_CTL_INTR_STATUS3 0x44 /* RO Y - - */ 137252206Sdavidcs#define Q81_CTL_INTR_STATUS4 0x48 /* RO Y - - */ 138252206Sdavidcs#define Q81_CTL_REV_ID 0x4C /* RO - - - */ 139252206Sdavidcs#define Q81_CTL_FATAL_ERR_STATUS 0x54 /* RO Y - - */ 140252206Sdavidcs#define Q81_CTL_COR_ECC_ERR_COUNTER 0x60 /* RO Y - - */ 141252206Sdavidcs#define Q81_CTL_SEMAPHORE 0x64 /* MWR Y - - */ 142252206Sdavidcs#define Q81_CTL_GPIO1 0x68 /* MWR Y - - */ 143252206Sdavidcs#define Q81_CTL_GPIO2 0x6C /* MWR Y - - */ 144252206Sdavidcs#define Q81_CTL_GPIO3 0x70 /* MWR Y - - */ 145252206Sdavidcs#define Q81_CTL_XGMAC_ADDR 0x78 /* R/W Y Y - */ 146252206Sdavidcs#define Q81_CTL_XGMAC_DATA 0x7C /* R/W Y Y Y */ 147252206Sdavidcs#define Q81_CTL_NIC_ENH_TX_SCHD 0x80 /* R/W Y - Y */ 148252206Sdavidcs#define Q81_CTL_CNA_ENH_TX_SCHD 0x84 /* R/W Y - Y */ 149252206Sdavidcs#define Q81_CTL_FLASH_ADDR 0x88 /* R/W - Y - */ 150252206Sdavidcs#define Q81_CTL_FLASH_DATA 0x8C /* R/W - Y - */ 151252206Sdavidcs#define Q81_CTL_STOP_CQ_PROCESSING 0x90 /* MWR Y - - */ 152252206Sdavidcs#define Q81_CTL_MAC_PROTO_ADDR_INDEX 0xA8 /* R/W - Y - */ 153252206Sdavidcs#define Q81_CTL_MAC_PROTO_ADDR_DATA 0xAC /* R/W - Y - */ 154252206Sdavidcs#define Q81_CTL_COS_DEF_CQ1 0xB0 /* R/W Y - - */ 155252206Sdavidcs#define Q81_CTL_COS_DEF_CQ2 0xB4 /* R/W Y - - */ 156252206Sdavidcs#define Q81_CTL_ETHERTYPE_SKIP_1 0xB8 /* R/W Y - - */ 157252206Sdavidcs#define Q81_CTL_ETHERTYPE_SKIP_2 0xBC /* R/W Y - - */ 158252206Sdavidcs#define Q81_CTL_SPLIT_HDR 0xC0 /* R/W Y - - */ 159252206Sdavidcs#define Q81_CTL_NIC_PAUSE_THRES 0xC8 /* R/W Y - Y */ 160252206Sdavidcs#define Q81_CTL_NIC_RCV_CONFIG 0xD4 /* MWR Y - Y */ 161252206Sdavidcs#define Q81_CTL_COS_TAGS_IN_NIC_FIFO 0xDC /* R/W Y - Y */ 162252206Sdavidcs#define Q81_CTL_MGMT_RCV_CONFIG 0xE0 /* MWR Y - Y */ 163252206Sdavidcs#define Q81_CTL_ROUTING_INDEX 0xE4 /* R/W Y Y - */ 164252206Sdavidcs#define Q81_CTL_ROUTING_DATA 0xE8 /* R/W Y Y - */ 165252206Sdavidcs#define Q81_CTL_XG_SERDES_ADDR 0xF0 /* R/W Y Y Y */ 166252206Sdavidcs#define Q81_CTL_XG_SERDES_DATA 0xF4 /* R/W Y Y Y */ 167252206Sdavidcs#define Q81_CTL_XG_PROBE_MUX_ADDR 0xF8 /* R/W - Y - */ 168252206Sdavidcs#define Q81_CTL_XG_PROBE_MUX_DATA 0xFC /* R/W - Y - */ 169252206Sdavidcs 170252206Sdavidcs 171252206Sdavidcs/* 172252206Sdavidcs * Process Address Register (0x00) 173252206Sdavidcs */ 174252206Sdavidcs#define Q81_CTL_PROC_ADDR_RDY BIT_31 175252206Sdavidcs#define Q81_CTL_PROC_ADDR_READ BIT_30 176252206Sdavidcs#define Q81_CTL_PROC_ADDR_ERR BIT_29 177252206Sdavidcs#define Q81_CTL_PROC_ADDR_MPI_RISC (0x00 << 16) 178252206Sdavidcs#define Q81_CTL_PROC_ADDR_MDE (0x01 << 16) 179252206Sdavidcs#define Q81_CTL_PROC_ADDR_REG_BLOCK (0x02 << 16) 180252206Sdavidcs#define Q81_CTL_PROC_ADDR_RISC_INT_REG (0x03 << 16) 181252206Sdavidcs 182252206Sdavidcs 183252206Sdavidcs/* 184252206Sdavidcs * System Register (0x08) 185252206Sdavidcs */ 186252206Sdavidcs#define Q81_CTL_SYSTEM_MASK_SHIFT 16 187252206Sdavidcs#define Q81_CTL_SYSTEM_ENABLE_VQM_WR BIT_5 188252206Sdavidcs#define Q81_CTL_SYSTEM_ENABLE_DWC BIT_4 189252206Sdavidcs#define Q81_CTL_SYSTEM_ENABLE_DA_SINGLE_THRD BIT_3 190252206Sdavidcs#define Q81_CTL_SYSTEM_ENABLE_MDC BIT_2 191252206Sdavidcs#define Q81_CTL_SYSTEM_ENABLE_FAE BIT_1 192252206Sdavidcs#define Q81_CTL_SYSTEM_ENABLE_EFE BIT_0 193252206Sdavidcs 194252206Sdavidcs/* 195252206Sdavidcs * Reset Register (0x0C) 196252206Sdavidcs */ 197252206Sdavidcs#define Q81_CTL_RESET_MASK_SHIFT 16 198252206Sdavidcs#define Q81_CTL_RESET_FUNC BIT_15 199252206Sdavidcs#define Q81_CTL_RESET_RR_SHIFT 1 200252206Sdavidcs 201252206Sdavidcs/* 202252206Sdavidcs * Function Specific Control Register (0x10) 203252206Sdavidcs */ 204252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_MASK_SHIFT 16 205252206Sdavidcs 206252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_FE BIT_15 207252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_STE BIT_13 208252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DSB BIT_12 209252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_SH BIT_11 210252206Sdavidcs 211252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_MASK (0x7 << 8) 212252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_2K (0x1 << 8) 213252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_4K (0x2 << 8) 214252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_8K (0x3 << 8) 215252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_64K (0x6 << 8) 216252206Sdavidcs 217252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_EPC_O BIT_7 218252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_EPC_I BIT_6 219252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_EC BIT_5 220252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBL_DBRST (0x00 << 3) 221252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_PAYLDSZ (0x01 << 3) 222252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_RDBRSTSZ (0x02 << 3) 223252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBL_128 (0x03 << 3) 224252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBRST_256 0x00 225252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBRST_512 0x01 226252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBRST_768 0x02 227252206Sdavidcs#define Q81_CTL_FUNC_SPECIFIC_DBRST_1024 0x03 228252206Sdavidcs 229252206Sdavidcs 230252206Sdavidcs/* 231252206Sdavidcs * Host Command/Status Register (0x14) 232252206Sdavidcs */ 233252206Sdavidcs#define Q81_CTL_HCS_CMD_NOP (0x00 << 28) 234252206Sdavidcs#define Q81_CTL_HCS_CMD_SET_RISC_RESET (0x01 << 28) 235252206Sdavidcs#define Q81_CTL_HCS_CMD_CLR_RISC_RESET (0x02 << 28) 236252206Sdavidcs#define Q81_CTL_HCS_CMD_SET_RISC_PAUSE (0x03 << 28) 237252206Sdavidcs#define Q81_CTL_HCS_CMD_CLR_RISC_PAUSE (0x04 << 28) 238252206Sdavidcs#define Q81_CTL_HCS_CMD_SET_HTR_INTR (0x05 << 28) 239252206Sdavidcs#define Q81_CTL_HCS_CMD_CLR_HTR_INTR (0x06 << 28) 240252206Sdavidcs#define Q81_CTL_HCS_CMD_SET_PARITY_EN (0x07 << 28) 241252206Sdavidcs#define Q81_CTL_HCS_CMD_FORCE_BAD_PARITY (0x08 << 28) 242252206Sdavidcs#define Q81_CTL_HCS_CMD_CLR_BAD_PARITY (0x09 << 28) 243252206Sdavidcs#define Q81_CTL_HCS_CMD_CLR_RTH_INTR (0x0A << 28) 244252206Sdavidcs 245252206Sdavidcs#define Q81_CTL_HCS_CMD_PAR_SHIFT 22 246252206Sdavidcs#define Q81_CTL_HCS_RISC_PAUSED BIT_10 247252206Sdavidcs#define Q81_CTL_HCS_HTR_INTR BIT_9 248252206Sdavidcs#define Q81_CTL_HCS_RISC_RESET BIT_8 249252206Sdavidcs#define Q81_CTL_HCS_ERR_STATUS_MASK 0x3F 250252206Sdavidcs 251252206Sdavidcs 252252206Sdavidcs/* 253252206Sdavidcs * Configuration Register (0x28) 254252206Sdavidcs */ 255252206Sdavidcs#define Q81_CTL_CONFIG_MASK_SHIFT 16 256252206Sdavidcs#define Q81_CTL_CONFIG_Q_NUM_SHIFT 8 257252206Sdavidcs#define Q81_CTL_CONFIG_Q_NUM_MASK (0x7F << Q81_CTL_CONFIG_Q_NUM_SHIFT) 258252206Sdavidcs#define Q81_CTL_CONFIG_DCQ BIT_7 259252206Sdavidcs#define Q81_CTL_CONFIG_LCQ BIT_6 260252206Sdavidcs#define Q81_CTL_CONFIG_LE BIT_5 261252206Sdavidcs#define Q81_CTL_CONFIG_DR BIT_3 262252206Sdavidcs#define Q81_CTL_CONFIG_LR BIT_2 263252206Sdavidcs#define Q81_CTL_CONFIG_DRQ BIT_1 264252206Sdavidcs#define Q81_CTL_CONFIG_LRQ BIT_0 265252206Sdavidcs 266252206Sdavidcs 267252206Sdavidcs/* 268252206Sdavidcs * Status Register (0x30) 269252206Sdavidcs */ 270252206Sdavidcs#define Q81_CTL_STATUS_MASK_SHIFT 16 271252206Sdavidcs#define Q81_CTL_STATUS_NFE BIT_12 272252206Sdavidcs#define Q81_CTL_STATUS_F3E BIT_11 273252206Sdavidcs#define Q81_CTL_STATUS_F2E BIT_10 274252206Sdavidcs#define Q81_CTL_STATUS_F1E BIT_9 275252206Sdavidcs#define Q81_CTL_STATUS_F0E BIT_8 276252206Sdavidcs#define Q81_CTL_STATUS_FUNC_SHIFT 6 277252206Sdavidcs#define Q81_CTL_STATUS_PI1 BIT_5 278252206Sdavidcs#define Q81_CTL_STATUS_PI0 BIT_4 279252206Sdavidcs#define Q81_CTL_STATUS_PL1 BIT_3 280252206Sdavidcs#define Q81_CTL_STATUS_PL0 BIT_2 281252206Sdavidcs#define Q81_CTL_STATUS_PI BIT_1 282252206Sdavidcs#define Q81_CTL_STATUS_FE BIT_0 283252206Sdavidcs 284252206Sdavidcs/* 285252206Sdavidcs * Interrupt Enable Register (0x34) 286252206Sdavidcs */ 287252206Sdavidcs#define Q81_CTL_INTRE_MASK_SHIFT 16 288252206Sdavidcs#define Q81_CTL_INTRE_EN BIT_15 289252206Sdavidcs#define Q81_CTL_INTRE_EI BIT_14 290252206Sdavidcs#define Q81_CTL_INTRE_IHD BIT_13 291252206Sdavidcs#define Q81_CTL_INTRE_RTYPE_MASK (0x3 << 8) 292252206Sdavidcs#define Q81_CTL_INTRE_RTYPE_ENABLE (0x1 << 8) 293252206Sdavidcs#define Q81_CTL_INTRE_RTYPE_DISABLE (0x2 << 8) 294252206Sdavidcs#define Q81_CTL_INTRE_RTYPE_SETUP_TO_RD (0x3 << 8) 295252206Sdavidcs#define Q81_CTL_INTRE_HOST_INTR_MASK 0x7F 296252206Sdavidcs 297252206Sdavidcs/* 298252206Sdavidcs * Interrupt Mask Register (0x38) 299252206Sdavidcs */ 300252206Sdavidcs#define Q81_CTL_INTRM_MASK_SHIFT 16 301252206Sdavidcs#define Q81_CTL_INTRM_MC BIT_7 302252206Sdavidcs#define Q81_CTL_INTRM_LSC BIT_6 303252206Sdavidcs#define Q81_CTL_INTRM_LH1 BIT_4 304252206Sdavidcs#define Q81_CTL_INTRM_HL1 BIT_3 305252206Sdavidcs#define Q81_CTL_INTRM_LH0 BIT_2 306252206Sdavidcs#define Q81_CTL_INTRM_HL0 BIT_1 307252206Sdavidcs#define Q81_CTL_INTRM_PI BIT_0 308252206Sdavidcs 309252206Sdavidcs/* 310252206Sdavidcs * Interrupt Status 1 Register (0x3C) 311252206Sdavidcs */ 312252206Sdavidcs#define Q81_CTL_INTRS1_COMPQ(i) (0x1 << i) 313252206Sdavidcs 314252206Sdavidcs/* 315252206Sdavidcs * Interrupt Status 2 Register (0x40) 316252206Sdavidcs */ 317252206Sdavidcs#define Q81_CTL_INTRS2_COMPQ(i) (0x1 << i) 318252206Sdavidcs 319252206Sdavidcs/* 320252206Sdavidcs * Interrupt Status 3 Register (0x44) 321252206Sdavidcs */ 322252206Sdavidcs#define Q81_CTL_INTRS3_COMPQ(i) (0x1 << i) 323252206Sdavidcs 324252206Sdavidcs/* 325252206Sdavidcs * Interrupt Status 4 Register (0x48) 326252206Sdavidcs */ 327252206Sdavidcs#define Q81_CTL_INTRS4_COMPQ(i) (0x1 << i) 328252206Sdavidcs 329252206Sdavidcs/* 330252206Sdavidcs * Revision ID Register (0x4C) 331252206Sdavidcs */ 332252206Sdavidcs#define Q81_CTL_REV_ID_CHIP_REV_MASK (0xF << 28) 333252206Sdavidcs#define Q81_CTL_REV_ID_XGMAC_RCV_MASK (0xF << 16) 334252206Sdavidcs#define Q81_CTL_REV_ID_XGMAC_ROLL_MASK (0xF << 8) 335252206Sdavidcs#define Q81_CTL_REV_ID_NIC_REV_MASK (0xF << 4) 336252206Sdavidcs#define Q81_CTL_REV_ID_NIC_ROLL_MASK (0xF << 0) 337252206Sdavidcs 338252206Sdavidcs/* 339252206Sdavidcs * Semaphore Register (0x64) 340252206Sdavidcs */ 341252206Sdavidcs 342252206Sdavidcs#define Q81_CTL_SEM_MASK_PROC_ADDR_NIC_RCV 0xC0000000 343252206Sdavidcs 344252206Sdavidcs#define Q81_CTL_SEM_MASK_RIDX_DATAREG 0x30000000 345252206Sdavidcs 346252206Sdavidcs#define Q81_CTL_SEM_MASK_FLASH 0x03000000 347252206Sdavidcs 348252206Sdavidcs#define Q81_CTL_SEM_MASK_MAC_SERDES 0x00C00000 349252206Sdavidcs 350252206Sdavidcs#define Q81_CTL_SEM_MASK_ICB 0x00300000 351252206Sdavidcs 352252206Sdavidcs#define Q81_CTL_SEM_MASK_XGMAC1 0x000C0000 353252206Sdavidcs 354252206Sdavidcs#define Q81_CTL_SEM_MASK_XGMAC0 0x00030000 355252206Sdavidcs 356252206Sdavidcs#define Q81_CTL_SEM_SET_PROC_ADDR_NIC_RCV 0x4000 357252206Sdavidcs#define Q81_CTL_SEM_SET_RIDX_DATAREG 0x1000 358252206Sdavidcs#define Q81_CTL_SEM_SET_FLASH 0x0100 359252206Sdavidcs#define Q81_CTL_SEM_SET_MAC_SERDES 0x0040 360252206Sdavidcs#define Q81_CTL_SEM_SET_ICB 0x0010 361252206Sdavidcs#define Q81_CTL_SEM_SET_XGMAC1 0x0004 362252206Sdavidcs#define Q81_CTL_SEM_SET_XGMAC0 0x0001 363252206Sdavidcs 364252206Sdavidcs 365252206Sdavidcs/* 366252206Sdavidcs * Flash Address Register (0x88) 367252206Sdavidcs */ 368252206Sdavidcs#define Q81_CTL_FLASH_ADDR_RDY BIT_31 369252206Sdavidcs#define Q81_CTL_FLASH_ADDR_R BIT_30 370252206Sdavidcs#define Q81_CTL_FLASH_ADDR_ERR BIT_29 371252206Sdavidcs#define Q81_CTL_FLASH_ADDR_MASK 0x7FFFFF 372252206Sdavidcs 373252206Sdavidcs/* 374252206Sdavidcs * Stop CQ Processing Register (0x90) 375252206Sdavidcs */ 376252206Sdavidcs#define Q81_CTL_STOP_CQ_MASK_SHIFT 16 377252206Sdavidcs#define Q81_CTL_STOP_CQ_EN BIT_15 378252206Sdavidcs#define Q81_CTL_STOP_CQ_RQ_STARTQ (0x1 << 8) 379252206Sdavidcs#define Q81_CTL_STOP_CQ_RQ_STOPQ (0x2 << 8) 380252206Sdavidcs#define Q81_CTL_STOP_CQ_RQ_READ (0x3 << 8) 381252206Sdavidcs#define Q81_CTL_STOP_CQ_MASK 0x7F 382252206Sdavidcs 383252206Sdavidcs/* 384252206Sdavidcs * MAC Protocol Address Index Register (0xA8) 385252206Sdavidcs */ 386252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_MW BIT_31 387252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_MR BIT_30 388252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_E BIT_27 389252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_RS BIT_26 390252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_ADR BIT_25 391252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_SHIFT 16 392252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MASK 0xF0000 393252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_IDX_SHIFT 4 394252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_IDX_MASK 0xFFF0 395252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_OFF_MASK 0xF 396252206Sdavidcs 397252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_CAM_MAC (0 << 16) 398252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST (1 << 16) 399252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_VLAN (2 << 16) 400252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST_FILTER (3 << 16) 401252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_MAC (5 << 16) 402252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMMT_VLAN (6 << 16) 403252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV4 (7 << 16) 404252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV6 (8 << 16) 405252206Sdavidcs#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_PORT (9 << 16) /* TCP/UDP Port */ 406252206Sdavidcs 407252206Sdavidcs/* 408252206Sdavidcs * CAM MAC offset 2 definitions 409252206Sdavidcs */ 410252206Sdavidcs#define Q81_CAM_MAC_OFF2_ROUTE_FC 0x00000000 411252206Sdavidcs#define Q81_CAM_MAC_OFF2_ROUTE_NIC 0x00000001 412252206Sdavidcs#define Q81_CAM_MAC_OFF2_FUNC_SHIFT 2 413252206Sdavidcs#define Q81_CAM_MAC_OFF2_RV 0x00000010 414252206Sdavidcs#define Q81_CAM_MAC_OFF2_CQID_SHIFT 5 415252206Sdavidcs#define Q81_CAM_MAC_OFF2_SH 0x00008000 416252206Sdavidcs#define Q81_CAM_MAC_OFF2_MHT 0x40000000 417252206Sdavidcs#define Q81_CAM_MAC_OFF2_VLD 0x80000000 418252206Sdavidcs 419252206Sdavidcs/* 420252206Sdavidcs * NIC Pause Threshold Register (0xC8) 421252206Sdavidcs */ 422252206Sdavidcs#define Q81_CTL_NIC_PAUSE_THRES_PAUSE_SHIFT 16 423252206Sdavidcs#define Q81_CTL_NIC_PAUSE_THRES_RESUME_SHIFT 0 424252206Sdavidcs 425252206Sdavidcs/* 426252206Sdavidcs * NIC Receive Configuration Register (0xD4) 427252206Sdavidcs */ 428252206Sdavidcs#define Q81_CTL_NIC_RCVC_MASK_SHIFT 16 429252206Sdavidcs#define Q81_CTL_NIC_RCVC_DCQ_SHIFT 8 430252206Sdavidcs#define Q81_CTL_NIC_RCVC_DCQ_MASK 0x7F00 431252206Sdavidcs#define Q81_CTL_NIC_RCVC_DTP BIT_5 432252206Sdavidcs#define Q81_CTL_NIC_RCVC_R4T BIT_4 433252206Sdavidcs#define Q81_CTL_NIC_RCVC_RV BIT_3 434252206Sdavidcs#define Q81_CTL_NIC_RCVC_VLAN_ALL (0x0 << 1) 435252206Sdavidcs#define Q81_CTL_NIC_RCVC_VLAN_ONLY (0x1 << 1) 436252206Sdavidcs#define Q81_CTL_NIC_RCVC_VLAN_NON_VLAN (0x2 << 1) 437252206Sdavidcs#define Q81_CTL_NIC_RCVC_VLAN_REJECT (0x3 << 1) 438252206Sdavidcs#define Q81_CTL_NIC_RCVC_PPE BIT_0 439252206Sdavidcs 440252206Sdavidcs 441252206Sdavidcs/* 442252206Sdavidcs * Routing Index Register (0xE4) 443252206Sdavidcs */ 444252206Sdavidcs#define Q81_CTL_RI_MW BIT_31 445252206Sdavidcs#define Q81_CTL_RI_MR BIT_30 446252206Sdavidcs#define Q81_CTL_RI_E BIT_27 447252206Sdavidcs#define Q81_CTL_RI_RS BIT_26 448252206Sdavidcs 449252206Sdavidcs#define Q81_CTL_RI_DST_RSS (0x00 << 20) 450252206Sdavidcs#define Q81_CTL_RI_DST_CAMQ (0x01 << 20) 451252206Sdavidcs#define Q81_CTL_RI_DST_COSQ (0x02 << 20) 452252206Sdavidcs#define Q81_CTL_RI_DST_DFLTQ (0x03 << 20) 453252206Sdavidcs#define Q81_CTL_RI_DST_DESTQ (0x04 << 20) 454252206Sdavidcs#define Q81_CTL_RI_DST_DROP (0x07 << 20) 455252206Sdavidcs 456252206Sdavidcs#define Q81_CTL_RI_TYPE_RTMASK (0x00 << 16) 457252206Sdavidcs#define Q81_CTL_RI_TYPE_RTINVMASK (0x01 << 16) 458252206Sdavidcs#define Q81_CTL_RI_TYPE_NICQMASK (0x02 << 16) 459252206Sdavidcs#define Q81_CTL_RI_TYPE_NICQINVMASK (0x03 << 16) 460252206Sdavidcs 461252206Sdavidcs/* these indices for the Routing Index Register are user defined */ 462252206Sdavidcs#define Q81_CTL_RI_IDX_ALL_ERROR (0x00 << 8) 463252206Sdavidcs#define Q81_CTL_RI_IDX_MAC_ERROR (0x00 << 8) 464252206Sdavidcs#define Q81_CTL_RI_IDX_IPCSUM_ERROR (0x01 << 8) 465252206Sdavidcs#define Q81_CTL_RI_IDX_TCPCSUM_ERROR (0x02 << 8) 466252206Sdavidcs#define Q81_CTL_RI_IDX_BCAST (0x03 << 8) 467252206Sdavidcs#define Q81_CTL_RI_IDX_MCAST_MATCH (0x04 << 8) 468252206Sdavidcs#define Q81_CTL_RI_IDX_ALLMULTI (0x05 << 8) 469252206Sdavidcs#define Q81_CTL_RI_IDX_RSS_MATCH (0x08 << 8) 470252206Sdavidcs#define Q81_CTL_RI_IDX_RSS_IPV4 (0x08 << 8) 471252206Sdavidcs#define Q81_CTL_RI_IDX_RSS_IPV6 (0x09 << 8) 472252206Sdavidcs#define Q81_CTL_RI_IDX_RSS_TCPV4 (0x0A << 8) 473252206Sdavidcs#define Q81_CTL_RI_IDX_RSS_TCPV6 (0x0B << 8) 474252206Sdavidcs#define Q81_CTL_RI_IDX_CAM_HIT (0x0C << 8) 475252206Sdavidcs#define Q81_CTL_RI_IDX_PROMISCUOUS (0x0F << 8) 476252206Sdavidcs 477252206Sdavidcs/* Routing Masks to be loaded into Routing Data Register */ 478252206Sdavidcs#define Q81_CTL_RD_BCAST BIT_0 479252206Sdavidcs#define Q81_CTL_RD_MCAST BIT_1 480252206Sdavidcs#define Q81_CTL_RD_MCAST_MATCH BIT_2 481252206Sdavidcs#define Q81_CTL_RD_MCAST_REG_MATCH BIT_3 482252206Sdavidcs#define Q81_CTL_RD_MCAST_HASH_MATCH BIT_4 483252206Sdavidcs#define Q81_CTL_RD_CAM_HIT BIT_7 484252206Sdavidcs#define Q81_CTL_RD_CAM_BIT0 BIT_8 485252206Sdavidcs#define Q81_CTL_RD_CAM_BIT1 BIT_9 486252206Sdavidcs#define Q81_CTL_RD_VLAN_TAG_PRESENT BIT_10 487252206Sdavidcs#define Q81_CTL_RD_VLAN_MATCH BIT_11 488252206Sdavidcs#define Q81_CTL_RD_VLAN_FILTER_PASS BIT_12 489252206Sdavidcs#define Q81_CTL_RD_SKIP_ETHERTYPE_1 BIT_13 490252206Sdavidcs#define Q81_CTL_RD_SKIP_ETHERTYPE_2 BIT_14 491252206Sdavidcs#define Q81_CTL_RD_BCAST_OR_MCAST_MATCH BIT_15 492252206Sdavidcs#define Q81_CTL_RD_802_3_PKT BIT_16 493252206Sdavidcs#define Q81_CTL_RD_LLDP_PKT BIT_17 494252206Sdavidcs#define Q81_CTL_RD_TUNNELED_PKT BIT_18 495252206Sdavidcs#define Q81_CTL_RD_ERROR_PKT BIT_22 496252206Sdavidcs#define Q81_CTL_RD_VALID_PKT BIT_23 497252206Sdavidcs#define Q81_CTL_RD_TCP_UDP_CSUM_ERR BIT_24 498252206Sdavidcs#define Q81_CTL_RD_IPCSUM_ERR BIT_25 499252206Sdavidcs#define Q81_CTL_RD_MAC_ERR BIT_26 500252206Sdavidcs#define Q81_CTL_RD_RSS_TCP_IPV6 BIT_27 501252206Sdavidcs#define Q81_CTL_RD_RSS_TCP_IPV4 BIT_28 502252206Sdavidcs#define Q81_CTL_RD_RSS_IPV6 BIT_29 503252206Sdavidcs#define Q81_CTL_RD_RSS_IPV4 BIT_30 504252206Sdavidcs#define Q81_CTL_RD_RSS_MATCH BIT_31 505252206Sdavidcs 506252206Sdavidcs 507252206Sdavidcs/********************************************************************* 508252206Sdavidcs * Host Data Structures * 509252206Sdavidcs *********************************************************************/ 510252206Sdavidcs 511252206Sdavidcs/* 512252206Sdavidcs * Work Queue Initialization Control Block 513252206Sdavidcs */ 514252206Sdavidcs 515252206Sdavidcstypedef struct _q81_wq_icb { 516252206Sdavidcs 517252206Sdavidcs uint16_t length_v; 518252206Sdavidcs#define Q81_WQ_ICB_VALID BIT_4 519252206Sdavidcs 520252206Sdavidcs uint8_t pri; 521252206Sdavidcs#define Q81_WQ_ICB_PRI_SHIFT 1 522252206Sdavidcs 523252206Sdavidcs uint8_t flags; 524252206Sdavidcs#define Q81_WQ_ICB_FLAGS_LO BIT_7 525252206Sdavidcs#define Q81_WQ_ICB_FLAGS_LI BIT_6 526252206Sdavidcs#define Q81_WQ_ICB_FLAGS_LB BIT_5 527252206Sdavidcs#define Q81_WQ_ICB_FLAGS_LC BIT_4 528252206Sdavidcs 529252206Sdavidcs uint16_t wqcqid_rss; 530252206Sdavidcs#define Q81_WQ_ICB_RSS_V BIT_15 531252206Sdavidcs 532252206Sdavidcs uint16_t rsrvd; 533252206Sdavidcs 534252206Sdavidcs uint32_t baddr_lo; 535252206Sdavidcs uint32_t baddr_hi; 536252206Sdavidcs 537252206Sdavidcs uint32_t ci_addr_lo; 538252206Sdavidcs uint32_t ci_addr_hi; 539252206Sdavidcs} __packed q81_wq_icb_t; 540252206Sdavidcs 541252206Sdavidcs 542252206Sdavidcs/* 543252206Sdavidcs * Completion Queue Initialization Control Block 544252206Sdavidcs */ 545252206Sdavidcs 546252206Sdavidcstypedef struct _q81_cq_icb { 547252206Sdavidcs uint8_t msix_vector; 548252206Sdavidcs uint16_t rsrvd0; 549252206Sdavidcs uint8_t flags; 550252206Sdavidcs#define Q81_CQ_ICB_FLAGS_LC BIT_7 551252206Sdavidcs#define Q81_CQ_ICB_FLAGS_LI BIT_6 552252206Sdavidcs#define Q81_CQ_ICB_FLAGS_LL BIT_5 553252206Sdavidcs#define Q81_CQ_ICB_FLAGS_LS BIT_4 554252206Sdavidcs#define Q81_CQ_ICB_FLAGS_LV BIT_3 555252206Sdavidcs 556252206Sdavidcs uint16_t length_v; 557252206Sdavidcs#define Q81_CQ_ICB_VALID BIT_4 558252206Sdavidcs 559252206Sdavidcs uint16_t rsrvd1; 560252206Sdavidcs 561252206Sdavidcs uint32_t cq_baddr_lo; 562252206Sdavidcs uint32_t cq_baddr_hi; 563252206Sdavidcs 564252206Sdavidcs uint32_t cqi_addr_lo; 565252206Sdavidcs uint32_t cqi_addr_hi; 566252206Sdavidcs 567252206Sdavidcs uint16_t pkt_idelay; 568252206Sdavidcs uint16_t idelay; 569252206Sdavidcs 570252206Sdavidcs uint32_t lbq_baddr_lo; 571252206Sdavidcs uint32_t lbq_baddr_hi; 572252206Sdavidcs uint16_t lbq_bsize; 573252206Sdavidcs uint16_t lbq_length; 574252206Sdavidcs 575252206Sdavidcs uint32_t sbq_baddr_lo; 576252206Sdavidcs uint32_t sbq_baddr_hi; 577252206Sdavidcs uint16_t sbq_bsize; 578252206Sdavidcs uint16_t sbq_length; 579252206Sdavidcs} __packed q81_cq_icb_t; 580252206Sdavidcs 581252206Sdavidcs/* 582252206Sdavidcs * RSS Initialization Control Block 583252206Sdavidcs */ 584252206Sdavidcstypedef struct _q81_rss_icb { 585252206Sdavidcs uint16_t flags_base_cq_num; 586252206Sdavidcs#define Q81_RSS_ICB_FLAGS_L4K BIT_7 587252206Sdavidcs#define Q81_RSS_ICB_FLAGS_L6K BIT_8 588252206Sdavidcs#define Q81_RSS_ICB_FLAGS_LI BIT_9 589252206Sdavidcs#define Q81_RSS_ICB_FLAGS_LB BIT_10 590252206Sdavidcs#define Q81_RSS_ICB_FLAGS_LM BIT_11 591252206Sdavidcs#define Q81_RSS_ICB_FLAGS_RI4 BIT_12 592252206Sdavidcs#define Q81_RSS_ICB_FLAGS_RT4 BIT_13 593252206Sdavidcs#define Q81_RSS_ICB_FLAGS_RI6 BIT_14 594252206Sdavidcs#define Q81_RSS_ICB_FLAGS_RT6 BIT_15 595252206Sdavidcs 596252206Sdavidcs uint16_t mask; /* bits 9-0 are valid */ 597252206Sdavidcs 598252206Sdavidcs#define Q81_RSS_ICB_NUM_INDTBL_ENTRIES 1024 599252206Sdavidcs /* Indirection Table */ 600252206Sdavidcs uint8_t cq_id[Q81_RSS_ICB_NUM_INDTBL_ENTRIES]; 601252206Sdavidcs 602252206Sdavidcs /* Hash Keys */ 603252206Sdavidcs uint32_t ipv6_rss_hash_key[10]; 604252206Sdavidcs uint32_t ipv4_rss_hash_key[4]; 605252206Sdavidcs} __packed q81_rss_icb_t; 606252206Sdavidcs 607252206Sdavidcs 608252206Sdavidcs 609252206Sdavidcs/* 610252206Sdavidcs * Transmit Buffer Descriptor 611252206Sdavidcs */ 612252206Sdavidcs 613252206Sdavidcstypedef struct _q81_txb_desc { 614252206Sdavidcs uint64_t baddr; 615252206Sdavidcs uint16_t length; 616252206Sdavidcs 617252206Sdavidcs uint16_t flags; 618252206Sdavidcs#define Q81_TXB_DESC_FLAGS_E BIT_15 619252206Sdavidcs#define Q81_TXB_DESC_FLAGS_C BIT_14 620252206Sdavidcs 621252206Sdavidcs} __packed q81_txb_desc_t; 622252206Sdavidcs 623252206Sdavidcs 624252206Sdavidcs/* 625252206Sdavidcs * Receive Buffer Descriptor 626252206Sdavidcs */ 627252206Sdavidcs 628252206Sdavidcstypedef struct _q81_rxb_desc { 629252206Sdavidcs uint32_t baddr_lo; 630252206Sdavidcs#define Q81_RXB_DESC_BADDR_LO_S BIT_1 631252206Sdavidcs 632252206Sdavidcs uint64_t baddr; 633252206Sdavidcs 634252206Sdavidcs uint16_t length; 635252206Sdavidcs 636252206Sdavidcs uint16_t flags; 637252206Sdavidcs#define Q81_RXB_DESC_FLAGS_E BIT_15 638252206Sdavidcs#define Q81_RXB_DESC_FLAGS_C BIT_14 639252206Sdavidcs 640252206Sdavidcs} __packed q81_rxb_desc_t; 641252206Sdavidcs 642252206Sdavidcs/* 643252206Sdavidcs * IOCB Types 644252206Sdavidcs */ 645252206Sdavidcs 646252206Sdavidcs#define Q81_IOCB_TX_MAC 0x01 647252206Sdavidcs#define Q81_IOCB_TX_TSO 0x02 648252206Sdavidcs#define Q81_IOCB_RX 0x20 649252206Sdavidcs#define Q81_IOCB_MPI 0x21 650252206Sdavidcs#define Q81_IOCB_SYS 0x3F 651252206Sdavidcs 652252206Sdavidcs 653252206Sdavidcs/* 654252206Sdavidcs * IOCB Definitions 655252206Sdavidcs */ 656252206Sdavidcs 657252206Sdavidcs/* 658252206Sdavidcs * MAC Tx Frame IOCB 659252206Sdavidcs * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 660252206Sdavidcs */ 661252206Sdavidcs#define MAX_TX_MAC_DESC 8 662252206Sdavidcs 663252206Sdavidcstypedef struct _q81_tx_mac { 664252206Sdavidcs 665252206Sdavidcs uint8_t opcode; 666252206Sdavidcs 667252206Sdavidcs uint16_t flags; 668252206Sdavidcs#define Q81_TX_MAC_FLAGS_D BIT_3 669252206Sdavidcs#define Q81_TX_MAC_FLAGS_I BIT_1 670252206Sdavidcs#define Q81_TX_MAC_FLAGS_OI BIT_0 671252206Sdavidcs 672252206Sdavidcs uint8_t vlan_off; 673252206Sdavidcs#define Q81_TX_MAC_VLAN_OFF_SHIFT 3 674252206Sdavidcs#define Q81_TX_MAC_VLAN_OFF_V BIT_2 675252206Sdavidcs#define Q81_TX_MAC_VLAN_OFF_DFP BIT_1 676252206Sdavidcs 677252206Sdavidcs uint32_t rsrvd1; 678252206Sdavidcs uint32_t rsrvd2; 679252206Sdavidcs 680252206Sdavidcs uint16_t frame_length; /* only bits0-13 are valid */ 681252206Sdavidcs uint16_t rsrvd3; 682252206Sdavidcs 683252206Sdavidcs uint32_t tid_lo; 684252206Sdavidcs uint32_t tid_hi; 685252206Sdavidcs 686252206Sdavidcs uint32_t rsrvd4; 687252206Sdavidcs 688252206Sdavidcs uint16_t vlan_tci; 689252206Sdavidcs uint16_t rsrvd5; 690252206Sdavidcs 691252206Sdavidcs q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 692252206Sdavidcs} __packed q81_tx_mac_t; 693252206Sdavidcs 694252206Sdavidcs 695252206Sdavidcs/* 696252206Sdavidcs * MAC Tx Frame with TSO IOCB 697252206Sdavidcs * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 698252206Sdavidcs */ 699252206Sdavidcstypedef struct _q81_tx_tso { 700252206Sdavidcs uint8_t opcode; 701252206Sdavidcs 702252206Sdavidcs uint16_t flags; 703252206Sdavidcs#define Q81_TX_TSO_FLAGS_OI BIT_0 704252206Sdavidcs#define Q81_TX_TSO_FLAGS_I BIT_1 705252206Sdavidcs#define Q81_TX_TSO_FLAGS_D BIT_3 706252206Sdavidcs#define Q81_TX_TSO_FLAGS_IPV4 BIT_6 707252206Sdavidcs#define Q81_TX_TSO_FLAGS_IPV6 BIT_7 708252206Sdavidcs#define Q81_TX_TSO_FLAGS_LSO BIT_13 709252206Sdavidcs#define Q81_TX_TSO_FLAGS_UC BIT_14 710252206Sdavidcs#define Q81_TX_TSO_FLAGS_TC BIT_15 711252206Sdavidcs 712252206Sdavidcs uint8_t vlan_off; 713252206Sdavidcs#define Q81_TX_TSO_VLAN_OFF_SHIFT 3 714252206Sdavidcs#define Q81_TX_TSO_VLAN_OFF_V BIT_2 715252206Sdavidcs#define Q81_TX_TSO_VLAN_OFF_DFP BIT_1 716252206Sdavidcs#define Q81_TX_TSO_VLAN_OFF_IC BIT_0 717252206Sdavidcs 718252206Sdavidcs uint32_t rsrvd1; 719252206Sdavidcs uint32_t rsrvd2; 720252206Sdavidcs 721252206Sdavidcs uint32_t length; 722252206Sdavidcs uint32_t tid_lo; 723252206Sdavidcs uint32_t tid_hi; 724252206Sdavidcs 725252206Sdavidcs uint16_t phdr_length; 726252206Sdavidcs 727252206Sdavidcs uint16_t phdr_offsets; 728252206Sdavidcs#define Q81_TX_TSO_PHDR_SHIFT 6 729252206Sdavidcs 730252206Sdavidcs uint16_t vlan_tci; 731252206Sdavidcs uint16_t mss; 732252206Sdavidcs 733252206Sdavidcs q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 734252206Sdavidcs} __packed q81_tx_tso_t; 735252206Sdavidcs 736252206Sdavidcstypedef struct _q81_tx_cmd { 737252206Sdavidcs uint8_t bytes[128]; 738252206Sdavidcs} __packed q81_tx_cmd_t; 739252206Sdavidcs 740252206Sdavidcs/* 741252206Sdavidcs * MAC TX Frame Completion 742252206Sdavidcs * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 743252206Sdavidcs */ 744252206Sdavidcs 745252206Sdavidcstypedef struct _q81_tx_mac_comp { 746252206Sdavidcs uint8_t opcode; 747252206Sdavidcs 748252206Sdavidcs uint8_t flags; 749252206Sdavidcs#define Q81_TX_MAC_COMP_FLAGS_OI BIT_0 750252206Sdavidcs#define Q81_TX_MAC_COMP_FLAGS_I BIT_1 751252206Sdavidcs#define Q81_TX_MAC_COMP_FLAGS_E BIT_3 752252206Sdavidcs#define Q81_TX_MAC_COMP_FLAGS_S BIT_4 753252206Sdavidcs#define Q81_TX_MAC_COMP_FLAGS_L BIT_5 754252206Sdavidcs#define Q81_TX_MAC_COMP_FLAGS_P BIT_6 755252206Sdavidcs 756252206Sdavidcs uint8_t rsrvd0; 757252206Sdavidcs 758252206Sdavidcs uint8_t err; 759252206Sdavidcs#define Q81_TX_MAC_COMP_ERR_B BIT_7 760252206Sdavidcs 761252206Sdavidcs uint32_t tid_lo; 762252206Sdavidcs uint32_t tid_hi; 763252206Sdavidcs 764252206Sdavidcs uint32_t rsrvd1[13]; 765252206Sdavidcs} __packed q81_tx_mac_comp_t; 766252206Sdavidcs 767252206Sdavidcs 768252206Sdavidcs/* 769252206Sdavidcs * MAC TX Frame with LSO Completion 770252206Sdavidcs * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 771252206Sdavidcs */ 772252206Sdavidcs 773252206Sdavidcstypedef struct _q81_tx_tso_comp { 774252206Sdavidcs uint8_t opcode; 775252206Sdavidcs 776252206Sdavidcs uint8_t flags; 777252206Sdavidcs#define Q81_TX_TSO_COMP_FLAGS_OI BIT_0 778252206Sdavidcs#define Q81_TX_TSO_COMP_FLAGS_I BIT_1 779252206Sdavidcs#define Q81_TX_TSO_COMP_FLAGS_E BIT_3 780252206Sdavidcs#define Q81_TX_TSO_COMP_FLAGS_S BIT_4 781252206Sdavidcs#define Q81_TX_TSO_COMP_FLAGS_P BIT_6 782252206Sdavidcs 783252206Sdavidcs uint8_t rsrvd0; 784252206Sdavidcs 785252206Sdavidcs uint8_t err; 786252206Sdavidcs#define Q81_TX_TSO_COMP_ERR_B BIT_7 787252206Sdavidcs 788252206Sdavidcs uint32_t tid_lo; 789252206Sdavidcs uint32_t tid_hi; 790252206Sdavidcs 791252206Sdavidcs uint32_t rsrvd1[13]; 792252206Sdavidcs} __packed q81_tx_tso_comp_t; 793252206Sdavidcs 794252206Sdavidcs 795252206Sdavidcs/* 796252206Sdavidcs * SYS - Chip Event Notification Completion 797252206Sdavidcs * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 798252206Sdavidcs */ 799252206Sdavidcs 800252206Sdavidcstypedef struct _q81_sys_comp { 801252206Sdavidcs uint8_t opcode; 802252206Sdavidcs 803252206Sdavidcs uint8_t flags; 804252206Sdavidcs#define Q81_SYS_COMP_FLAGS_OI BIT_0 805252206Sdavidcs#define Q81_SYS_COMP_FLAGS_I BIT_1 806252206Sdavidcs 807252206Sdavidcs uint8_t etype; 808252206Sdavidcs#define Q81_SYS_COMPE_LINK_UP 0x00 809252206Sdavidcs#define Q81_SYS_COMPE_LINK_DOWN 0x01 810252206Sdavidcs#define Q81_SYS_COMPE_MULTI_CAM_LOOKUP 0x06 811252206Sdavidcs#define Q81_SYS_COMPE_SOFT_ECC 0x07 812252206Sdavidcs#define Q81_SYS_COMPE_MPI_FATAL_ERROR 0x08 813252206Sdavidcs#define Q81_SYS_COMPE_MAC_INTR 0x09 814252206Sdavidcs#define Q81_SYS_COMPE_GPI0_HTOL 0x10 815252206Sdavidcs#define Q81_SYS_COMPE_GPI0_LTOH 0x20 816252206Sdavidcs#define Q81_SYS_COMPE_GPI1_HTOL 0x11 817252206Sdavidcs#define Q81_SYS_COMPE_GPI1_LTOH 0x21 818252206Sdavidcs 819252206Sdavidcs uint8_t q_id; /* only bits 0-6 are valid */ 820252206Sdavidcs 821252206Sdavidcs uint32_t rsrvd1[15]; 822252206Sdavidcs} __packed q81_sys_comp_t; 823252206Sdavidcs 824252206Sdavidcs 825252206Sdavidcs 826252206Sdavidcs/* 827252206Sdavidcs * Mac Rx Packet Completion 828252206Sdavidcs * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 829252206Sdavidcs */ 830252206Sdavidcs 831252206Sdavidcstypedef struct _q81_rx { 832252206Sdavidcs uint8_t opcode; 833252206Sdavidcs 834252206Sdavidcs uint8_t flags0; 835252206Sdavidcs#define Q81_RX_FLAGS0_OI BIT_0 836252206Sdavidcs#define Q81_RX_FLAGS0_I BIT_1 837252206Sdavidcs#define Q81_RX_FLAGS0_TE BIT_2 838252206Sdavidcs#define Q81_RX_FLAGS0_NU BIT_3 839252206Sdavidcs#define Q81_RX_FLAGS0_IE BIT_4 840252206Sdavidcs 841252206Sdavidcs#define Q81_RX_FLAGS0_MCAST_MASK (0x03 << 5) 842252206Sdavidcs#define Q81_RX_FLAGS0_MCAST_NONE (0x00 << 5) 843252206Sdavidcs#define Q81_RX_FLAGS0_MCAST_HASH_MATCH (0x01 << 5) 844252206Sdavidcs#define Q81_RX_FLAGS0_MCAST_REG_MATCH (0x02 << 5) 845252206Sdavidcs#define Q81_RX_FLAGS0_MCAST_PROMISC (0x03 << 5) 846252206Sdavidcs 847252206Sdavidcs#define Q81_RX_FLAGS0_B BIT_7 848252206Sdavidcs 849252206Sdavidcs uint16_t flags1; 850252206Sdavidcs#define Q81_RX_FLAGS1_P BIT_0 851252206Sdavidcs#define Q81_RX_FLAGS1_V BIT_1 852252206Sdavidcs 853252206Sdavidcs#define Q81_RX_FLAGS1_ERR_NONE (0x00 << 2) 854252206Sdavidcs#define Q81_RX_FLAGS1_ERR_CODE (0x01 << 2) 855252206Sdavidcs#define Q81_RX_FLAGS1_ERR_OSIZE (0x02 << 2) 856252206Sdavidcs#define Q81_RX_FLAGS1_ERR_USIZE (0x04 << 2) 857252206Sdavidcs#define Q81_RX_FLAGS1_ERR_PREAMBLE (0x05 << 2) 858252206Sdavidcs#define Q81_RX_FLAGS1_ERR_FRAMELENGTH (0x06 << 2) 859252206Sdavidcs#define Q81_RX_FLAGS1_ERR_CRC (0x07 << 2) 860252206Sdavidcs#define Q81_RX_FLAGS1_ERR_MASK (0x07 << 2) 861252206Sdavidcs 862252206Sdavidcs#define Q81_RX_FLAGS1_U BIT_5 863252206Sdavidcs#define Q81_RX_FLAGS1_T BIT_6 864252206Sdavidcs#define Q81_RX_FLAGS1_FO BIT_7 865252206Sdavidcs#define Q81_RX_FLAGS1_RSS_NO_MATCH (0x00 << 8) 866252206Sdavidcs#define Q81_RX_FLAGS1_RSS_IPV4_MATCH (0x04 << 8) 867252206Sdavidcs#define Q81_RX_FLAGS1_RSS_IPV6_MATCH (0x02 << 8) 868252206Sdavidcs#define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 869252206Sdavidcs#define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 870252206Sdavidcs#define Q81_RX_FLAGS1_RSS_MATCH_MASK (0x07 << 8) 871252206Sdavidcs#define Q81_RX_FLAGS1_V4 BIT_11 872252206Sdavidcs#define Q81_RX_FLAGS1_V6 BIT_12 873252206Sdavidcs#define Q81_RX_FLAGS1_IH BIT_13 874252206Sdavidcs#define Q81_RX_FLAGS1_DS BIT_14 875252206Sdavidcs#define Q81_RX_FLAGS1_DL BIT_15 876252206Sdavidcs 877252206Sdavidcs uint32_t length; 878252206Sdavidcs uint64_t b_paddr; 879252206Sdavidcs 880252206Sdavidcs uint32_t rss; 881252206Sdavidcs uint16_t vlan_tag; 882252206Sdavidcs uint16_t rsrvd; 883252206Sdavidcs uint32_t rsrvd1; 884252206Sdavidcs uint32_t flags2; 885252206Sdavidcs#define Q81_RX_FLAGS2_HV BIT_13 886252206Sdavidcs#define Q81_RX_FLAGS2_HS BIT_14 887252206Sdavidcs#define Q81_RX_FLAGS2_HL BIT_15 888252206Sdavidcs 889252206Sdavidcs uint32_t hdr_length; 890252206Sdavidcs uint32_t hdr_baddr_lo; 891252206Sdavidcs uint32_t hdr_baddr_hi; 892252206Sdavidcs 893252206Sdavidcs} __packed q81_rx_t; 894252206Sdavidcs 895252206Sdavidcstypedef struct _q81_cq_e { 896252206Sdavidcs uint8_t opcode; 897252206Sdavidcs uint8_t bytes[63]; 898252206Sdavidcs} __packed q81_cq_e_t; 899252206Sdavidcs 900252206Sdavidcstypedef struct _q81_bq_addr_e { 901252206Sdavidcs uint32_t addr_lo; 902252206Sdavidcs uint32_t addr_hi; 903252206Sdavidcs} __packed q81_bq_addr_e_t; 904252206Sdavidcs 905252206Sdavidcs 906252206Sdavidcs/* 907252206Sdavidcs * Macros for reading and writing registers 908252206Sdavidcs */ 909252206Sdavidcs 910252206Sdavidcs#if defined(__i386__) || defined(__amd64__) 911252206Sdavidcs#define Q8_MB() __asm volatile("mfence" ::: "memory") 912252206Sdavidcs#define Q8_WMB() __asm volatile("sfence" ::: "memory") 913252206Sdavidcs#define Q8_RMB() __asm volatile("lfence" ::: "memory") 914252206Sdavidcs#else 915252206Sdavidcs#define Q8_MB() 916252206Sdavidcs#define Q8_WMB() 917252206Sdavidcs#define Q8_RMB() 918252206Sdavidcs#endif 919252206Sdavidcs 920252206Sdavidcs#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 921252206Sdavidcs#define READ_REG64(ha, reg) bus_read_8((ha->pci_reg), reg) 922252206Sdavidcs 923252206Sdavidcs#define WRITE_REG32_ONLY(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 924252206Sdavidcs 925252206Sdavidcs#define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 926252206Sdavidcs 927252206Sdavidcs#define Q81_CTL_INTRE_MASK_VALUE \ 928252206Sdavidcs (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 929252206Sdavidcs Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_ENABLE) 930252206Sdavidcs 931252206Sdavidcs#define Q81_ENABLE_INTR(ha, idx) \ 932252206Sdavidcs WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx)) 933252206Sdavidcs 934252206Sdavidcs#define Q81_CTL_INTRD_MASK_VALUE \ 935252206Sdavidcs (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 936252206Sdavidcs Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_DISABLE) 937252206Sdavidcs 938252206Sdavidcs#define Q81_DISABLE_INTR(ha, idx) \ 939252206Sdavidcs WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx)) 940252206Sdavidcs 941252206Sdavidcs#define Q81_WR_WQ_PROD_IDX(wq_idx, idx) bus_write_4((ha->pci_reg1),\ 942252206Sdavidcs (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG), idx) 943252206Sdavidcs 944252206Sdavidcs#define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\ 945252206Sdavidcs (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG)) 946252206Sdavidcs 947252206Sdavidcs 948252206Sdavidcs#define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\ 949252206Sdavidcs (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 950252206Sdavidcs Q81_COMPQ_VALID_V) 951252206Sdavidcs 952252206Sdavidcs#define Q81_SET_WQ_INVALID(wq_idx) bus_write_4((ha->pci_reg1),\ 953252206Sdavidcs (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 954252206Sdavidcs (~Q81_COMPQ_VALID_V)) 955252206Sdavidcs 956252206Sdavidcs#define Q81_WR_CQ_CONS_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 957252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG), idx) 958252206Sdavidcs 959252206Sdavidcs#define Q81_RD_CQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 960252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG)) 961252206Sdavidcs 962252206Sdavidcs#define Q81_SET_CQ_VALID(cq_idx) bus_write_4((ha->pci_reg1),\ 963252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 964252206Sdavidcs Q81_COMPQ_VALID_V) 965252206Sdavidcs 966252206Sdavidcs#define Q81_SET_CQ_INVALID(cq_idx) bus_write_4((ha->pci_reg1),\ 967252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 968252206Sdavidcs ~Q81_COMPQ_VALID_V) 969252206Sdavidcs 970252206Sdavidcs#define Q81_WR_LBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 971252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG), idx) 972252206Sdavidcs 973252206Sdavidcs#define Q81_RD_LBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 974252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG)) 975252206Sdavidcs 976252206Sdavidcs#define Q81_WR_SBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 977252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG), idx) 978252206Sdavidcs 979252206Sdavidcs#define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 980252206Sdavidcs (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG)) 981252206Sdavidcs 982252206Sdavidcs 983252206Sdavidcs/* 984252206Sdavidcs * Flash Related 985252206Sdavidcs */ 986252206Sdavidcs 987252206Sdavidcs#define Q81_F0_FLASH_OFFSET 0x140200 988252206Sdavidcs#define Q81_F1_FLASH_OFFSET 0x140600 989252206Sdavidcs#define Q81_FLASH_ID "8000" 990252206Sdavidcs 991252206Sdavidcstypedef struct _q81_flash { 992252206Sdavidcs 993252206Sdavidcs uint8_t id[4]; /* equal to "8000" */ 994252206Sdavidcs 995252206Sdavidcs uint16_t version; 996252206Sdavidcs uint16_t size; 997252206Sdavidcs uint16_t csum; 998252206Sdavidcs uint16_t rsrvd0; 999252206Sdavidcs uint16_t total_size; 1000252206Sdavidcs uint16_t nentries; 1001252206Sdavidcs 1002252206Sdavidcs uint8_t dtype0; 1003252206Sdavidcs uint8_t dsize0; 1004252206Sdavidcs uint8_t mac_addr0[6]; 1005252206Sdavidcs 1006252206Sdavidcs uint8_t dtype1; 1007252206Sdavidcs uint8_t dsize1; 1008252206Sdavidcs uint8_t mac_addr1[6]; 1009252206Sdavidcs 1010252206Sdavidcs uint8_t dtype2; 1011252206Sdavidcs uint8_t dsize2; 1012252206Sdavidcs uint16_t vlan_id; 1013252206Sdavidcs 1014252206Sdavidcs uint8_t dtype3; 1015252206Sdavidcs uint8_t dsize3; 1016252206Sdavidcs uint16_t last; 1017252206Sdavidcs 1018252206Sdavidcs uint8_t rsrvd1[464]; 1019252206Sdavidcs 1020252206Sdavidcs uint16_t subsys_vid; 1021252206Sdavidcs uint16_t subsys_did; 1022252206Sdavidcs 1023252206Sdavidcs uint8_t rsrvd2[4]; 1024252206Sdavidcs} __packed q81_flash_t; 1025252206Sdavidcs 1026252206Sdavidcs 1027252206Sdavidcs/* 1028252206Sdavidcs * MPI Related 1029252206Sdavidcs */ 1030252206Sdavidcs 1031252206Sdavidcs#define Q81_NUM_MBX_REGISTERS 16 1032252206Sdavidcs#define Q81_NUM_AEN_REGISTERS 9 1033252206Sdavidcs 1034252206Sdavidcs#define Q81_FUNC0_MBX_IN_REG0 0x1180 1035252206Sdavidcs#define Q81_FUNC0_MBX_OUT_REG0 0x1190 1036252206Sdavidcs 1037252206Sdavidcs#define Q81_FUNC1_MBX_IN_REG0 0x1280 1038252206Sdavidcs#define Q81_FUNC1_MBX_OUT_REG0 0x1290 1039252206Sdavidcs 1040252206Sdavidcs#define Q81_MBX_NOP 0x0000 1041252206Sdavidcs#define Q81_MBX_EXEC_FW 0x0002 1042252206Sdavidcs#define Q81_MBX_REG_TEST 0x0006 1043252206Sdavidcs#define Q81_MBX_VERIFY_CHKSUM 0x0007 1044252206Sdavidcs#define Q81_MBX_ABOUT_FW 0x0008 1045252206Sdavidcs#define Q81_MBX_RISC_MEMCPY 0x000A 1046252206Sdavidcs#define Q81_MBX_LOAD_RISC_RAM 0x000B 1047252206Sdavidcs#define Q81_MBX_DUMP_RISC_RAM 0x000C 1048252206Sdavidcs#define Q81_MBX_WR_RAM_WORD 0x000D 1049252206Sdavidcs#define Q81_MBX_INIT_RISC_RAM 0x000E 1050252206Sdavidcs#define Q81_MBX_RD_RAM_WORD 0x000F 1051252206Sdavidcs#define Q81_MBX_STOP_FW 0x0014 1052252206Sdavidcs#define Q81_MBX_GEN_SYS_ERR 0x002A 1053252206Sdavidcs#define Q81_MBX_WR_SFP_PLUS 0x0030 1054252206Sdavidcs#define Q81_MBX_RD_SFP_PLUS 0x0031 1055252206Sdavidcs#define Q81_MBX_INIT_FW 0x0060 1056252206Sdavidcs#define Q81_MBX_GET_IFCB 0x0061 1057252206Sdavidcs#define Q81_MBX_GET_FW_STATE 0x0069 1058252206Sdavidcs#define Q81_MBX_IDC_REQ 0x0100 1059252206Sdavidcs#define Q81_MBX_IDC_ACK 0x0101 1060252206Sdavidcs#define Q81_MBX_IDC_TIME_EXTEND 0x0102 1061252206Sdavidcs#define Q81_MBX_WOL_MODE 0x0110 1062252206Sdavidcs#define Q81_MBX_SET_WOL_FILTER 0x0111 1063252206Sdavidcs#define Q81_MBX_CLR_WOL_FILTER 0x0112 1064252206Sdavidcs#define Q81_MBX_SET_WOL_MAGIC 0x0113 1065252206Sdavidcs#define Q81_MBX_WOL_MODE_IMM 0x0115 1066252206Sdavidcs#define Q81_MBX_PORT_RESET 0x0120 1067252206Sdavidcs#define Q81_MBX_SET_PORT_CFG 0x0122 1068252206Sdavidcs#define Q81_MBX_GET_PORT_CFG 0x0123 1069252206Sdavidcs#define Q81_MBX_GET_LNK_STATUS 0x0124 1070252206Sdavidcs#define Q81_MBX_SET_LED_CFG 0x0125 1071252206Sdavidcs#define Q81_MBX_GET_LED_CFG 0x0126 1072252206Sdavidcs#define Q81_MBX_SET_DCBX_CTLB 0x0130 1073252206Sdavidcs#define Q81_MBX_GET_DCBX_CTLB 0x0131 1074252206Sdavidcs#define Q81_MBX_GET_DCBX_TLV 0x0132 1075252206Sdavidcs#define Q81_MBX_DIAG_CMDS 0x0150 1076252206Sdavidcs#define Q81_MBX_SET_MGMT_CTL 0x0160 1077252206Sdavidcs#define Q81_MBX_SET_MGMT_CTL_STOP 0x01 1078252206Sdavidcs#define Q81_MBX_SET_MGMT_CTL_RESUME 0x02 1079252206Sdavidcs#define Q81_MBX_GET_MGMT_CTL 0x0161 1080252206Sdavidcs#define Q81_MBX_GET_MGMT_CTL_MASK ~0x3 1081252206Sdavidcs#define Q81_MBX_GET_MGMT_CTL_FIFO_EMPTY 0x02 1082252206Sdavidcs#define Q81_MBX_GET_MGMT_CTL_SET_MGMT 0x01 1083252206Sdavidcs 1084252206Sdavidcs#define Q81_MBX_CMD_COMPLETE 0x4000 1085252206Sdavidcs#define Q81_MBX_CMD_INVALID 0x4001 1086252206Sdavidcs#define Q81_MBX_CMD_TEST_FAILED 0x4003 1087252206Sdavidcs#define Q81_MBX_CMD_ERROR 0x4005 1088252206Sdavidcs#define Q81_MBX_CMD_PARAM_ERROR 0x4006 1089252206Sdavidcs 1090252206Sdavidcs#endif /* #ifndef _QLS_HW_H_ */ 1091