1/* 2 * Copyright (c) 2013-2014 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29/* 30 * File: qls_hw.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33#ifndef _QLS_HW_H_ 34#define _QLS_HW_H_ 35 36#define Q8_MAX_NUM_MULTICAST_ADDRS 32 37#define Q8_MAC_ADDR_LEN 6 38 39#define BIT_0 (0x1 << 0) 40#define BIT_1 (0x1 << 1) 41#define BIT_2 (0x1 << 2) 42#define BIT_3 (0x1 << 3) 43#define BIT_4 (0x1 << 4) 44#define BIT_5 (0x1 << 5) 45#define BIT_6 (0x1 << 6) 46#define BIT_7 (0x1 << 7) 47#define BIT_8 (0x1 << 8) 48#define BIT_9 (0x1 << 9) 49#define BIT_10 (0x1 << 10) 50#define BIT_11 (0x1 << 11) 51#define BIT_12 (0x1 << 12) 52#define BIT_13 (0x1 << 13) 53#define BIT_14 (0x1 << 14) 54#define BIT_15 (0x1 << 15) 55#define BIT_16 (0x1 << 16) 56#define BIT_17 (0x1 << 17) 57#define BIT_18 (0x1 << 18) 58#define BIT_19 (0x1 << 19) 59#define BIT_20 (0x1 << 20) 60#define BIT_21 (0x1 << 21) 61#define BIT_22 (0x1 << 22) 62#define BIT_23 (0x1 << 23) 63#define BIT_24 (0x1 << 24) 64#define BIT_25 (0x1 << 25) 65#define BIT_11 (0x1 << 11) 66#define BIT_12 (0x1 << 12) 67#define BIT_13 (0x1 << 13) 68#define BIT_14 (0x1 << 14) 69#define BIT_15 (0x1 << 15) 70#define BIT_16 (0x1 << 16) 71#define BIT_17 (0x1 << 17) 72#define BIT_18 (0x1 << 18) 73#define BIT_19 (0x1 << 19) 74#define BIT_20 (0x1 << 20) 75#define BIT_21 (0x1 << 21) 76#define BIT_22 (0x1 << 22) 77#define BIT_23 (0x1 << 23) 78#define BIT_24 (0x1 << 24) 79#define BIT_25 (0x1 << 25) 80#define BIT_26 (0x1 << 26) 81#define BIT_27 (0x1 << 27) 82#define BIT_28 (0x1 << 28) 83#define BIT_29 (0x1 << 29) 84#define BIT_30 (0x1 << 30) 85#define BIT_31 (0x1 << 31) 86 87 88/* 89 * Firmware Interface 90 */ 91 92/********************************************************************* 93 * Work Queue Register Map 94 *********************************************************************/ 95#define Q81_WRKQ_INDEX_REG 0x00 96#define Q81_WRKQ_CONS_INDEX_MASK 0xFFFF0000 97#define Q81_WRKQ_PROD_INDEX_MASK 0x0000FFFF 98#define Q81_WRKQ_VALID_REG 0x04 99#define Q81_WRKQ_VALID_ONQ BIT_25 100#define Q81_WRKQ_VALID_V BIT_4 101 102/********************************************************************* 103 * Completion Queue Register Map 104 *********************************************************************/ 105#define Q81_COMPQ_INDEX_REG 0x00 106#define Q81_COMPQ_PROD_INDEX_MASK 0xFFFF0000 107#define Q81_COMPQ_CONS_INDEX_MASK 0x0000FFFF 108#define Q81_COMPQ_VALID_REG 0x04 109#define Q81_COMPQ_VALID_V BIT_4 110#define Q81_LRGBQ_INDEX_REG 0x18 111#define Q81_LRGBQ_CONS_INDEX_MASK 0xFFFF0000 112#define Q81_LRGBQ_PROD_INDEX_MASK 0x0000FFFF 113#define Q81_SMBQ_INDEX_REG 0x1C 114#define Q81_SMBQ_CONS_INDEX_MASK 0xFFFF0000 115#define Q81_SMBQ_PROD_INDEX_MASK 0x0000FFFF 116 117/********************************************************************* 118 * Control Register Definitions 119 * (Access, Function Specific, Shared via Semaphore, Control by MPI FW) 120 *********************************************************************/ 121#define Q81_CTL_PROC_ADDR 0x00 /* R/W - Y - */ 122#define Q81_CTL_PROC_DATA 0x04 /* R/W - Y - */ 123#define Q81_CTL_SYSTEM 0x08 /* MWR - - - */ 124#define Q81_CTL_RESET 0x0C /* MWR Y - - */ 125#define Q81_CTL_FUNC_SPECIFIC 0x10 /* MWR Y - - */ 126#define Q81_CTL_HOST_CMD_STATUS 0x14 /* R/W Y - - */ 127#define Q81_CTL_LED 0x18 /* R/W Y - Y */ 128#define Q81_CTL_ICB_ACCESS_ADDR_LO 0x20 /* R/W - Y - */ 129#define Q81_CTL_ICB_ACCESS_ADDR_HI 0x24 /* R/W - Y - */ 130#define Q81_CTL_CONFIG 0x28 /* MWR - - - */ 131#define Q81_CTL_STATUS 0x30 /* MWR Y - - */ 132#define Q81_CTL_INTR_ENABLE 0x34 /* MWR Y - - */ 133#define Q81_CTL_INTR_MASK 0x38 /* MWR Y - - */ 134#define Q81_CTL_INTR_STATUS1 0x3C /* RO Y - - */ 135#define Q81_CTL_INTR_STATUS2 0x40 /* RO Y - - */ 136#define Q81_CTL_INTR_STATUS3 0x44 /* RO Y - - */ 137#define Q81_CTL_INTR_STATUS4 0x48 /* RO Y - - */ 138#define Q81_CTL_REV_ID 0x4C /* RO - - - */ 139#define Q81_CTL_FATAL_ERR_STATUS 0x54 /* RO Y - - */ 140#define Q81_CTL_COR_ECC_ERR_COUNTER 0x60 /* RO Y - - */ 141#define Q81_CTL_SEMAPHORE 0x64 /* MWR Y - - */ 142#define Q81_CTL_GPIO1 0x68 /* MWR Y - - */ 143#define Q81_CTL_GPIO2 0x6C /* MWR Y - - */ 144#define Q81_CTL_GPIO3 0x70 /* MWR Y - - */ 145#define Q81_CTL_XGMAC_ADDR 0x78 /* R/W Y Y - */ 146#define Q81_CTL_XGMAC_DATA 0x7C /* R/W Y Y Y */ 147#define Q81_CTL_NIC_ENH_TX_SCHD 0x80 /* R/W Y - Y */ 148#define Q81_CTL_CNA_ENH_TX_SCHD 0x84 /* R/W Y - Y */ 149#define Q81_CTL_FLASH_ADDR 0x88 /* R/W - Y - */ 150#define Q81_CTL_FLASH_DATA 0x8C /* R/W - Y - */ 151#define Q81_CTL_STOP_CQ_PROCESSING 0x90 /* MWR Y - - */ 152#define Q81_CTL_MAC_PROTO_ADDR_INDEX 0xA8 /* R/W - Y - */ 153#define Q81_CTL_MAC_PROTO_ADDR_DATA 0xAC /* R/W - Y - */ 154#define Q81_CTL_COS_DEF_CQ1 0xB0 /* R/W Y - - */ 155#define Q81_CTL_COS_DEF_CQ2 0xB4 /* R/W Y - - */ 156#define Q81_CTL_ETHERTYPE_SKIP_1 0xB8 /* R/W Y - - */ 157#define Q81_CTL_ETHERTYPE_SKIP_2 0xBC /* R/W Y - - */ 158#define Q81_CTL_SPLIT_HDR 0xC0 /* R/W Y - - */ 159#define Q81_CTL_NIC_PAUSE_THRES 0xC8 /* R/W Y - Y */ 160#define Q81_CTL_NIC_RCV_CONFIG 0xD4 /* MWR Y - Y */ 161#define Q81_CTL_COS_TAGS_IN_NIC_FIFO 0xDC /* R/W Y - Y */ 162#define Q81_CTL_MGMT_RCV_CONFIG 0xE0 /* MWR Y - Y */ 163#define Q81_CTL_ROUTING_INDEX 0xE4 /* R/W Y Y - */ 164#define Q81_CTL_ROUTING_DATA 0xE8 /* R/W Y Y - */ 165#define Q81_CTL_XG_SERDES_ADDR 0xF0 /* R/W Y Y Y */ 166#define Q81_CTL_XG_SERDES_DATA 0xF4 /* R/W Y Y Y */ 167#define Q81_CTL_XG_PROBE_MUX_ADDR 0xF8 /* R/W - Y - */ 168#define Q81_CTL_XG_PROBE_MUX_DATA 0xFC /* R/W - Y - */ 169 170 171/* 172 * Process Address Register (0x00) 173 */ 174#define Q81_CTL_PROC_ADDR_RDY BIT_31 175#define Q81_CTL_PROC_ADDR_READ BIT_30 176#define Q81_CTL_PROC_ADDR_ERR BIT_29 177#define Q81_CTL_PROC_ADDR_MPI_RISC (0x00 << 16) 178#define Q81_CTL_PROC_ADDR_MDE (0x01 << 16) 179#define Q81_CTL_PROC_ADDR_REG_BLOCK (0x02 << 16) 180#define Q81_CTL_PROC_ADDR_RISC_INT_REG (0x03 << 16) 181 182 183/* 184 * System Register (0x08) 185 */ 186#define Q81_CTL_SYSTEM_MASK_SHIFT 16 187#define Q81_CTL_SYSTEM_ENABLE_VQM_WR BIT_5 188#define Q81_CTL_SYSTEM_ENABLE_DWC BIT_4 189#define Q81_CTL_SYSTEM_ENABLE_DA_SINGLE_THRD BIT_3 190#define Q81_CTL_SYSTEM_ENABLE_MDC BIT_2 191#define Q81_CTL_SYSTEM_ENABLE_FAE BIT_1 192#define Q81_CTL_SYSTEM_ENABLE_EFE BIT_0 193 194/* 195 * Reset Register (0x0C) 196 */ 197#define Q81_CTL_RESET_MASK_SHIFT 16 198#define Q81_CTL_RESET_FUNC BIT_15 199#define Q81_CTL_RESET_RR_SHIFT 1 200 201/* 202 * Function Specific Control Register (0x10) 203 */ 204#define Q81_CTL_FUNC_SPECIFIC_MASK_SHIFT 16 205 206#define Q81_CTL_FUNC_SPECIFIC_FE BIT_15 207#define Q81_CTL_FUNC_SPECIFIC_STE BIT_13 208#define Q81_CTL_FUNC_SPECIFIC_DSB BIT_12 209#define Q81_CTL_FUNC_SPECIFIC_SH BIT_11 210 211#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_MASK (0x7 << 8) 212#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_2K (0x1 << 8) 213#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_4K (0x2 << 8) 214#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_8K (0x3 << 8) 215#define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_64K (0x6 << 8) 216 217#define Q81_CTL_FUNC_SPECIFIC_EPC_O BIT_7 218#define Q81_CTL_FUNC_SPECIFIC_EPC_I BIT_6 219#define Q81_CTL_FUNC_SPECIFIC_EC BIT_5 220#define Q81_CTL_FUNC_SPECIFIC_DBL_DBRST (0x00 << 3) 221#define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_PAYLDSZ (0x01 << 3) 222#define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_RDBRSTSZ (0x02 << 3) 223#define Q81_CTL_FUNC_SPECIFIC_DBL_128 (0x03 << 3) 224#define Q81_CTL_FUNC_SPECIFIC_DBRST_256 0x00 225#define Q81_CTL_FUNC_SPECIFIC_DBRST_512 0x01 226#define Q81_CTL_FUNC_SPECIFIC_DBRST_768 0x02 227#define Q81_CTL_FUNC_SPECIFIC_DBRST_1024 0x03 228 229 230/* 231 * Host Command/Status Register (0x14) 232 */ 233#define Q81_CTL_HCS_CMD_NOP (0x00 << 28) 234#define Q81_CTL_HCS_CMD_SET_RISC_RESET (0x01 << 28) 235#define Q81_CTL_HCS_CMD_CLR_RISC_RESET (0x02 << 28) 236#define Q81_CTL_HCS_CMD_SET_RISC_PAUSE (0x03 << 28) 237#define Q81_CTL_HCS_CMD_CLR_RISC_PAUSE (0x04 << 28) 238#define Q81_CTL_HCS_CMD_SET_HTR_INTR (0x05 << 28) 239#define Q81_CTL_HCS_CMD_CLR_HTR_INTR (0x06 << 28) 240#define Q81_CTL_HCS_CMD_SET_PARITY_EN (0x07 << 28) 241#define Q81_CTL_HCS_CMD_FORCE_BAD_PARITY (0x08 << 28) 242#define Q81_CTL_HCS_CMD_CLR_BAD_PARITY (0x09 << 28) 243#define Q81_CTL_HCS_CMD_CLR_RTH_INTR (0x0A << 28) 244 245#define Q81_CTL_HCS_CMD_PAR_SHIFT 22 246#define Q81_CTL_HCS_RISC_PAUSED BIT_10 247#define Q81_CTL_HCS_HTR_INTR BIT_9 248#define Q81_CTL_HCS_RISC_RESET BIT_8 249#define Q81_CTL_HCS_ERR_STATUS_MASK 0x3F 250 251 252/* 253 * Configuration Register (0x28) 254 */ 255#define Q81_CTL_CONFIG_MASK_SHIFT 16 256#define Q81_CTL_CONFIG_Q_NUM_SHIFT 8 257#define Q81_CTL_CONFIG_Q_NUM_MASK (0x7F << Q81_CTL_CONFIG_Q_NUM_SHIFT) 258#define Q81_CTL_CONFIG_DCQ BIT_7 259#define Q81_CTL_CONFIG_LCQ BIT_6 260#define Q81_CTL_CONFIG_LE BIT_5 261#define Q81_CTL_CONFIG_DR BIT_3 262#define Q81_CTL_CONFIG_LR BIT_2 263#define Q81_CTL_CONFIG_DRQ BIT_1 264#define Q81_CTL_CONFIG_LRQ BIT_0 265 266 267/* 268 * Status Register (0x30) 269 */ 270#define Q81_CTL_STATUS_MASK_SHIFT 16 271#define Q81_CTL_STATUS_NFE BIT_12 272#define Q81_CTL_STATUS_F3E BIT_11 273#define Q81_CTL_STATUS_F2E BIT_10 274#define Q81_CTL_STATUS_F1E BIT_9 275#define Q81_CTL_STATUS_F0E BIT_8 276#define Q81_CTL_STATUS_FUNC_SHIFT 6 277#define Q81_CTL_STATUS_PI1 BIT_5 278#define Q81_CTL_STATUS_PI0 BIT_4 279#define Q81_CTL_STATUS_PL1 BIT_3 280#define Q81_CTL_STATUS_PL0 BIT_2 281#define Q81_CTL_STATUS_PI BIT_1 282#define Q81_CTL_STATUS_FE BIT_0 283 284/* 285 * Interrupt Enable Register (0x34) 286 */ 287#define Q81_CTL_INTRE_MASK_SHIFT 16 288#define Q81_CTL_INTRE_EN BIT_15 289#define Q81_CTL_INTRE_EI BIT_14 290#define Q81_CTL_INTRE_IHD BIT_13 291#define Q81_CTL_INTRE_RTYPE_MASK (0x3 << 8) 292#define Q81_CTL_INTRE_RTYPE_ENABLE (0x1 << 8) 293#define Q81_CTL_INTRE_RTYPE_DISABLE (0x2 << 8) 294#define Q81_CTL_INTRE_RTYPE_SETUP_TO_RD (0x3 << 8) 295#define Q81_CTL_INTRE_HOST_INTR_MASK 0x7F 296 297/* 298 * Interrupt Mask Register (0x38) 299 */ 300#define Q81_CTL_INTRM_MASK_SHIFT 16 301#define Q81_CTL_INTRM_MC BIT_7 302#define Q81_CTL_INTRM_LSC BIT_6 303#define Q81_CTL_INTRM_LH1 BIT_4 304#define Q81_CTL_INTRM_HL1 BIT_3 305#define Q81_CTL_INTRM_LH0 BIT_2 306#define Q81_CTL_INTRM_HL0 BIT_1 307#define Q81_CTL_INTRM_PI BIT_0 308 309/* 310 * Interrupt Status 1 Register (0x3C) 311 */ 312#define Q81_CTL_INTRS1_COMPQ(i) (0x1 << i) 313 314/* 315 * Interrupt Status 2 Register (0x40) 316 */ 317#define Q81_CTL_INTRS2_COMPQ(i) (0x1 << i) 318 319/* 320 * Interrupt Status 3 Register (0x44) 321 */ 322#define Q81_CTL_INTRS3_COMPQ(i) (0x1 << i) 323 324/* 325 * Interrupt Status 4 Register (0x48) 326 */ 327#define Q81_CTL_INTRS4_COMPQ(i) (0x1 << i) 328 329/* 330 * Revision ID Register (0x4C) 331 */ 332#define Q81_CTL_REV_ID_CHIP_REV_MASK (0xF << 28) 333#define Q81_CTL_REV_ID_XGMAC_RCV_MASK (0xF << 16) 334#define Q81_CTL_REV_ID_XGMAC_ROLL_MASK (0xF << 8) 335#define Q81_CTL_REV_ID_NIC_REV_MASK (0xF << 4) 336#define Q81_CTL_REV_ID_NIC_ROLL_MASK (0xF << 0) 337 338/* 339 * Semaphore Register (0x64) 340 */ 341 342#define Q81_CTL_SEM_MASK_PROC_ADDR_NIC_RCV 0xC0000000 343 344#define Q81_CTL_SEM_MASK_RIDX_DATAREG 0x30000000 345 346#define Q81_CTL_SEM_MASK_FLASH 0x03000000 347 348#define Q81_CTL_SEM_MASK_MAC_SERDES 0x00C00000 349 350#define Q81_CTL_SEM_MASK_ICB 0x00300000 351 352#define Q81_CTL_SEM_MASK_XGMAC1 0x000C0000 353 354#define Q81_CTL_SEM_MASK_XGMAC0 0x00030000 355 356#define Q81_CTL_SEM_SET_PROC_ADDR_NIC_RCV 0x4000 357#define Q81_CTL_SEM_SET_RIDX_DATAREG 0x1000 358#define Q81_CTL_SEM_SET_FLASH 0x0100 359#define Q81_CTL_SEM_SET_MAC_SERDES 0x0040 360#define Q81_CTL_SEM_SET_ICB 0x0010 361#define Q81_CTL_SEM_SET_XGMAC1 0x0004 362#define Q81_CTL_SEM_SET_XGMAC0 0x0001 363 364 365/* 366 * Flash Address Register (0x88) 367 */ 368#define Q81_CTL_FLASH_ADDR_RDY BIT_31 369#define Q81_CTL_FLASH_ADDR_R BIT_30 370#define Q81_CTL_FLASH_ADDR_ERR BIT_29 371#define Q81_CTL_FLASH_ADDR_MASK 0x7FFFFF 372 373/* 374 * Stop CQ Processing Register (0x90) 375 */ 376#define Q81_CTL_STOP_CQ_MASK_SHIFT 16 377#define Q81_CTL_STOP_CQ_EN BIT_15 378#define Q81_CTL_STOP_CQ_RQ_STARTQ (0x1 << 8) 379#define Q81_CTL_STOP_CQ_RQ_STOPQ (0x2 << 8) 380#define Q81_CTL_STOP_CQ_RQ_READ (0x3 << 8) 381#define Q81_CTL_STOP_CQ_MASK 0x7F 382 383/* 384 * MAC Protocol Address Index Register (0xA8) 385 */ 386#define Q81_CTL_MAC_PROTO_AI_MW BIT_31 387#define Q81_CTL_MAC_PROTO_AI_MR BIT_30 388#define Q81_CTL_MAC_PROTO_AI_E BIT_27 389#define Q81_CTL_MAC_PROTO_AI_RS BIT_26 390#define Q81_CTL_MAC_PROTO_AI_ADR BIT_25 391#define Q81_CTL_MAC_PROTO_AI_TYPE_SHIFT 16 392#define Q81_CTL_MAC_PROTO_AI_TYPE_MASK 0xF0000 393#define Q81_CTL_MAC_PROTO_AI_IDX_SHIFT 4 394#define Q81_CTL_MAC_PROTO_AI_IDX_MASK 0xFFF0 395#define Q81_CTL_MAC_PROTO_AI_OFF_MASK 0xF 396 397#define Q81_CTL_MAC_PROTO_AI_TYPE_CAM_MAC (0 << 16) 398#define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST (1 << 16) 399#define Q81_CTL_MAC_PROTO_AI_TYPE_VLAN (2 << 16) 400#define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST_FILTER (3 << 16) 401#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_MAC (5 << 16) 402#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMMT_VLAN (6 << 16) 403#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV4 (7 << 16) 404#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV6 (8 << 16) 405#define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_PORT (9 << 16) /* TCP/UDP Port */ 406 407/* 408 * CAM MAC offset 2 definitions 409 */ 410#define Q81_CAM_MAC_OFF2_ROUTE_FC 0x00000000 411#define Q81_CAM_MAC_OFF2_ROUTE_NIC 0x00000001 412#define Q81_CAM_MAC_OFF2_FUNC_SHIFT 2 413#define Q81_CAM_MAC_OFF2_RV 0x00000010 414#define Q81_CAM_MAC_OFF2_CQID_SHIFT 5 415#define Q81_CAM_MAC_OFF2_SH 0x00008000 416#define Q81_CAM_MAC_OFF2_MHT 0x40000000 417#define Q81_CAM_MAC_OFF2_VLD 0x80000000 418 419/* 420 * NIC Pause Threshold Register (0xC8) 421 */ 422#define Q81_CTL_NIC_PAUSE_THRES_PAUSE_SHIFT 16 423#define Q81_CTL_NIC_PAUSE_THRES_RESUME_SHIFT 0 424 425/* 426 * NIC Receive Configuration Register (0xD4) 427 */ 428#define Q81_CTL_NIC_RCVC_MASK_SHIFT 16 429#define Q81_CTL_NIC_RCVC_DCQ_SHIFT 8 430#define Q81_CTL_NIC_RCVC_DCQ_MASK 0x7F00 431#define Q81_CTL_NIC_RCVC_DTP BIT_5 432#define Q81_CTL_NIC_RCVC_R4T BIT_4 433#define Q81_CTL_NIC_RCVC_RV BIT_3 434#define Q81_CTL_NIC_RCVC_VLAN_ALL (0x0 << 1) 435#define Q81_CTL_NIC_RCVC_VLAN_ONLY (0x1 << 1) 436#define Q81_CTL_NIC_RCVC_VLAN_NON_VLAN (0x2 << 1) 437#define Q81_CTL_NIC_RCVC_VLAN_REJECT (0x3 << 1) 438#define Q81_CTL_NIC_RCVC_PPE BIT_0 439 440 441/* 442 * Routing Index Register (0xE4) 443 */ 444#define Q81_CTL_RI_MW BIT_31 445#define Q81_CTL_RI_MR BIT_30 446#define Q81_CTL_RI_E BIT_27 447#define Q81_CTL_RI_RS BIT_26 448 449#define Q81_CTL_RI_DST_RSS (0x00 << 20) 450#define Q81_CTL_RI_DST_CAMQ (0x01 << 20) 451#define Q81_CTL_RI_DST_COSQ (0x02 << 20) 452#define Q81_CTL_RI_DST_DFLTQ (0x03 << 20) 453#define Q81_CTL_RI_DST_DESTQ (0x04 << 20) 454#define Q81_CTL_RI_DST_DROP (0x07 << 20) 455 456#define Q81_CTL_RI_TYPE_RTMASK (0x00 << 16) 457#define Q81_CTL_RI_TYPE_RTINVMASK (0x01 << 16) 458#define Q81_CTL_RI_TYPE_NICQMASK (0x02 << 16) 459#define Q81_CTL_RI_TYPE_NICQINVMASK (0x03 << 16) 460 461/* these indices for the Routing Index Register are user defined */ 462#define Q81_CTL_RI_IDX_ALL_ERROR (0x00 << 8) 463#define Q81_CTL_RI_IDX_MAC_ERROR (0x00 << 8) 464#define Q81_CTL_RI_IDX_IPCSUM_ERROR (0x01 << 8) 465#define Q81_CTL_RI_IDX_TCPCSUM_ERROR (0x02 << 8) 466#define Q81_CTL_RI_IDX_BCAST (0x03 << 8) 467#define Q81_CTL_RI_IDX_MCAST_MATCH (0x04 << 8) 468#define Q81_CTL_RI_IDX_ALLMULTI (0x05 << 8) 469#define Q81_CTL_RI_IDX_RSS_MATCH (0x08 << 8) 470#define Q81_CTL_RI_IDX_RSS_IPV4 (0x08 << 8) 471#define Q81_CTL_RI_IDX_RSS_IPV6 (0x09 << 8) 472#define Q81_CTL_RI_IDX_RSS_TCPV4 (0x0A << 8) 473#define Q81_CTL_RI_IDX_RSS_TCPV6 (0x0B << 8) 474#define Q81_CTL_RI_IDX_CAM_HIT (0x0C << 8) 475#define Q81_CTL_RI_IDX_PROMISCUOUS (0x0F << 8) 476 477/* Routing Masks to be loaded into Routing Data Register */ 478#define Q81_CTL_RD_BCAST BIT_0 479#define Q81_CTL_RD_MCAST BIT_1 480#define Q81_CTL_RD_MCAST_MATCH BIT_2 481#define Q81_CTL_RD_MCAST_REG_MATCH BIT_3 482#define Q81_CTL_RD_MCAST_HASH_MATCH BIT_4 483#define Q81_CTL_RD_CAM_HIT BIT_7 484#define Q81_CTL_RD_CAM_BIT0 BIT_8 485#define Q81_CTL_RD_CAM_BIT1 BIT_9 486#define Q81_CTL_RD_VLAN_TAG_PRESENT BIT_10 487#define Q81_CTL_RD_VLAN_MATCH BIT_11 488#define Q81_CTL_RD_VLAN_FILTER_PASS BIT_12 489#define Q81_CTL_RD_SKIP_ETHERTYPE_1 BIT_13 490#define Q81_CTL_RD_SKIP_ETHERTYPE_2 BIT_14 491#define Q81_CTL_RD_BCAST_OR_MCAST_MATCH BIT_15 492#define Q81_CTL_RD_802_3_PKT BIT_16 493#define Q81_CTL_RD_LLDP_PKT BIT_17 494#define Q81_CTL_RD_TUNNELED_PKT BIT_18 495#define Q81_CTL_RD_ERROR_PKT BIT_22 496#define Q81_CTL_RD_VALID_PKT BIT_23 497#define Q81_CTL_RD_TCP_UDP_CSUM_ERR BIT_24 498#define Q81_CTL_RD_IPCSUM_ERR BIT_25 499#define Q81_CTL_RD_MAC_ERR BIT_26 500#define Q81_CTL_RD_RSS_TCP_IPV6 BIT_27 501#define Q81_CTL_RD_RSS_TCP_IPV4 BIT_28 502#define Q81_CTL_RD_RSS_IPV6 BIT_29 503#define Q81_CTL_RD_RSS_IPV4 BIT_30 504#define Q81_CTL_RD_RSS_MATCH BIT_31 505 506 507/********************************************************************* 508 * Host Data Structures * 509 *********************************************************************/ 510 511/* 512 * Work Queue Initialization Control Block 513 */ 514 515typedef struct _q81_wq_icb { 516 517 uint16_t length_v; 518#define Q81_WQ_ICB_VALID BIT_4 519 520 uint8_t pri; 521#define Q81_WQ_ICB_PRI_SHIFT 1 522 523 uint8_t flags; 524#define Q81_WQ_ICB_FLAGS_LO BIT_7 525#define Q81_WQ_ICB_FLAGS_LI BIT_6 526#define Q81_WQ_ICB_FLAGS_LB BIT_5 527#define Q81_WQ_ICB_FLAGS_LC BIT_4 528 529 uint16_t wqcqid_rss; 530#define Q81_WQ_ICB_RSS_V BIT_15 531 532 uint16_t rsrvd; 533 534 uint32_t baddr_lo; 535 uint32_t baddr_hi; 536 537 uint32_t ci_addr_lo; 538 uint32_t ci_addr_hi; 539} __packed q81_wq_icb_t; 540 541 542/* 543 * Completion Queue Initialization Control Block 544 */ 545 546typedef struct _q81_cq_icb { 547 uint8_t msix_vector; 548 uint16_t rsrvd0; 549 uint8_t flags; 550#define Q81_CQ_ICB_FLAGS_LC BIT_7 551#define Q81_CQ_ICB_FLAGS_LI BIT_6 552#define Q81_CQ_ICB_FLAGS_LL BIT_5 553#define Q81_CQ_ICB_FLAGS_LS BIT_4 554#define Q81_CQ_ICB_FLAGS_LV BIT_3 555 556 uint16_t length_v; 557#define Q81_CQ_ICB_VALID BIT_4 558 559 uint16_t rsrvd1; 560 561 uint32_t cq_baddr_lo; 562 uint32_t cq_baddr_hi; 563 564 uint32_t cqi_addr_lo; 565 uint32_t cqi_addr_hi; 566 567 uint16_t pkt_idelay; 568 uint16_t idelay; 569 570 uint32_t lbq_baddr_lo; 571 uint32_t lbq_baddr_hi; 572 uint16_t lbq_bsize; 573 uint16_t lbq_length; 574 575 uint32_t sbq_baddr_lo; 576 uint32_t sbq_baddr_hi; 577 uint16_t sbq_bsize; 578 uint16_t sbq_length; 579} __packed q81_cq_icb_t; 580 581/* 582 * RSS Initialization Control Block 583 */ 584typedef struct _q81_rss_icb { 585 uint16_t flags_base_cq_num; 586#define Q81_RSS_ICB_FLAGS_L4K BIT_7 587#define Q81_RSS_ICB_FLAGS_L6K BIT_8 588#define Q81_RSS_ICB_FLAGS_LI BIT_9 589#define Q81_RSS_ICB_FLAGS_LB BIT_10 590#define Q81_RSS_ICB_FLAGS_LM BIT_11 591#define Q81_RSS_ICB_FLAGS_RI4 BIT_12 592#define Q81_RSS_ICB_FLAGS_RT4 BIT_13 593#define Q81_RSS_ICB_FLAGS_RI6 BIT_14 594#define Q81_RSS_ICB_FLAGS_RT6 BIT_15 595 596 uint16_t mask; /* bits 9-0 are valid */ 597 598#define Q81_RSS_ICB_NUM_INDTBL_ENTRIES 1024 599 /* Indirection Table */ 600 uint8_t cq_id[Q81_RSS_ICB_NUM_INDTBL_ENTRIES]; 601 602 /* Hash Keys */ 603 uint32_t ipv6_rss_hash_key[10]; 604 uint32_t ipv4_rss_hash_key[4]; 605} __packed q81_rss_icb_t; 606 607 608 609/* 610 * Transmit Buffer Descriptor 611 */ 612 613typedef struct _q81_txb_desc { 614 uint64_t baddr; 615 uint16_t length; 616 617 uint16_t flags; 618#define Q81_TXB_DESC_FLAGS_E BIT_15 619#define Q81_TXB_DESC_FLAGS_C BIT_14 620 621} __packed q81_txb_desc_t; 622 623 624/* 625 * Receive Buffer Descriptor 626 */ 627 628typedef struct _q81_rxb_desc { 629 uint32_t baddr_lo; 630#define Q81_RXB_DESC_BADDR_LO_S BIT_1 631 632 uint64_t baddr; 633 634 uint16_t length; 635 636 uint16_t flags; 637#define Q81_RXB_DESC_FLAGS_E BIT_15 638#define Q81_RXB_DESC_FLAGS_C BIT_14 639 640} __packed q81_rxb_desc_t; 641 642/* 643 * IOCB Types 644 */ 645 646#define Q81_IOCB_TX_MAC 0x01 647#define Q81_IOCB_TX_TSO 0x02 648#define Q81_IOCB_RX 0x20 649#define Q81_IOCB_MPI 0x21 650#define Q81_IOCB_SYS 0x3F 651 652 653/* 654 * IOCB Definitions 655 */ 656 657/* 658 * MAC Tx Frame IOCB 659 * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 660 */ 661#define MAX_TX_MAC_DESC 8 662 663typedef struct _q81_tx_mac { 664 665 uint8_t opcode; 666 667 uint16_t flags; 668#define Q81_TX_MAC_FLAGS_D BIT_3 669#define Q81_TX_MAC_FLAGS_I BIT_1 670#define Q81_TX_MAC_FLAGS_OI BIT_0 671 672 uint8_t vlan_off; 673#define Q81_TX_MAC_VLAN_OFF_SHIFT 3 674#define Q81_TX_MAC_VLAN_OFF_V BIT_2 675#define Q81_TX_MAC_VLAN_OFF_DFP BIT_1 676 677 uint32_t rsrvd1; 678 uint32_t rsrvd2; 679 680 uint16_t frame_length; /* only bits0-13 are valid */ 681 uint16_t rsrvd3; 682 683 uint32_t tid_lo; 684 uint32_t tid_hi; 685 686 uint32_t rsrvd4; 687 688 uint16_t vlan_tci; 689 uint16_t rsrvd5; 690 691 q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 692} __packed q81_tx_mac_t; 693 694 695/* 696 * MAC Tx Frame with TSO IOCB 697 * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 698 */ 699typedef struct _q81_tx_tso { 700 uint8_t opcode; 701 702 uint16_t flags; 703#define Q81_TX_TSO_FLAGS_OI BIT_0 704#define Q81_TX_TSO_FLAGS_I BIT_1 705#define Q81_TX_TSO_FLAGS_D BIT_3 706#define Q81_TX_TSO_FLAGS_IPV4 BIT_6 707#define Q81_TX_TSO_FLAGS_IPV6 BIT_7 708#define Q81_TX_TSO_FLAGS_LSO BIT_13 709#define Q81_TX_TSO_FLAGS_UC BIT_14 710#define Q81_TX_TSO_FLAGS_TC BIT_15 711 712 uint8_t vlan_off; 713#define Q81_TX_TSO_VLAN_OFF_SHIFT 3 714#define Q81_TX_TSO_VLAN_OFF_V BIT_2 715#define Q81_TX_TSO_VLAN_OFF_DFP BIT_1 716#define Q81_TX_TSO_VLAN_OFF_IC BIT_0 717 718 uint32_t rsrvd1; 719 uint32_t rsrvd2; 720 721 uint32_t length; 722 uint32_t tid_lo; 723 uint32_t tid_hi; 724 725 uint16_t phdr_length; 726 727 uint16_t phdr_offsets; 728#define Q81_TX_TSO_PHDR_SHIFT 6 729 730 uint16_t vlan_tci; 731 uint16_t mss; 732 733 q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 734} __packed q81_tx_tso_t; 735 736typedef struct _q81_tx_cmd { 737 uint8_t bytes[128]; 738} __packed q81_tx_cmd_t; 739 740/* 741 * MAC TX Frame Completion 742 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 743 */ 744 745typedef struct _q81_tx_mac_comp { 746 uint8_t opcode; 747 748 uint8_t flags; 749#define Q81_TX_MAC_COMP_FLAGS_OI BIT_0 750#define Q81_TX_MAC_COMP_FLAGS_I BIT_1 751#define Q81_TX_MAC_COMP_FLAGS_E BIT_3 752#define Q81_TX_MAC_COMP_FLAGS_S BIT_4 753#define Q81_TX_MAC_COMP_FLAGS_L BIT_5 754#define Q81_TX_MAC_COMP_FLAGS_P BIT_6 755 756 uint8_t rsrvd0; 757 758 uint8_t err; 759#define Q81_TX_MAC_COMP_ERR_B BIT_7 760 761 uint32_t tid_lo; 762 uint32_t tid_hi; 763 764 uint32_t rsrvd1[13]; 765} __packed q81_tx_mac_comp_t; 766 767 768/* 769 * MAC TX Frame with LSO Completion 770 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 771 */ 772 773typedef struct _q81_tx_tso_comp { 774 uint8_t opcode; 775 776 uint8_t flags; 777#define Q81_TX_TSO_COMP_FLAGS_OI BIT_0 778#define Q81_TX_TSO_COMP_FLAGS_I BIT_1 779#define Q81_TX_TSO_COMP_FLAGS_E BIT_3 780#define Q81_TX_TSO_COMP_FLAGS_S BIT_4 781#define Q81_TX_TSO_COMP_FLAGS_P BIT_6 782 783 uint8_t rsrvd0; 784 785 uint8_t err; 786#define Q81_TX_TSO_COMP_ERR_B BIT_7 787 788 uint32_t tid_lo; 789 uint32_t tid_hi; 790 791 uint32_t rsrvd1[13]; 792} __packed q81_tx_tso_comp_t; 793 794 795/* 796 * SYS - Chip Event Notification Completion 797 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 798 */ 799 800typedef struct _q81_sys_comp { 801 uint8_t opcode; 802 803 uint8_t flags; 804#define Q81_SYS_COMP_FLAGS_OI BIT_0 805#define Q81_SYS_COMP_FLAGS_I BIT_1 806 807 uint8_t etype; 808#define Q81_SYS_COMPE_LINK_UP 0x00 809#define Q81_SYS_COMPE_LINK_DOWN 0x01 810#define Q81_SYS_COMPE_MULTI_CAM_LOOKUP 0x06 811#define Q81_SYS_COMPE_SOFT_ECC 0x07 812#define Q81_SYS_COMPE_MPI_FATAL_ERROR 0x08 813#define Q81_SYS_COMPE_MAC_INTR 0x09 814#define Q81_SYS_COMPE_GPI0_HTOL 0x10 815#define Q81_SYS_COMPE_GPI0_LTOH 0x20 816#define Q81_SYS_COMPE_GPI1_HTOL 0x11 817#define Q81_SYS_COMPE_GPI1_LTOH 0x21 818 819 uint8_t q_id; /* only bits 0-6 are valid */ 820 821 uint32_t rsrvd1[15]; 822} __packed q81_sys_comp_t; 823 824 825 826/* 827 * Mac Rx Packet Completion 828 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 829 */ 830 831typedef struct _q81_rx { 832 uint8_t opcode; 833 834 uint8_t flags0; 835#define Q81_RX_FLAGS0_OI BIT_0 836#define Q81_RX_FLAGS0_I BIT_1 837#define Q81_RX_FLAGS0_TE BIT_2 838#define Q81_RX_FLAGS0_NU BIT_3 839#define Q81_RX_FLAGS0_IE BIT_4 840 841#define Q81_RX_FLAGS0_MCAST_MASK (0x03 << 5) 842#define Q81_RX_FLAGS0_MCAST_NONE (0x00 << 5) 843#define Q81_RX_FLAGS0_MCAST_HASH_MATCH (0x01 << 5) 844#define Q81_RX_FLAGS0_MCAST_REG_MATCH (0x02 << 5) 845#define Q81_RX_FLAGS0_MCAST_PROMISC (0x03 << 5) 846 847#define Q81_RX_FLAGS0_B BIT_7 848 849 uint16_t flags1; 850#define Q81_RX_FLAGS1_P BIT_0 851#define Q81_RX_FLAGS1_V BIT_1 852 853#define Q81_RX_FLAGS1_ERR_NONE (0x00 << 2) 854#define Q81_RX_FLAGS1_ERR_CODE (0x01 << 2) 855#define Q81_RX_FLAGS1_ERR_OSIZE (0x02 << 2) 856#define Q81_RX_FLAGS1_ERR_USIZE (0x04 << 2) 857#define Q81_RX_FLAGS1_ERR_PREAMBLE (0x05 << 2) 858#define Q81_RX_FLAGS1_ERR_FRAMELENGTH (0x06 << 2) 859#define Q81_RX_FLAGS1_ERR_CRC (0x07 << 2) 860#define Q81_RX_FLAGS1_ERR_MASK (0x07 << 2) 861 862#define Q81_RX_FLAGS1_U BIT_5 863#define Q81_RX_FLAGS1_T BIT_6 864#define Q81_RX_FLAGS1_FO BIT_7 865#define Q81_RX_FLAGS1_RSS_NO_MATCH (0x00 << 8) 866#define Q81_RX_FLAGS1_RSS_IPV4_MATCH (0x04 << 8) 867#define Q81_RX_FLAGS1_RSS_IPV6_MATCH (0x02 << 8) 868#define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 869#define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 870#define Q81_RX_FLAGS1_RSS_MATCH_MASK (0x07 << 8) 871#define Q81_RX_FLAGS1_V4 BIT_11 872#define Q81_RX_FLAGS1_V6 BIT_12 873#define Q81_RX_FLAGS1_IH BIT_13 874#define Q81_RX_FLAGS1_DS BIT_14 875#define Q81_RX_FLAGS1_DL BIT_15 876 877 uint32_t length; 878 uint64_t b_paddr; 879 880 uint32_t rss; 881 uint16_t vlan_tag; 882 uint16_t rsrvd; 883 uint32_t rsrvd1; 884 uint32_t flags2; 885#define Q81_RX_FLAGS2_HV BIT_13 886#define Q81_RX_FLAGS2_HS BIT_14 887#define Q81_RX_FLAGS2_HL BIT_15 888 889 uint32_t hdr_length; 890 uint32_t hdr_baddr_lo; 891 uint32_t hdr_baddr_hi; 892 893} __packed q81_rx_t; 894 895typedef struct _q81_cq_e { 896 uint8_t opcode; 897 uint8_t bytes[63]; 898} __packed q81_cq_e_t; 899 900typedef struct _q81_bq_addr_e { 901 uint32_t addr_lo; 902 uint32_t addr_hi; 903} __packed q81_bq_addr_e_t; 904 905 906/* 907 * Macros for reading and writing registers 908 */ 909 910#if defined(__i386__) || defined(__amd64__) 911#define Q8_MB() __asm volatile("mfence" ::: "memory") 912#define Q8_WMB() __asm volatile("sfence" ::: "memory") 913#define Q8_RMB() __asm volatile("lfence" ::: "memory") 914#else 915#define Q8_MB() 916#define Q8_WMB() 917#define Q8_RMB() 918#endif 919 920#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 921#define READ_REG64(ha, reg) bus_read_8((ha->pci_reg), reg) 922 923#define WRITE_REG32_ONLY(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 924 925#define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 926 927#define Q81_CTL_INTRE_MASK_VALUE \ 928 (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 929 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_ENABLE) 930 931#define Q81_ENABLE_INTR(ha, idx) \ 932 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx)) 933 934#define Q81_CTL_INTRD_MASK_VALUE \ 935 (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 936 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_DISABLE) 937 938#define Q81_DISABLE_INTR(ha, idx) \ 939 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx)) 940 941#define Q81_WR_WQ_PROD_IDX(wq_idx, idx) bus_write_4((ha->pci_reg1),\ 942 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG), idx) 943 944#define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\ 945 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG)) 946 947 948#define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\ 949 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 950 Q81_COMPQ_VALID_V) 951 952#define Q81_SET_WQ_INVALID(wq_idx) bus_write_4((ha->pci_reg1),\ 953 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 954 (~Q81_COMPQ_VALID_V)) 955 956#define Q81_WR_CQ_CONS_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 957 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG), idx) 958 959#define Q81_RD_CQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 960 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG)) 961 962#define Q81_SET_CQ_VALID(cq_idx) bus_write_4((ha->pci_reg1),\ 963 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 964 Q81_COMPQ_VALID_V) 965 966#define Q81_SET_CQ_INVALID(cq_idx) bus_write_4((ha->pci_reg1),\ 967 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 968 ~Q81_COMPQ_VALID_V) 969 970#define Q81_WR_LBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 971 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG), idx) 972 973#define Q81_RD_LBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 974 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG)) 975 976#define Q81_WR_SBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 977 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG), idx) 978 979#define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 980 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG)) 981 982 983/* 984 * Flash Related 985 */ 986 987#define Q81_F0_FLASH_OFFSET 0x140200 988#define Q81_F1_FLASH_OFFSET 0x140600 989#define Q81_FLASH_ID "8000" 990 991typedef struct _q81_flash { 992 993 uint8_t id[4]; /* equal to "8000" */ 994 995 uint16_t version; 996 uint16_t size; 997 uint16_t csum; 998 uint16_t rsrvd0; 999 uint16_t total_size; 1000 uint16_t nentries; 1001 1002 uint8_t dtype0; 1003 uint8_t dsize0; 1004 uint8_t mac_addr0[6]; 1005 1006 uint8_t dtype1; 1007 uint8_t dsize1; 1008 uint8_t mac_addr1[6]; 1009 1010 uint8_t dtype2; 1011 uint8_t dsize2; 1012 uint16_t vlan_id; 1013 1014 uint8_t dtype3; 1015 uint8_t dsize3; 1016 uint16_t last; 1017 1018 uint8_t rsrvd1[464]; 1019 1020 uint16_t subsys_vid; 1021 uint16_t subsys_did; 1022 1023 uint8_t rsrvd2[4]; 1024} __packed q81_flash_t; 1025 1026 1027/* 1028 * MPI Related 1029 */ 1030 1031#define Q81_NUM_MBX_REGISTERS 16 1032#define Q81_NUM_AEN_REGISTERS 9 1033 1034#define Q81_FUNC0_MBX_IN_REG0 0x1180 1035#define Q81_FUNC0_MBX_OUT_REG0 0x1190 1036 1037#define Q81_FUNC1_MBX_IN_REG0 0x1280 1038#define Q81_FUNC1_MBX_OUT_REG0 0x1290 1039 1040#define Q81_MBX_NOP 0x0000 1041#define Q81_MBX_EXEC_FW 0x0002 1042#define Q81_MBX_REG_TEST 0x0006 1043#define Q81_MBX_VERIFY_CHKSUM 0x0007 1044#define Q81_MBX_ABOUT_FW 0x0008 1045#define Q81_MBX_RISC_MEMCPY 0x000A 1046#define Q81_MBX_LOAD_RISC_RAM 0x000B 1047#define Q81_MBX_DUMP_RISC_RAM 0x000C 1048#define Q81_MBX_WR_RAM_WORD 0x000D 1049#define Q81_MBX_INIT_RISC_RAM 0x000E 1050#define Q81_MBX_RD_RAM_WORD 0x000F 1051#define Q81_MBX_STOP_FW 0x0014 1052#define Q81_MBX_GEN_SYS_ERR 0x002A 1053#define Q81_MBX_WR_SFP_PLUS 0x0030 1054#define Q81_MBX_RD_SFP_PLUS 0x0031 1055#define Q81_MBX_INIT_FW 0x0060 1056#define Q81_MBX_GET_IFCB 0x0061 1057#define Q81_MBX_GET_FW_STATE 0x0069 1058#define Q81_MBX_IDC_REQ 0x0100 1059#define Q81_MBX_IDC_ACK 0x0101 1060#define Q81_MBX_IDC_TIME_EXTEND 0x0102 1061#define Q81_MBX_WOL_MODE 0x0110 1062#define Q81_MBX_SET_WOL_FILTER 0x0111 1063#define Q81_MBX_CLR_WOL_FILTER 0x0112 1064#define Q81_MBX_SET_WOL_MAGIC 0x0113 1065#define Q81_MBX_WOL_MODE_IMM 0x0115 1066#define Q81_MBX_PORT_RESET 0x0120 1067#define Q81_MBX_SET_PORT_CFG 0x0122 1068#define Q81_MBX_GET_PORT_CFG 0x0123 1069#define Q81_MBX_GET_LNK_STATUS 0x0124 1070#define Q81_MBX_SET_LED_CFG 0x0125 1071#define Q81_MBX_GET_LED_CFG 0x0126 1072#define Q81_MBX_SET_DCBX_CTLB 0x0130 1073#define Q81_MBX_GET_DCBX_CTLB 0x0131 1074#define Q81_MBX_GET_DCBX_TLV 0x0132 1075#define Q81_MBX_DIAG_CMDS 0x0150 1076#define Q81_MBX_SET_MGMT_CTL 0x0160 1077#define Q81_MBX_SET_MGMT_CTL_STOP 0x01 1078#define Q81_MBX_SET_MGMT_CTL_RESUME 0x02 1079#define Q81_MBX_GET_MGMT_CTL 0x0161 1080#define Q81_MBX_GET_MGMT_CTL_MASK ~0x3 1081#define Q81_MBX_GET_MGMT_CTL_FIFO_EMPTY 0x02 1082#define Q81_MBX_GET_MGMT_CTL_SET_MGMT 0x01 1083 1084#define Q81_MBX_CMD_COMPLETE 0x4000 1085#define Q81_MBX_CMD_INVALID 0x4001 1086#define Q81_MBX_CMD_TEST_FAILED 0x4003 1087#define Q81_MBX_CMD_ERROR 0x4005 1088#define Q81_MBX_CMD_PARAM_ERROR 0x4006 1089 1090#endif /* #ifndef _QLS_HW_H_ */ 1091