ppc.c revision 63403
1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/ppc/ppc.c 63403 2000-07-18 09:01:09Z dfr $ 27 * 28 */ 29 30#include "opt_ppc.h" 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/malloc.h> 37 38#include <vm/vm.h> 39#include <vm/pmap.h> 40#include <machine/clock.h> 41#include <machine/bus.h> 42#include <machine/resource.h> 43#include <machine/vmparam.h> 44#include <sys/rman.h> 45 46#include <isa/isareg.h> 47#include <isa/isavar.h> 48 49#include <dev/ppbus/ppbconf.h> 50#include <dev/ppbus/ppb_msq.h> 51 52#include <isa/ppcreg.h> 53 54#include "ppbus_if.h" 55 56#define LOG_PPC(function, ppc, string) \ 57 if (bootverbose) printf("%s: %s\n", function, string) 58 59 60#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 61 62devclass_t ppc_devclass; 63 64static int ppc_probe(device_t dev); 65static int ppc_attach(device_t dev); 66static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val); 67 68static void ppc_reset_epp(device_t); 69static void ppc_ecp_sync(device_t); 70static void ppcintr(void *arg); 71 72static int ppc_exec_microseq(device_t, struct ppb_microseq **); 73static int ppc_setmode(device_t, int); 74 75static int ppc_read(device_t, char *, int, int); 76static int ppc_write(device_t, char *, int, int); 77 78static u_char ppc_io(device_t, int, u_char *, int, u_char); 79 80static int ppc_setup_intr(device_t, device_t, struct resource *, int, 81 void (*)(void *), void *, void **); 82static int ppc_teardown_intr(device_t, device_t, struct resource *, void *); 83 84static device_method_t ppc_methods[] = { 85 /* device interface */ 86 DEVMETHOD(device_probe, ppc_probe), 87 DEVMETHOD(device_attach, ppc_attach), 88 89 /* bus interface */ 90 DEVMETHOD(bus_read_ivar, ppc_read_ivar), 91 DEVMETHOD(bus_setup_intr, ppc_setup_intr), 92 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), 93 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 94 95 /* ppbus interface */ 96 DEVMETHOD(ppbus_io, ppc_io), 97 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), 98 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), 99 DEVMETHOD(ppbus_setmode, ppc_setmode), 100 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), 101 DEVMETHOD(ppbus_read, ppc_read), 102 DEVMETHOD(ppbus_write, ppc_write), 103 104 { 0, 0 } 105 }; 106 107static driver_t ppc_driver = { 108 "ppc", 109 ppc_methods, 110 sizeof(struct ppc_data), 111}; 112 113static char *ppc_models[] = { 114 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 115 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 116 "SMC FDC37C935", 0 117}; 118 119/* list of available modes */ 120static char *ppc_avms[] = { 121 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 122 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 123 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 124 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 125}; 126 127/* list of current executing modes 128 * Note that few modes do not actually exist. 129 */ 130static char *ppc_modes[] = { 131 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 132 "EPP", "EPP", "EPP", "ECP", 133 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 134 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 135}; 136 137static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 138 139#ifdef __i386__ 140/* 141 * BIOS printer list - used by BIOS probe. 142 */ 143#define BIOS_PPC_PORTS 0x408 144#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 145#define BIOS_MAX_PPC 4 146#endif 147 148/* 149 * ppc_ecp_sync() XXX 150 */ 151static void 152ppc_ecp_sync(device_t dev) { 153 154 int i, r; 155 struct ppc_data *ppc = DEVTOSOFTC(dev); 156 157 if (!(ppc->ppc_avm & PPB_ECP)) 158 return; 159 160 r = r_ecr(ppc); 161 if ((r & 0xe0) != PPC_ECR_EPP) 162 return; 163 164 for (i = 0; i < 100; i++) { 165 r = r_ecr(ppc); 166 if (r & 0x1) 167 return; 168 DELAY(100); 169 } 170 171 printf("ppc%d: ECP sync failed as data still " \ 172 "present in FIFO.\n", ppc->ppc_unit); 173 174 return; 175} 176 177/* 178 * ppc_detect_fifo() 179 * 180 * Detect parallel port FIFO 181 */ 182static int 183ppc_detect_fifo(struct ppc_data *ppc) 184{ 185 char ecr_sav; 186 char ctr_sav, ctr, cc; 187 short i; 188 189 /* save registers */ 190 ecr_sav = r_ecr(ppc); 191 ctr_sav = r_ctr(ppc); 192 193 /* enter ECP configuration mode, no interrupt, no DMA */ 194 w_ecr(ppc, 0xf4); 195 196 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 197 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 198 199 /* XXX 16 and 32 bits implementations not supported */ 200 if (ppc->ppc_pword != PPC_PWORD_8) { 201 LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 202 goto error; 203 } 204 205 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 206 ctr = r_ctr(ppc); 207 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 208 209 /* enter ECP test mode, no interrupt, no DMA */ 210 w_ecr(ppc, 0xd4); 211 212 /* flush the FIFO */ 213 for (i=0; i<1024; i++) { 214 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 215 break; 216 cc = r_fifo(ppc); 217 } 218 219 if (i >= 1024) { 220 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 221 goto error; 222 } 223 224 /* enable interrupts, no DMA */ 225 w_ecr(ppc, 0xd0); 226 227 /* determine readIntrThreshold 228 * fill the FIFO until serviceIntr is set 229 */ 230 for (i=0; i<1024; i++) { 231 w_fifo(ppc, (char)i); 232 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 233 /* readThreshold reached */ 234 ppc->ppc_rthr = i+1; 235 } 236 if (r_ecr(ppc) & PPC_FIFO_FULL) { 237 ppc->ppc_fifo = i+1; 238 break; 239 } 240 } 241 242 if (i >= 1024) { 243 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 244 goto error; 245 } 246 247 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 248 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 249 w_ecr(ppc, 0xd0); /* enable interrupts */ 250 251 /* determine writeIntrThreshold 252 * empty the FIFO until serviceIntr is set 253 */ 254 for (i=ppc->ppc_fifo; i>0; i--) { 255 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 256 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 257 goto error; 258 } 259 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 260 /* writeIntrThreshold reached */ 261 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 262 } 263 /* if FIFO empty before the last byte, error */ 264 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 265 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 266 goto error; 267 } 268 } 269 270 /* FIFO must be empty after the last byte */ 271 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 272 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 273 goto error; 274 } 275 276 w_ctr(ppc, ctr_sav); 277 w_ecr(ppc, ecr_sav); 278 279 return (0); 280 281error: 282 w_ctr(ppc, ctr_sav); 283 w_ecr(ppc, ecr_sav); 284 285 return (EINVAL); 286} 287 288static int 289ppc_detect_port(struct ppc_data *ppc) 290{ 291 292 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 293 w_dtr(ppc, 0xaa); 294 if (r_dtr(ppc) != 0xaa) 295 return (0); 296 297 return (1); 298} 299 300/* 301 * EPP timeout, according to the PC87332 manual 302 * Semantics of clearing EPP timeout bit. 303 * PC87332 - reading SPP_STR does it... 304 * SMC - write 1 to EPP timeout bit XXX 305 * Others - (?) write 0 to EPP timeout bit 306 */ 307static void 308ppc_reset_epp_timeout(struct ppc_data *ppc) 309{ 310 register char r; 311 312 r = r_str(ppc); 313 w_str(ppc, r | 0x1); 314 w_str(ppc, r & 0xfe); 315 316 return; 317} 318 319static int 320ppc_check_epp_timeout(struct ppc_data *ppc) 321{ 322 ppc_reset_epp_timeout(ppc); 323 324 return (!(r_str(ppc) & TIMEOUT)); 325} 326 327/* 328 * Configure current operating mode 329 */ 330static int 331ppc_generic_setmode(struct ppc_data *ppc, int mode) 332{ 333 u_char ecr = 0; 334 335 /* check if mode is available */ 336 if (mode && !(ppc->ppc_avm & mode)) 337 return (EINVAL); 338 339 /* if ECP mode, configure ecr register */ 340 if (ppc->ppc_avm & PPB_ECP) { 341 /* return to byte mode (keeping direction bit), 342 * no interrupt, no DMA to be able to change to 343 * ECP 344 */ 345 w_ecr(ppc, PPC_ECR_RESET); 346 ecr = PPC_DISABLE_INTR; 347 348 if (mode & PPB_EPP) 349 return (EINVAL); 350 else if (mode & PPB_ECP) 351 /* select ECP mode */ 352 ecr |= PPC_ECR_ECP; 353 else if (mode & PPB_PS2) 354 /* select PS2 mode with ECP */ 355 ecr |= PPC_ECR_PS2; 356 else 357 /* select COMPATIBLE/NIBBLE mode */ 358 ecr |= PPC_ECR_STD; 359 360 w_ecr(ppc, ecr); 361 } 362 363 ppc->ppc_mode = mode; 364 365 return (0); 366} 367 368/* 369 * The ppc driver is free to choose options like FIFO or DMA 370 * if ECP mode is available. 371 * 372 * The 'RAW' option allows the upper drivers to force the ppc mode 373 * even with FIFO, DMA available. 374 */ 375static int 376ppc_smclike_setmode(struct ppc_data *ppc, int mode) 377{ 378 u_char ecr = 0; 379 380 /* check if mode is available */ 381 if (mode && !(ppc->ppc_avm & mode)) 382 return (EINVAL); 383 384 /* if ECP mode, configure ecr register */ 385 if (ppc->ppc_avm & PPB_ECP) { 386 /* return to byte mode (keeping direction bit), 387 * no interrupt, no DMA to be able to change to 388 * ECP or EPP mode 389 */ 390 w_ecr(ppc, PPC_ECR_RESET); 391 ecr = PPC_DISABLE_INTR; 392 393 if (mode & PPB_EPP) 394 /* select EPP mode */ 395 ecr |= PPC_ECR_EPP; 396 else if (mode & PPB_ECP) 397 /* select ECP mode */ 398 ecr |= PPC_ECR_ECP; 399 else if (mode & PPB_PS2) 400 /* select PS2 mode with ECP */ 401 ecr |= PPC_ECR_PS2; 402 else 403 /* select COMPATIBLE/NIBBLE mode */ 404 ecr |= PPC_ECR_STD; 405 406 w_ecr(ppc, ecr); 407 } 408 409 ppc->ppc_mode = mode; 410 411 return (0); 412} 413 414#ifdef PPC_PROBE_CHIPSET 415/* 416 * ppc_pc873xx_detect 417 * 418 * Probe for a Natsemi PC873xx-family part. 419 * 420 * References in this function are to the National Semiconductor 421 * PC87332 datasheet TL/C/11930, May 1995 revision. 422 */ 423static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 424static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 425static int pc873xx_irqtab[] = {5, 7, 5, 0}; 426 427static int pc873xx_regstab[] = { 428 PC873_FER, PC873_FAR, PC873_PTR, 429 PC873_FCR, PC873_PCR, PC873_PMC, 430 PC873_TUP, PC873_SID, PC873_PNP0, 431 PC873_PNP1, PC873_LPTBA, -1 432}; 433 434static char *pc873xx_rnametab[] = { 435 "FER", "FAR", "PTR", "FCR", "PCR", 436 "PMC", "TUP", "SID", "PNP0", "PNP1", 437 "LPTBA", NULL 438}; 439 440static int 441ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 442{ 443 static int index = 0; 444 int idport, irq; 445 int ptr, pcr, val, i; 446 447 while ((idport = pc873xx_basetab[index++])) { 448 449 /* XXX should check first to see if this location is already claimed */ 450 451 /* 452 * Pull the 873xx through the power-on ID cycle (2.2,1.). 453 * We can't use this to locate the chip as it may already have 454 * been used by the BIOS. 455 */ 456 (void)inb(idport); (void)inb(idport); 457 (void)inb(idport); (void)inb(idport); 458 459 /* 460 * Read the SID byte. Possible values are : 461 * 462 * 01010xxx PC87334 463 * 0001xxxx PC87332 464 * 01110xxx PC87306 465 */ 466 outb(idport, PC873_SID); 467 val = inb(idport + 1); 468 if ((val & 0xf0) == 0x10) { 469 ppc->ppc_model = NS_PC87332; 470 } else if ((val & 0xf8) == 0x70) { 471 ppc->ppc_model = NS_PC87306; 472 } else if ((val & 0xf8) == 0x50) { 473 ppc->ppc_model = NS_PC87334; 474 } else { 475 if (bootverbose && (val != 0xff)) 476 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 477 continue ; /* not recognised */ 478 } 479 480 /* print registers */ 481 if (bootverbose) { 482 printf("PC873xx"); 483 for (i=0; pc873xx_regstab[i] != -1; i++) { 484 outb(idport, pc873xx_regstab[i]); 485 printf(" %s=0x%x", pc873xx_rnametab[i], 486 inb(idport + 1) & 0xff); 487 } 488 printf("\n"); 489 } 490 491 /* 492 * We think we have one. Is it enabled and where we want it to be? 493 */ 494 outb(idport, PC873_FER); 495 val = inb(idport + 1); 496 if (!(val & PC873_PPENABLE)) { 497 if (bootverbose) 498 printf("PC873xx parallel port disabled\n"); 499 continue; 500 } 501 outb(idport, PC873_FAR); 502 val = inb(idport + 1) & 0x3; 503 /* XXX we should create a driver instance for every port found */ 504 if (pc873xx_porttab[val] != ppc->ppc_base) { 505 if (bootverbose) 506 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 507 pc873xx_porttab[val], ppc->ppc_base); 508 continue; 509 } 510 511 outb(idport, PC873_PTR); 512 ptr = inb(idport + 1); 513 514 /* get irq settings */ 515 if (ppc->ppc_base == 0x378) 516 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 517 else 518 irq = pc873xx_irqtab[val]; 519 520 if (bootverbose) 521 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 522 523 /* 524 * Check if irq settings are correct 525 */ 526 if (irq != ppc->ppc_irq) { 527 /* 528 * If the chipset is not locked and base address is 0x378, 529 * we have another chance 530 */ 531 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 532 if (ppc->ppc_irq == 7) { 533 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 534 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 535 } else { 536 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 537 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 538 } 539 if (bootverbose) 540 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 541 } else { 542 if (bootverbose) 543 printf("PC873xx sorry, can't change irq setting\n"); 544 } 545 } else { 546 if (bootverbose) 547 printf("PC873xx irq settings are correct\n"); 548 } 549 550 outb(idport, PC873_PCR); 551 pcr = inb(idport + 1); 552 553 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 554 if (bootverbose) 555 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 556 557 ppc->ppc_avm |= PPB_NIBBLE; 558 if (bootverbose) 559 printf(", NIBBLE"); 560 561 if (pcr & PC873_EPPEN) { 562 ppc->ppc_avm |= PPB_EPP; 563 564 if (bootverbose) 565 printf(", EPP"); 566 567 if (pcr & PC873_EPP19) 568 ppc->ppc_epp = EPP_1_9; 569 else 570 ppc->ppc_epp = EPP_1_7; 571 572 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 573 outb(idport, PC873_PTR); 574 ptr = inb(idport + 1); 575 if (ptr & PC873_EPPRDIR) 576 printf(", Regular mode"); 577 else 578 printf(", Automatic mode"); 579 } 580 } else if (pcr & PC873_ECPEN) { 581 ppc->ppc_avm |= PPB_ECP; 582 if (bootverbose) 583 printf(", ECP"); 584 585 if (pcr & PC873_ECPCLK) { /* XXX */ 586 ppc->ppc_avm |= PPB_PS2; 587 if (bootverbose) 588 printf(", PS/2"); 589 } 590 } else { 591 outb(idport, PC873_PTR); 592 ptr = inb(idport + 1); 593 if (ptr & PC873_EXTENDED) { 594 ppc->ppc_avm |= PPB_SPP; 595 if (bootverbose) 596 printf(", SPP"); 597 } 598 } 599 } else { 600 if (bootverbose) 601 printf("PC873xx unlocked"); 602 603 if (chipset_mode & PPB_ECP) { 604 if ((chipset_mode & PPB_EPP) && bootverbose) 605 printf(", ECP+EPP not supported"); 606 607 pcr &= ~PC873_EPPEN; 608 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 609 outb(idport + 1, pcr); 610 outb(idport + 1, pcr); 611 612 if (bootverbose) 613 printf(", ECP"); 614 615 } else if (chipset_mode & PPB_EPP) { 616 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 617 pcr |= (PC873_EPPEN | PC873_EPP19); 618 outb(idport + 1, pcr); 619 outb(idport + 1, pcr); 620 621 ppc->ppc_epp = EPP_1_9; /* XXX */ 622 623 if (bootverbose) 624 printf(", EPP1.9"); 625 626 /* enable automatic direction turnover */ 627 if (ppc->ppc_model == NS_PC87332) { 628 outb(idport, PC873_PTR); 629 ptr = inb(idport + 1); 630 ptr &= ~PC873_EPPRDIR; 631 outb(idport + 1, ptr); 632 outb(idport + 1, ptr); 633 634 if (bootverbose) 635 printf(", Automatic mode"); 636 } 637 } else { 638 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 639 outb(idport + 1, pcr); 640 outb(idport + 1, pcr); 641 642 /* configure extended bit in PTR */ 643 outb(idport, PC873_PTR); 644 ptr = inb(idport + 1); 645 646 if (chipset_mode & PPB_PS2) { 647 ptr |= PC873_EXTENDED; 648 649 if (bootverbose) 650 printf(", PS/2"); 651 652 } else { 653 /* default to NIBBLE mode */ 654 ptr &= ~PC873_EXTENDED; 655 656 if (bootverbose) 657 printf(", NIBBLE"); 658 } 659 outb(idport + 1, ptr); 660 outb(idport + 1, ptr); 661 } 662 663 ppc->ppc_avm = chipset_mode; 664 } 665 666 if (bootverbose) 667 printf("\n"); 668 669 ppc->ppc_type = PPC_TYPE_GENERIC; 670 ppc_generic_setmode(ppc, chipset_mode); 671 672 return(chipset_mode); 673 } 674 return(-1); 675} 676 677/* 678 * ppc_smc37c66xgt_detect 679 * 680 * SMC FDC37C66xGT configuration. 681 */ 682static int 683ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 684{ 685 int s, i; 686 u_char r; 687 int type = -1; 688 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 689 690 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 691 692 693#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 694 695 /* 696 * Detection: enter configuration mode and read CRD register. 697 */ 698 699 s = splhigh(); 700 outb(csr, SMC665_iCODE); 701 outb(csr, SMC665_iCODE); 702 splx(s); 703 704 outb(csr, 0xd); 705 if (inb(cio) == 0x65) { 706 type = SMC_37C665GT; 707 goto config; 708 } 709 710 for (i = 0; i < 2; i++) { 711 s = splhigh(); 712 outb(csr, SMC666_iCODE); 713 outb(csr, SMC666_iCODE); 714 splx(s); 715 716 outb(csr, 0xd); 717 if (inb(cio) == 0x66) { 718 type = SMC_37C666GT; 719 break; 720 } 721 722 /* Another chance, CSR may be hard-configured to be at 0x370 */ 723 csr = SMC666_CSR; 724 } 725 726config: 727 /* 728 * If chipset not found, do not continue. 729 */ 730 if (type == -1) 731 return (-1); 732 733 /* select CR1 */ 734 outb(csr, 0x1); 735 736 /* read the port's address: bits 0 and 1 of CR1 */ 737 r = inb(cio) & SMC_CR1_ADDR; 738 if (port_address[(int)r] != ppc->ppc_base) 739 return (-1); 740 741 ppc->ppc_model = type; 742 743 /* 744 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 745 * If SPP mode is detected, try to set ECP+EPP mode 746 */ 747 748 if (bootverbose) { 749 outb(csr, 0x1); 750 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 751 inb(cio) & 0xff); 752 753 outb(csr, 0x4); 754 printf(" CR4=0x%x", inb(cio) & 0xff); 755 } 756 757 /* select CR1 */ 758 outb(csr, 0x1); 759 760 if (!chipset_mode) { 761 /* autodetect mode */ 762 763 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 764 if (type == SMC_37C666GT) { 765 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 766 if (bootverbose) 767 printf(" configuration hardwired, supposing " \ 768 "ECP+EPP SPP"); 769 770 } else 771 if ((inb(cio) & SMC_CR1_MODE) == 0) { 772 /* already in extended parallel port mode, read CR4 */ 773 outb(csr, 0x4); 774 r = (inb(cio) & SMC_CR4_EMODE); 775 776 switch (r) { 777 case SMC_SPP: 778 ppc->ppc_avm |= PPB_SPP; 779 if (bootverbose) 780 printf(" SPP"); 781 break; 782 783 case SMC_EPPSPP: 784 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 785 if (bootverbose) 786 printf(" EPP SPP"); 787 break; 788 789 case SMC_ECP: 790 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 791 if (bootverbose) 792 printf(" ECP SPP"); 793 break; 794 795 case SMC_ECPEPP: 796 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 797 if (bootverbose) 798 printf(" ECP+EPP SPP"); 799 break; 800 } 801 } else { 802 /* not an extended port mode */ 803 ppc->ppc_avm |= PPB_SPP; 804 if (bootverbose) 805 printf(" SPP"); 806 } 807 808 } else { 809 /* mode forced */ 810 ppc->ppc_avm = chipset_mode; 811 812 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 813 if (type == SMC_37C666GT) 814 goto end_detect; 815 816 r = inb(cio); 817 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 818 /* do not use ECP when the mode is not forced to */ 819 outb(cio, r | SMC_CR1_MODE); 820 if (bootverbose) 821 printf(" SPP"); 822 } else { 823 /* an extended mode is selected */ 824 outb(cio, r & ~SMC_CR1_MODE); 825 826 /* read CR4 register and reset mode field */ 827 outb(csr, 0x4); 828 r = inb(cio) & ~SMC_CR4_EMODE; 829 830 if (chipset_mode & PPB_ECP) { 831 if (chipset_mode & PPB_EPP) { 832 outb(cio, r | SMC_ECPEPP); 833 if (bootverbose) 834 printf(" ECP+EPP"); 835 } else { 836 outb(cio, r | SMC_ECP); 837 if (bootverbose) 838 printf(" ECP"); 839 } 840 } else { 841 /* PPB_EPP is set */ 842 outb(cio, r | SMC_EPPSPP); 843 if (bootverbose) 844 printf(" EPP SPP"); 845 } 846 } 847 ppc->ppc_avm = chipset_mode; 848 } 849 850 /* set FIFO threshold to 16 */ 851 if (ppc->ppc_avm & PPB_ECP) { 852 /* select CRA */ 853 outb(csr, 0xa); 854 outb(cio, 16); 855 } 856 857end_detect: 858 859 if (bootverbose) 860 printf ("\n"); 861 862 if (ppc->ppc_avm & PPB_EPP) { 863 /* select CR4 */ 864 outb(csr, 0x4); 865 r = inb(cio); 866 867 /* 868 * Set the EPP protocol... 869 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 870 */ 871 if (ppc->ppc_epp == EPP_1_9) 872 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 873 else 874 outb(cio, (r | SMC_CR4_EPPTYPE)); 875 } 876 877 /* end config mode */ 878 outb(csr, 0xaa); 879 880 ppc->ppc_type = PPC_TYPE_SMCLIKE; 881 ppc_smclike_setmode(ppc, chipset_mode); 882 883 return (chipset_mode); 884} 885 886/* 887 * SMC FDC37C935 configuration 888 * Found on many Alpha machines 889 */ 890static int 891ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 892{ 893 int s; 894 int type = -1; 895 896 s = splhigh(); 897 outb(SMC935_CFG, 0x55); /* enter config mode */ 898 outb(SMC935_CFG, 0x55); 899 splx(s); 900 901 outb(SMC935_IND, SMC935_ID); /* check device id */ 902 if (inb(SMC935_DAT) == 0x2) 903 type = SMC_37C935; 904 905 if (type == -1) { 906 outb(SMC935_CFG, 0xaa); /* exit config mode */ 907 return (-1); 908 } 909 910 ppc->ppc_model = type; 911 912 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 913 outb(SMC935_DAT, 3); /* which is logical device 3 */ 914 915 /* set io port base */ 916 outb(SMC935_IND, SMC935_PORTHI); 917 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 918 outb(SMC935_IND, SMC935_PORTLO); 919 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 920 921 if (!chipset_mode) 922 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 923 else { 924 ppc->ppc_avm = chipset_mode; 925 outb(SMC935_IND, SMC935_PPMODE); 926 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 927 928 /* SPP + EPP or just plain SPP */ 929 if (chipset_mode & (PPB_SPP)) { 930 if (chipset_mode & PPB_EPP) { 931 if (ppc->ppc_epp == EPP_1_9) { 932 outb(SMC935_IND, SMC935_PPMODE); 933 outb(SMC935_DAT, SMC935_EPP19SPP); 934 } 935 if (ppc->ppc_epp == EPP_1_7) { 936 outb(SMC935_IND, SMC935_PPMODE); 937 outb(SMC935_DAT, SMC935_EPP17SPP); 938 } 939 } else { 940 outb(SMC935_IND, SMC935_PPMODE); 941 outb(SMC935_DAT, SMC935_SPP); 942 } 943 } 944 945 /* ECP + EPP or just plain ECP */ 946 if (chipset_mode & PPB_ECP) { 947 if (chipset_mode & PPB_EPP) { 948 if (ppc->ppc_epp == EPP_1_9) { 949 outb(SMC935_IND, SMC935_PPMODE); 950 outb(SMC935_DAT, SMC935_ECPEPP19); 951 } 952 if (ppc->ppc_epp == EPP_1_7) { 953 outb(SMC935_IND, SMC935_PPMODE); 954 outb(SMC935_DAT, SMC935_ECPEPP17); 955 } 956 } else { 957 outb(SMC935_IND, SMC935_PPMODE); 958 outb(SMC935_DAT, SMC935_ECP); 959 } 960 } 961 } 962 963 outb(SMC935_CFG, 0xaa); /* exit config mode */ 964 965 ppc->ppc_type = PPC_TYPE_SMCLIKE; 966 ppc_smclike_setmode(ppc, chipset_mode); 967 968 return (chipset_mode); 969} 970 971/* 972 * Winbond W83877F stuff 973 * 974 * EFER: extended function enable register 975 * EFIR: extended function index register 976 * EFDR: extended function data register 977 */ 978#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 979#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 980 981static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 982static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 983static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 984static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 985 986static int 987ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 988{ 989 int i, j, efer; 990 unsigned char r, hefere, hefras; 991 992 for (i = 0; i < 4; i ++) { 993 /* first try to enable configuration registers */ 994 efer = w83877f_efers[i]; 995 996 /* write the key to the EFER */ 997 for (j = 0; j < w83877f_keyiter[i]; j ++) 998 outb (efer, w83877f_keys[i]); 999 1000 /* then check HEFERE and HEFRAS bits */ 1001 outb (efir, 0x0c); 1002 hefere = inb(efdr) & WINB_HEFERE; 1003 1004 outb (efir, 0x16); 1005 hefras = inb(efdr) & WINB_HEFRAS; 1006 1007 /* 1008 * HEFRAS HEFERE 1009 * 0 1 write 89h to 250h (power-on default) 1010 * 1 0 write 86h twice to 3f0h 1011 * 1 1 write 87h twice to 3f0h 1012 * 0 0 write 88h to 250h 1013 */ 1014 if ((hefere | hefras) == w83877f_hefs[i]) 1015 goto found; 1016 } 1017 1018 return (-1); /* failed */ 1019 1020found: 1021 /* check base port address - read from CR23 */ 1022 outb(efir, 0x23); 1023 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1024 return (-1); 1025 1026 /* read CHIP ID from CR9/bits0-3 */ 1027 outb(efir, 0x9); 1028 1029 switch (inb(efdr) & WINB_CHIPID) { 1030 case WINB_W83877F_ID: 1031 ppc->ppc_model = WINB_W83877F; 1032 break; 1033 1034 case WINB_W83877AF_ID: 1035 ppc->ppc_model = WINB_W83877AF; 1036 break; 1037 1038 default: 1039 ppc->ppc_model = WINB_UNKNOWN; 1040 } 1041 1042 if (bootverbose) { 1043 /* dump of registers */ 1044 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 1045 for (i = 0; i <= 0xd; i ++) { 1046 outb(efir, i); 1047 printf("0x%x ", inb(efdr)); 1048 } 1049 for (i = 0x10; i <= 0x17; i ++) { 1050 outb(efir, i); 1051 printf("0x%x ", inb(efdr)); 1052 } 1053 outb(efir, 0x1e); 1054 printf("0x%x ", inb(efdr)); 1055 for (i = 0x20; i <= 0x29; i ++) { 1056 outb(efir, i); 1057 printf("0x%x ", inb(efdr)); 1058 } 1059 printf("\n"); 1060 printf("ppc%d:", ppc->ppc_unit); 1061 } 1062 1063 ppc->ppc_type = PPC_TYPE_GENERIC; 1064 1065 if (!chipset_mode) { 1066 /* autodetect mode */ 1067 1068 /* select CR0 */ 1069 outb(efir, 0x0); 1070 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1071 1072 /* select CR9 */ 1073 outb(efir, 0x9); 1074 r |= (inb(efdr) & WINB_PRTMODS2); 1075 1076 switch (r) { 1077 case WINB_W83757: 1078 if (bootverbose) 1079 printf("ppc%d: W83757 compatible mode\n", 1080 ppc->ppc_unit); 1081 return (-1); /* generic or SMC-like */ 1082 1083 case WINB_EXTFDC: 1084 case WINB_EXTADP: 1085 case WINB_EXT2FDD: 1086 case WINB_JOYSTICK: 1087 if (bootverbose) 1088 printf(" not in parallel port mode\n"); 1089 return (-1); 1090 1091 case (WINB_PARALLEL | WINB_EPP_SPP): 1092 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1093 if (bootverbose) 1094 printf(" EPP SPP"); 1095 break; 1096 1097 case (WINB_PARALLEL | WINB_ECP): 1098 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1099 if (bootverbose) 1100 printf(" ECP SPP"); 1101 break; 1102 1103 case (WINB_PARALLEL | WINB_ECP_EPP): 1104 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1105 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1106 1107 if (bootverbose) 1108 printf(" ECP+EPP SPP"); 1109 break; 1110 default: 1111 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 1112 } 1113 1114 } else { 1115 /* mode forced */ 1116 1117 /* select CR9 and set PRTMODS2 bit */ 1118 outb(efir, 0x9); 1119 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1120 1121 /* select CR0 and reset PRTMODSx bits */ 1122 outb(efir, 0x0); 1123 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1124 1125 if (chipset_mode & PPB_ECP) { 1126 if (chipset_mode & PPB_EPP) { 1127 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1128 if (bootverbose) 1129 printf(" ECP+EPP"); 1130 1131 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1132 1133 } else { 1134 outb(efdr, inb(efdr) | WINB_ECP); 1135 if (bootverbose) 1136 printf(" ECP"); 1137 } 1138 } else { 1139 /* select EPP_SPP otherwise */ 1140 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1141 if (bootverbose) 1142 printf(" EPP SPP"); 1143 } 1144 ppc->ppc_avm = chipset_mode; 1145 } 1146 1147 if (bootverbose) 1148 printf("\n"); 1149 1150 /* exit configuration mode */ 1151 outb(efer, 0xaa); 1152 1153 switch (ppc->ppc_type) { 1154 case PPC_TYPE_SMCLIKE: 1155 ppc_smclike_setmode(ppc, chipset_mode); 1156 break; 1157 default: 1158 ppc_generic_setmode(ppc, chipset_mode); 1159 break; 1160 } 1161 1162 return (chipset_mode); 1163} 1164#endif 1165 1166/* 1167 * ppc_generic_detect 1168 */ 1169static int 1170ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1171{ 1172 /* default to generic */ 1173 ppc->ppc_type = PPC_TYPE_GENERIC; 1174 1175 if (bootverbose) 1176 printf("ppc%d:", ppc->ppc_unit); 1177 1178 if (!chipset_mode) { 1179 /* first, check for ECP */ 1180 w_ecr(ppc, PPC_ECR_PS2); 1181 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1182 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1183 if (bootverbose) 1184 printf(" ECP SPP"); 1185 1186 /* search for SMC style ECP+EPP mode */ 1187 w_ecr(ppc, PPC_ECR_EPP); 1188 } 1189 1190 /* try to reset EPP timeout bit */ 1191 if (ppc_check_epp_timeout(ppc)) { 1192 ppc->ppc_avm |= PPB_EPP; 1193 1194 if (ppc->ppc_avm & PPB_ECP) { 1195 /* SMC like chipset found */ 1196 ppc->ppc_model = SMC_LIKE; 1197 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1198 1199 if (bootverbose) 1200 printf(" ECP+EPP"); 1201 } else { 1202 if (bootverbose) 1203 printf(" EPP"); 1204 } 1205 } else { 1206 /* restore to standard mode */ 1207 w_ecr(ppc, PPC_ECR_STD); 1208 } 1209 1210 /* XXX try to detect NIBBLE and PS2 modes */ 1211 ppc->ppc_avm |= PPB_NIBBLE; 1212 1213 if (bootverbose) 1214 printf(" SPP"); 1215 1216 } else { 1217 ppc->ppc_avm = chipset_mode; 1218 } 1219 1220 if (bootverbose) 1221 printf("\n"); 1222 1223 switch (ppc->ppc_type) { 1224 case PPC_TYPE_SMCLIKE: 1225 ppc_smclike_setmode(ppc, chipset_mode); 1226 break; 1227 default: 1228 ppc_generic_setmode(ppc, chipset_mode); 1229 break; 1230 } 1231 1232 return (chipset_mode); 1233} 1234 1235/* 1236 * ppc_detect() 1237 * 1238 * mode is the mode suggested at boot 1239 */ 1240static int 1241ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1242 1243#ifdef PPC_PROBE_CHIPSET 1244 int i, mode; 1245 1246 /* list of supported chipsets */ 1247 int (*chipset_detect[])(struct ppc_data *, int) = { 1248 ppc_pc873xx_detect, 1249 ppc_smc37c66xgt_detect, 1250 ppc_w83877f_detect, 1251 ppc_smc37c935_detect, 1252 ppc_generic_detect, 1253 NULL 1254 }; 1255#endif 1256 1257 /* if can't find the port and mode not forced return error */ 1258 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1259 return (EIO); /* failed, port not present */ 1260 1261 /* assume centronics compatible mode is supported */ 1262 ppc->ppc_avm = PPB_COMPATIBLE; 1263 1264#ifdef PPC_PROBE_CHIPSET 1265 /* we have to differenciate available chipset modes, 1266 * chipset running modes and IEEE-1284 operating modes 1267 * 1268 * after detection, the port must support running in compatible mode 1269 */ 1270 if (ppc->ppc_flags & 0x40) { 1271 if (bootverbose) 1272 printf("ppc: chipset forced to generic\n"); 1273#endif 1274 1275 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1276 1277#ifdef PPC_PROBE_CHIPSET 1278 } else { 1279 for (i=0; chipset_detect[i] != NULL; i++) { 1280 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1281 ppc->ppc_mode = mode; 1282 break; 1283 } 1284 } 1285 } 1286#endif 1287 1288 /* configure/detect ECP FIFO */ 1289 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1290 ppc_detect_fifo(ppc); 1291 1292 return (0); 1293} 1294 1295/* 1296 * ppc_exec_microseq() 1297 * 1298 * Execute a microsequence. 1299 * Microsequence mechanism is supposed to handle fast I/O operations. 1300 */ 1301static int 1302ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1303{ 1304 struct ppc_data *ppc = DEVTOSOFTC(dev); 1305 struct ppb_microseq *mi; 1306 char cc, *p; 1307 int i, iter, len; 1308 int error; 1309 1310 register int reg; 1311 register char mask; 1312 register int accum = 0; 1313 register char *ptr = 0; 1314 1315 struct ppb_microseq *stack = 0; 1316 1317/* microsequence registers are equivalent to PC-like port registers */ 1318#define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1319#define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1320 1321#define INCR_PC (mi ++) /* increment program counter */ 1322 1323 mi = *p_msq; 1324 for (;;) { 1325 switch (mi->opcode) { 1326 case MS_OP_RSET: 1327 cc = r_reg(mi->arg[0].i, ppc); 1328 cc &= (char)mi->arg[2].i; /* clear mask */ 1329 cc |= (char)mi->arg[1].i; /* assert mask */ 1330 w_reg(mi->arg[0].i, ppc, cc); 1331 INCR_PC; 1332 break; 1333 1334 case MS_OP_RASSERT_P: 1335 reg = mi->arg[1].i; 1336 ptr = ppc->ppc_ptr; 1337 1338 if ((len = mi->arg[0].i) == MS_ACCUM) { 1339 accum = ppc->ppc_accum; 1340 for (; accum; accum--) 1341 w_reg(reg, ppc, *ptr++); 1342 ppc->ppc_accum = accum; 1343 } else 1344 for (i=0; i<len; i++) 1345 w_reg(reg, ppc, *ptr++); 1346 ppc->ppc_ptr = ptr; 1347 1348 INCR_PC; 1349 break; 1350 1351 case MS_OP_RFETCH_P: 1352 reg = mi->arg[1].i; 1353 mask = (char)mi->arg[2].i; 1354 ptr = ppc->ppc_ptr; 1355 1356 if ((len = mi->arg[0].i) == MS_ACCUM) { 1357 accum = ppc->ppc_accum; 1358 for (; accum; accum--) 1359 *ptr++ = r_reg(reg, ppc) & mask; 1360 ppc->ppc_accum = accum; 1361 } else 1362 for (i=0; i<len; i++) 1363 *ptr++ = r_reg(reg, ppc) & mask; 1364 ppc->ppc_ptr = ptr; 1365 1366 INCR_PC; 1367 break; 1368 1369 case MS_OP_RFETCH: 1370 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1371 (char)mi->arg[1].i; 1372 INCR_PC; 1373 break; 1374 1375 case MS_OP_RASSERT: 1376 case MS_OP_DELAY: 1377 1378 /* let's suppose the next instr. is the same */ 1379 prefetch: 1380 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1381 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1382 1383 if (mi->opcode == MS_OP_DELAY) { 1384 DELAY(mi->arg[0].i); 1385 INCR_PC; 1386 goto prefetch; 1387 } 1388 break; 1389 1390 case MS_OP_ADELAY: 1391 if (mi->arg[0].i) 1392 tsleep(NULL, PPBPRI, "ppbdelay", 1393 mi->arg[0].i * (hz/1000)); 1394 INCR_PC; 1395 break; 1396 1397 case MS_OP_TRIG: 1398 reg = mi->arg[0].i; 1399 iter = mi->arg[1].i; 1400 p = (char *)mi->arg[2].p; 1401 1402 /* XXX delay limited to 255 us */ 1403 for (i=0; i<iter; i++) { 1404 w_reg(reg, ppc, *p++); 1405 DELAY((unsigned char)*p++); 1406 } 1407 INCR_PC; 1408 break; 1409 1410 case MS_OP_SET: 1411 ppc->ppc_accum = mi->arg[0].i; 1412 INCR_PC; 1413 break; 1414 1415 case MS_OP_DBRA: 1416 if (--ppc->ppc_accum > 0) 1417 mi += mi->arg[0].i; 1418 INCR_PC; 1419 break; 1420 1421 case MS_OP_BRSET: 1422 cc = r_str(ppc); 1423 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1424 mi += mi->arg[1].i; 1425 INCR_PC; 1426 break; 1427 1428 case MS_OP_BRCLEAR: 1429 cc = r_str(ppc); 1430 if ((cc & (char)mi->arg[0].i) == 0) 1431 mi += mi->arg[1].i; 1432 INCR_PC; 1433 break; 1434 1435 case MS_OP_BRSTAT: 1436 cc = r_str(ppc); 1437 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1438 (char)mi->arg[0].i) 1439 mi += mi->arg[2].i; 1440 INCR_PC; 1441 break; 1442 1443 case MS_OP_C_CALL: 1444 /* 1445 * If the C call returns !0 then end the microseq. 1446 * The current state of ptr is passed to the C function 1447 */ 1448 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1449 return (error); 1450 1451 INCR_PC; 1452 break; 1453 1454 case MS_OP_PTR: 1455 ppc->ppc_ptr = (char *)mi->arg[0].p; 1456 INCR_PC; 1457 break; 1458 1459 case MS_OP_CALL: 1460 if (stack) 1461 panic("%s: too much calls", __FUNCTION__); 1462 1463 if (mi->arg[0].p) { 1464 /* store the state of the actual 1465 * microsequence 1466 */ 1467 stack = mi; 1468 1469 /* jump to the new microsequence */ 1470 mi = (struct ppb_microseq *)mi->arg[0].p; 1471 } else 1472 INCR_PC; 1473 1474 break; 1475 1476 case MS_OP_SUBRET: 1477 /* retrieve microseq and pc state before the call */ 1478 mi = stack; 1479 1480 /* reset the stack */ 1481 stack = 0; 1482 1483 /* XXX return code */ 1484 1485 INCR_PC; 1486 break; 1487 1488 case MS_OP_PUT: 1489 case MS_OP_GET: 1490 case MS_OP_RET: 1491 /* can't return to ppb level during the execution 1492 * of a submicrosequence */ 1493 if (stack) 1494 panic("%s: can't return to ppb level", 1495 __FUNCTION__); 1496 1497 /* update pc for ppb level of execution */ 1498 *p_msq = mi; 1499 1500 /* return to ppb level of execution */ 1501 return (0); 1502 1503 default: 1504 panic("%s: unknown microsequence opcode 0x%x", 1505 __FUNCTION__, mi->opcode); 1506 } 1507 } 1508 1509 /* unreached */ 1510} 1511 1512static void 1513ppcintr(void *arg) 1514{ 1515 device_t dev = (device_t)arg; 1516 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1517 u_char ctr, ecr, str; 1518 1519 str = r_str(ppc); 1520 ctr = r_ctr(ppc); 1521 ecr = r_ecr(ppc); 1522 1523#if PPC_DEBUG > 1 1524 printf("![%x/%x/%x]", ctr, ecr, str); 1525#endif 1526 1527 /* don't use ecp mode with IRQENABLE set */ 1528 if (ctr & IRQENABLE) { 1529 return; 1530 } 1531 1532 /* interrupts are generated by nFault signal 1533 * only in ECP mode */ 1534 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1535 /* check if ppc driver has programmed the 1536 * nFault interrupt */ 1537 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1538 1539 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1540 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1541 } else { 1542 /* shall be handled by underlying layers XXX */ 1543 return; 1544 } 1545 } 1546 1547 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1548 /* disable interrupts (should be done by hardware though) */ 1549 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1550 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1551 ecr = r_ecr(ppc); 1552 1553 /* check if DMA completed */ 1554 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1555#ifdef PPC_DEBUG 1556 printf("a"); 1557#endif 1558 /* stop DMA */ 1559 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1560 ecr = r_ecr(ppc); 1561 1562 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1563#ifdef PPC_DEBUG 1564 printf("d"); 1565#endif 1566 isa_dmadone( 1567 ppc->ppc_dmaflags, 1568 ppc->ppc_dmaddr, 1569 ppc->ppc_dmacnt, 1570 ppc->ppc_dmachan); 1571 1572 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1573 1574 /* wakeup the waiting process */ 1575 wakeup((caddr_t)ppc); 1576 } 1577 } 1578 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1579 1580 /* classic interrupt I/O */ 1581 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1582 } 1583 1584 return; 1585} 1586 1587static int 1588ppc_read(device_t dev, char *buf, int len, int mode) 1589{ 1590 return (EINVAL); 1591} 1592 1593/* 1594 * Call this function if you want to send data in any advanced mode 1595 * of your parallel port: FIFO, DMA 1596 * 1597 * If what you want is not possible (no ECP, no DMA...), 1598 * EINVAL is returned 1599 */ 1600static int 1601ppc_write(device_t dev, char *buf, int len, int how) 1602{ 1603 struct ppc_data *ppc = DEVTOSOFTC(dev); 1604 char ecr, ecr_sav, ctr, ctr_sav; 1605 int s, error = 0; 1606 int spin; 1607 1608#ifdef PPC_DEBUG 1609 printf("w"); 1610#endif 1611 1612 ecr_sav = r_ecr(ppc); 1613 ctr_sav = r_ctr(ppc); 1614 1615 /* 1616 * Send buffer with DMA, FIFO and interrupts 1617 */ 1618 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { 1619 1620 if (ppc->ppc_dmachan >= 0) { 1621 1622 /* byte mode, no intr, no DMA, dir=0, flush fifo 1623 */ 1624 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1625 w_ecr(ppc, ecr); 1626 1627 /* disable nAck interrupts */ 1628 ctr = r_ctr(ppc); 1629 ctr &= ~IRQENABLE; 1630 w_ctr(ppc, ctr); 1631 1632 ppc->ppc_dmaflags = 0; 1633 ppc->ppc_dmaddr = (caddr_t)buf; 1634 ppc->ppc_dmacnt = (u_int)len; 1635 1636 switch (ppc->ppc_mode) { 1637 case PPB_COMPATIBLE: 1638 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1639 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1640 break; 1641 case PPB_ECP: 1642 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1643 break; 1644 default: 1645 error = EINVAL; 1646 goto error; 1647 } 1648 1649 w_ecr(ppc, ecr); 1650 ecr = r_ecr(ppc); 1651 1652 /* enter splhigh() not to be preempted 1653 * by the dma interrupt, we may miss 1654 * the wakeup otherwise 1655 */ 1656 s = splhigh(); 1657 1658 ppc->ppc_dmastat = PPC_DMA_INIT; 1659 1660 /* enable interrupts */ 1661 ecr &= ~PPC_SERVICE_INTR; 1662 ppc->ppc_irqstat = PPC_IRQ_DMA; 1663 w_ecr(ppc, ecr); 1664 1665 isa_dmastart( 1666 ppc->ppc_dmaflags, 1667 ppc->ppc_dmaddr, 1668 ppc->ppc_dmacnt, 1669 ppc->ppc_dmachan); 1670#ifdef PPC_DEBUG 1671 printf("s%d", ppc->ppc_dmacnt); 1672#endif 1673 ppc->ppc_dmastat = PPC_DMA_STARTED; 1674 1675 /* Wait for the DMA completed interrupt. We hope we won't 1676 * miss it, otherwise a signal will be necessary to unlock the 1677 * process. 1678 */ 1679 do { 1680 /* release CPU */ 1681 error = tsleep((caddr_t)ppc, 1682 PPBPRI | PCATCH, "ppcdma", 0); 1683 1684 } while (error == EWOULDBLOCK); 1685 1686 splx(s); 1687 1688 if (error) { 1689#ifdef PPC_DEBUG 1690 printf("i"); 1691#endif 1692 /* stop DMA */ 1693 isa_dmadone( 1694 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1695 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1696 1697 /* no dma, no interrupt, flush the fifo */ 1698 w_ecr(ppc, PPC_ECR_RESET); 1699 1700 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1701 goto error; 1702 } 1703 1704 /* wait for an empty fifo */ 1705 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1706 1707 for (spin=100; spin; spin--) 1708 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1709 goto fifo_empty; 1710#ifdef PPC_DEBUG 1711 printf("Z"); 1712#endif 1713 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1714 if (error != EWOULDBLOCK) { 1715#ifdef PPC_DEBUG 1716 printf("I"); 1717#endif 1718 /* no dma, no interrupt, flush the fifo */ 1719 w_ecr(ppc, PPC_ECR_RESET); 1720 1721 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1722 error = EINTR; 1723 goto error; 1724 } 1725 } 1726 1727fifo_empty: 1728 /* no dma, no interrupt, flush the fifo */ 1729 w_ecr(ppc, PPC_ECR_RESET); 1730 1731 } else 1732 error = EINVAL; /* XXX we should FIFO and 1733 * interrupts */ 1734 } else 1735 error = EINVAL; 1736 1737error: 1738 1739 /* PDRQ must be kept unasserted until nPDACK is 1740 * deasserted for a minimum of 350ns (SMC datasheet) 1741 * 1742 * Consequence may be a FIFO that never empty 1743 */ 1744 DELAY(1); 1745 1746 w_ecr(ppc, ecr_sav); 1747 w_ctr(ppc, ctr_sav); 1748 1749 return (error); 1750} 1751 1752static void 1753ppc_reset_epp(device_t dev) 1754{ 1755 struct ppc_data *ppc = DEVTOSOFTC(dev); 1756 1757 ppc_reset_epp_timeout(ppc); 1758 1759 return; 1760} 1761 1762static int 1763ppc_setmode(device_t dev, int mode) 1764{ 1765 struct ppc_data *ppc = DEVTOSOFTC(dev); 1766 1767 switch (ppc->ppc_type) { 1768 case PPC_TYPE_SMCLIKE: 1769 return (ppc_smclike_setmode(ppc, mode)); 1770 break; 1771 1772 case PPC_TYPE_GENERIC: 1773 default: 1774 return (ppc_generic_setmode(ppc, mode)); 1775 break; 1776 } 1777 1778 /* not reached */ 1779 return (ENXIO); 1780} 1781 1782static struct isa_pnp_id lpc_ids[] = { 1783 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */ 1784 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */ 1785 { 0 } 1786}; 1787 1788static int 1789ppc_probe(device_t dev) 1790{ 1791#ifdef __i386__ 1792 static short next_bios_ppc = 0; 1793#endif 1794 struct ppc_data *ppc; 1795 device_t parent; 1796 int error; 1797 u_long port; 1798 1799 parent = device_get_parent(dev); 1800 1801 error = ISA_PNP_PROBE(parent, dev, lpc_ids); 1802 if (error == ENXIO) 1803 return (ENXIO); 1804 else if (error != 0) /* XXX shall be set after detection */ 1805 device_set_desc(dev, "Parallel port"); 1806 1807 /* 1808 * Allocate the ppc_data structure. 1809 */ 1810 ppc = DEVTOSOFTC(dev); 1811 bzero(ppc, sizeof(struct ppc_data)); 1812 1813 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; 1814 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; 1815 1816 /* retrieve ISA parameters */ 1817 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); 1818 1819#ifdef __i386__ 1820 /* 1821 * If port not specified, use bios list. 1822 */ 1823 if (error) { 1824 if((next_bios_ppc < BIOS_MAX_PPC) && 1825 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1826 port = *(BIOS_PORTS+next_bios_ppc++); 1827 if (bootverbose) 1828 device_printf(dev, "parallel port found at 0x%x\n", 1829 (int) port); 1830 } else { 1831 device_printf(dev, "parallel port not found.\n"); 1832 return ENXIO; 1833 } 1834 bus_set_resource(dev, SYS_RES_IOPORT, 0, port, 1835 IO_LPTSIZE_EXTENDED); 1836 } 1837#endif 1838#ifdef __alpha__ 1839 /* 1840 * There isn't a bios list on alpha. Put it in the usual place. 1841 */ 1842 if (error) { 1843 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, 1844 IO_LPTSIZE_NORMAL); 1845 } 1846#endif 1847 1848 /* IO port is mandatory */ 1849 1850 /* Try "extended" IO port range...*/ 1851 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1852 &ppc->rid_ioport, 0, ~0, 1853 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1854 1855 if (ppc->res_ioport != 0) { 1856 if (bootverbose) 1857 device_printf(dev, "using extended I/O port range\n"); 1858 } else { 1859 /* Failed? If so, then try the "normal" IO port range... */ 1860 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1861 &ppc->rid_ioport, 0, ~0, 1862 IO_LPTSIZE_NORMAL, 1863 RF_ACTIVE); 1864 if (ppc->res_ioport != 0) { 1865 if (bootverbose) 1866 device_printf(dev, "using normal I/O port range\n"); 1867 } else { 1868 device_printf(dev, "cannot reserve I/O port range\n"); 1869 goto error; 1870 } 1871 } 1872 1873 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1874 1875 ppc->ppc_flags = device_get_flags(dev); 1876 1877 if (!(ppc->ppc_flags & 0x20)) { 1878 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq, 1879 0ul, ~0ul, 1, RF_SHAREABLE); 1880 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq, 1881 0ul, ~0ul, 1, RF_ACTIVE); 1882 } 1883 1884 if (ppc->res_irq) 1885 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1886 if (ppc->res_drq) 1887 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1888 1889 ppc->ppc_unit = device_get_unit(dev); 1890 ppc->ppc_model = GENERIC; 1891 1892 ppc->ppc_mode = PPB_COMPATIBLE; 1893 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1894 1895 ppc->ppc_type = PPC_TYPE_GENERIC; 1896 1897 /* 1898 * Try to detect the chipset and its mode. 1899 */ 1900 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1901 goto error; 1902 1903 return (0); 1904 1905error: 1906 if (ppc->res_irq != 0) { 1907 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1908 ppc->res_irq); 1909 } 1910 if (ppc->res_ioport != 0) { 1911 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1912 ppc->res_ioport); 1913 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1914 ppc->res_ioport); 1915 } 1916 if (ppc->res_drq != 0) { 1917 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1918 ppc->res_drq); 1919 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1920 ppc->res_drq); 1921 } 1922 return (ENXIO); 1923} 1924 1925static int 1926ppc_attach(device_t dev) 1927{ 1928 struct ppc_data *ppc = DEVTOSOFTC(dev); 1929 1930 device_t ppbus; 1931 device_t parent = device_get_parent(dev); 1932 1933 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1934 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1935 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1936 ppc_epp_protocol[ppc->ppc_epp] : ""); 1937 1938 if (ppc->ppc_fifo) 1939 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1940 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1941 1942 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1943 /* acquire the DMA channel forever */ /* XXX */ 1944 isa_dma_acquire(ppc->ppc_dmachan); 1945 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1946 } 1947 1948 /* add ppbus as a child of this isa to parallel bridge */ 1949 ppbus = device_add_child(dev, "ppbus", -1); 1950 1951 /* 1952 * Probe the ppbus and attach devices found. 1953 */ 1954 device_probe_and_attach(ppbus); 1955 1956 /* register the ppc interrupt handler as default */ 1957 if (ppc->res_irq) { 1958 /* default to the tty mask for registration */ /* XXX */ 1959 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, 1960 ppcintr, dev, &ppc->intr_cookie) == 0) { 1961 1962 /* remember the ppcintr is registered */ 1963 ppc->ppc_registered = 1; 1964 } 1965 } 1966 1967 return (0); 1968} 1969 1970static u_char 1971ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1972{ 1973 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1974 switch (iop) { 1975 case PPB_OUTSB_EPP: 1976 outsb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1977 break; 1978 case PPB_OUTSW_EPP: 1979 outsw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1980 break; 1981 case PPB_OUTSL_EPP: 1982 outsl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1983 break; 1984 case PPB_INSB_EPP: 1985 insb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1986 break; 1987 case PPB_INSW_EPP: 1988 insw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1989 break; 1990 case PPB_INSL_EPP: 1991 insl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1992 break; 1993 case PPB_RDTR: 1994 return (r_dtr(ppc)); 1995 break; 1996 case PPB_RSTR: 1997 return (r_str(ppc)); 1998 break; 1999 case PPB_RCTR: 2000 return (r_ctr(ppc)); 2001 break; 2002 case PPB_REPP_A: 2003 return (r_epp_A(ppc)); 2004 break; 2005 case PPB_REPP_D: 2006 return (r_epp_D(ppc)); 2007 break; 2008 case PPB_RECR: 2009 return (r_ecr(ppc)); 2010 break; 2011 case PPB_RFIFO: 2012 return (r_fifo(ppc)); 2013 break; 2014 case PPB_WDTR: 2015 w_dtr(ppc, byte); 2016 break; 2017 case PPB_WSTR: 2018 w_str(ppc, byte); 2019 break; 2020 case PPB_WCTR: 2021 w_ctr(ppc, byte); 2022 break; 2023 case PPB_WEPP_A: 2024 w_epp_A(ppc, byte); 2025 break; 2026 case PPB_WEPP_D: 2027 w_epp_D(ppc, byte); 2028 break; 2029 case PPB_WECR: 2030 w_ecr(ppc, byte); 2031 break; 2032 case PPB_WFIFO: 2033 w_fifo(ppc, byte); 2034 break; 2035 default: 2036 panic("%s: unknown I/O operation", __FUNCTION__); 2037 break; 2038 } 2039 2040 return (0); /* not significative */ 2041} 2042 2043static int 2044ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 2045{ 2046 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 2047 2048 switch (index) { 2049 case PPC_IVAR_EPP_PROTO: 2050 *val = (u_long)ppc->ppc_epp; 2051 break; 2052 case PPC_IVAR_IRQ: 2053 *val = (u_long)ppc->ppc_irq; 2054 break; 2055 default: 2056 return (ENOENT); 2057 } 2058 2059 return (0); 2060} 2061 2062/* 2063 * Resource is useless here since ppbus devices' interrupt handlers are 2064 * multiplexed to the same resource initially allocated by ppc 2065 */ 2066static int 2067ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 2068 void (*ihand)(void *), void *arg, void **cookiep) 2069{ 2070 int error; 2071 struct ppc_data *ppc = DEVTOSOFTC(bus); 2072 2073 if (ppc->ppc_registered) { 2074 /* XXX refuse registration if DMA is in progress */ 2075 2076 /* first, unregister the default interrupt handler */ 2077 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 2078 bus, ppc->res_irq, ppc->intr_cookie))) 2079 return (error); 2080 2081/* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 2082/* ppc->res_irq); */ 2083 2084 /* DMA/FIFO operation won't be possible anymore */ 2085 ppc->ppc_registered = 0; 2086 } 2087 2088 /* pass registration to the upper layer, ignore the incoming resource */ 2089 return (BUS_SETUP_INTR(device_get_parent(bus), child, 2090 r, flags, ihand, arg, cookiep)); 2091} 2092 2093/* 2094 * When no underlying device has a registered interrupt, register the ppc 2095 * layer one 2096 */ 2097static int 2098ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 2099{ 2100 int error; 2101 struct ppc_data *ppc = DEVTOSOFTC(bus); 2102 device_t parent = device_get_parent(bus); 2103 2104 /* pass unregistration to the upper layer */ 2105 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 2106 return (error); 2107 2108 /* default to the tty mask for registration */ /* XXX */ 2109 if (ppc->ppc_irq && 2110 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 2111 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { 2112 2113 /* remember the ppcintr is registered */ 2114 ppc->ppc_registered = 1; 2115 } 2116 2117 return (error); 2118} 2119 2120DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); 2121