ppc.c revision 62061
1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/ppc/ppc.c 62061 2000-06-25 09:20:56Z dfr $ 27 * 28 */ 29 30#include "opt_ppc.h" 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/malloc.h> 37 38#include <vm/vm.h> 39#include <vm/pmap.h> 40#include <machine/clock.h> 41#include <machine/bus.h> 42#include <machine/resource.h> 43#include <machine/vmparam.h> 44#include <sys/rman.h> 45 46#include <isa/isareg.h> 47#include <isa/isavar.h> 48 49#include <dev/ppbus/ppbconf.h> 50#include <dev/ppbus/ppb_msq.h> 51 52#include <isa/ppcreg.h> 53 54#include "ppbus_if.h" 55 56#define LOG_PPC(function, ppc, string) \ 57 if (bootverbose) printf("%s: %s\n", function, string) 58 59 60#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 61 62devclass_t ppc_devclass; 63 64static int ppc_probe(device_t dev); 65static int ppc_attach(device_t dev); 66static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val); 67 68static void ppc_reset_epp(device_t); 69static void ppc_ecp_sync(device_t); 70static void ppcintr(void *arg); 71 72static int ppc_exec_microseq(device_t, struct ppb_microseq **); 73static int ppc_setmode(device_t, int); 74 75static int ppc_read(device_t, char *, int, int); 76static int ppc_write(device_t, char *, int, int); 77 78static u_char ppc_io(device_t, int, u_char *, int, u_char); 79 80static int ppc_setup_intr(device_t, device_t, struct resource *, int, 81 void (*)(void *), void *, void **); 82static int ppc_teardown_intr(device_t, device_t, struct resource *, void *); 83 84static device_method_t ppc_methods[] = { 85 /* device interface */ 86 DEVMETHOD(device_probe, ppc_probe), 87 DEVMETHOD(device_attach, ppc_attach), 88 89 /* bus interface */ 90 DEVMETHOD(bus_read_ivar, ppc_read_ivar), 91 DEVMETHOD(bus_setup_intr, ppc_setup_intr), 92 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), 93 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 94 95 /* ppbus interface */ 96 DEVMETHOD(ppbus_io, ppc_io), 97 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), 98 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), 99 DEVMETHOD(ppbus_setmode, ppc_setmode), 100 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), 101 DEVMETHOD(ppbus_read, ppc_read), 102 DEVMETHOD(ppbus_write, ppc_write), 103 104 { 0, 0 } 105 }; 106 107static driver_t ppc_driver = { 108 "ppc", 109 ppc_methods, 110 sizeof(struct ppc_data), 111}; 112 113static char *ppc_models[] = { 114 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 115 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0 116}; 117 118/* list of available modes */ 119static char *ppc_avms[] = { 120 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 121 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 122 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 123 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 124}; 125 126/* list of current executing modes 127 * Note that few modes do not actually exist. 128 */ 129static char *ppc_modes[] = { 130 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 131 "EPP", "EPP", "EPP", "ECP", 132 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 133 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 134}; 135 136static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 137 138#ifdef __i386__ 139/* 140 * BIOS printer list - used by BIOS probe. 141 */ 142#define BIOS_PPC_PORTS 0x408 143#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 144#define BIOS_MAX_PPC 4 145#endif 146 147/* 148 * ppc_ecp_sync() XXX 149 */ 150static void 151ppc_ecp_sync(device_t dev) { 152 153 int i, r; 154 struct ppc_data *ppc = DEVTOSOFTC(dev); 155 156 if (!(ppc->ppc_avm & PPB_ECP)) 157 return; 158 159 r = r_ecr(ppc); 160 if ((r & 0xe0) != PPC_ECR_EPP) 161 return; 162 163 for (i = 0; i < 100; i++) { 164 r = r_ecr(ppc); 165 if (r & 0x1) 166 return; 167 DELAY(100); 168 } 169 170 printf("ppc%d: ECP sync failed as data still " \ 171 "present in FIFO.\n", ppc->ppc_unit); 172 173 return; 174} 175 176/* 177 * ppc_detect_fifo() 178 * 179 * Detect parallel port FIFO 180 */ 181static int 182ppc_detect_fifo(struct ppc_data *ppc) 183{ 184 char ecr_sav; 185 char ctr_sav, ctr, cc; 186 short i; 187 188 /* save registers */ 189 ecr_sav = r_ecr(ppc); 190 ctr_sav = r_ctr(ppc); 191 192 /* enter ECP configuration mode, no interrupt, no DMA */ 193 w_ecr(ppc, 0xf4); 194 195 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 196 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 197 198 /* XXX 16 and 32 bits implementations not supported */ 199 if (ppc->ppc_pword != PPC_PWORD_8) { 200 LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 201 goto error; 202 } 203 204 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 205 ctr = r_ctr(ppc); 206 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 207 208 /* enter ECP test mode, no interrupt, no DMA */ 209 w_ecr(ppc, 0xd4); 210 211 /* flush the FIFO */ 212 for (i=0; i<1024; i++) { 213 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 214 break; 215 cc = r_fifo(ppc); 216 } 217 218 if (i >= 1024) { 219 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 220 goto error; 221 } 222 223 /* enable interrupts, no DMA */ 224 w_ecr(ppc, 0xd0); 225 226 /* determine readIntrThreshold 227 * fill the FIFO until serviceIntr is set 228 */ 229 for (i=0; i<1024; i++) { 230 w_fifo(ppc, (char)i); 231 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 232 /* readThreshold reached */ 233 ppc->ppc_rthr = i+1; 234 } 235 if (r_ecr(ppc) & PPC_FIFO_FULL) { 236 ppc->ppc_fifo = i+1; 237 break; 238 } 239 } 240 241 if (i >= 1024) { 242 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 243 goto error; 244 } 245 246 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 247 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 248 w_ecr(ppc, 0xd0); /* enable interrupts */ 249 250 /* determine writeIntrThreshold 251 * empty the FIFO until serviceIntr is set 252 */ 253 for (i=ppc->ppc_fifo; i>0; i--) { 254 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 255 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 256 goto error; 257 } 258 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 259 /* writeIntrThreshold reached */ 260 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 261 } 262 /* if FIFO empty before the last byte, error */ 263 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 264 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 265 goto error; 266 } 267 } 268 269 /* FIFO must be empty after the last byte */ 270 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 271 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 272 goto error; 273 } 274 275 w_ctr(ppc, ctr_sav); 276 w_ecr(ppc, ecr_sav); 277 278 return (0); 279 280error: 281 w_ctr(ppc, ctr_sav); 282 w_ecr(ppc, ecr_sav); 283 284 return (EINVAL); 285} 286 287static int 288ppc_detect_port(struct ppc_data *ppc) 289{ 290 291 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 292 w_dtr(ppc, 0xaa); 293 if (r_dtr(ppc) != 0xaa) 294 return (0); 295 296 return (1); 297} 298 299/* 300 * EPP timeout, according to the PC87332 manual 301 * Semantics of clearing EPP timeout bit. 302 * PC87332 - reading SPP_STR does it... 303 * SMC - write 1 to EPP timeout bit XXX 304 * Others - (?) write 0 to EPP timeout bit 305 */ 306static void 307ppc_reset_epp_timeout(struct ppc_data *ppc) 308{ 309 register char r; 310 311 r = r_str(ppc); 312 w_str(ppc, r | 0x1); 313 w_str(ppc, r & 0xfe); 314 315 return; 316} 317 318static int 319ppc_check_epp_timeout(struct ppc_data *ppc) 320{ 321 ppc_reset_epp_timeout(ppc); 322 323 return (!(r_str(ppc) & TIMEOUT)); 324} 325 326/* 327 * Configure current operating mode 328 */ 329static int 330ppc_generic_setmode(struct ppc_data *ppc, int mode) 331{ 332 u_char ecr = 0; 333 334 /* check if mode is available */ 335 if (mode && !(ppc->ppc_avm & mode)) 336 return (EINVAL); 337 338 /* if ECP mode, configure ecr register */ 339 if (ppc->ppc_avm & PPB_ECP) { 340 /* return to byte mode (keeping direction bit), 341 * no interrupt, no DMA to be able to change to 342 * ECP 343 */ 344 w_ecr(ppc, PPC_ECR_RESET); 345 ecr = PPC_DISABLE_INTR; 346 347 if (mode & PPB_EPP) 348 return (EINVAL); 349 else if (mode & PPB_ECP) 350 /* select ECP mode */ 351 ecr |= PPC_ECR_ECP; 352 else if (mode & PPB_PS2) 353 /* select PS2 mode with ECP */ 354 ecr |= PPC_ECR_PS2; 355 else 356 /* select COMPATIBLE/NIBBLE mode */ 357 ecr |= PPC_ECR_STD; 358 359 w_ecr(ppc, ecr); 360 } 361 362 ppc->ppc_mode = mode; 363 364 return (0); 365} 366 367/* 368 * The ppc driver is free to choose options like FIFO or DMA 369 * if ECP mode is available. 370 * 371 * The 'RAW' option allows the upper drivers to force the ppc mode 372 * even with FIFO, DMA available. 373 */ 374static int 375ppc_smclike_setmode(struct ppc_data *ppc, int mode) 376{ 377 u_char ecr = 0; 378 379 /* check if mode is available */ 380 if (mode && !(ppc->ppc_avm & mode)) 381 return (EINVAL); 382 383 /* if ECP mode, configure ecr register */ 384 if (ppc->ppc_avm & PPB_ECP) { 385 /* return to byte mode (keeping direction bit), 386 * no interrupt, no DMA to be able to change to 387 * ECP or EPP mode 388 */ 389 w_ecr(ppc, PPC_ECR_RESET); 390 ecr = PPC_DISABLE_INTR; 391 392 if (mode & PPB_EPP) 393 /* select EPP mode */ 394 ecr |= PPC_ECR_EPP; 395 else if (mode & PPB_ECP) 396 /* select ECP mode */ 397 ecr |= PPC_ECR_ECP; 398 else if (mode & PPB_PS2) 399 /* select PS2 mode with ECP */ 400 ecr |= PPC_ECR_PS2; 401 else 402 /* select COMPATIBLE/NIBBLE mode */ 403 ecr |= PPC_ECR_STD; 404 405 w_ecr(ppc, ecr); 406 } 407 408 ppc->ppc_mode = mode; 409 410 return (0); 411} 412 413#ifdef PPC_PROBE_CHIPSET 414/* 415 * ppc_pc873xx_detect 416 * 417 * Probe for a Natsemi PC873xx-family part. 418 * 419 * References in this function are to the National Semiconductor 420 * PC87332 datasheet TL/C/11930, May 1995 revision. 421 */ 422static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 423static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 424static int pc873xx_irqtab[] = {5, 7, 5, 0}; 425 426static int pc873xx_regstab[] = { 427 PC873_FER, PC873_FAR, PC873_PTR, 428 PC873_FCR, PC873_PCR, PC873_PMC, 429 PC873_TUP, PC873_SID, PC873_PNP0, 430 PC873_PNP1, PC873_LPTBA, -1 431}; 432 433static char *pc873xx_rnametab[] = { 434 "FER", "FAR", "PTR", "FCR", "PCR", 435 "PMC", "TUP", "SID", "PNP0", "PNP1", 436 "LPTBA", NULL 437}; 438 439static int 440ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 441{ 442 static int index = 0; 443 int idport, irq; 444 int ptr, pcr, val, i; 445 446 while ((idport = pc873xx_basetab[index++])) { 447 448 /* XXX should check first to see if this location is already claimed */ 449 450 /* 451 * Pull the 873xx through the power-on ID cycle (2.2,1.). 452 * We can't use this to locate the chip as it may already have 453 * been used by the BIOS. 454 */ 455 (void)inb(idport); (void)inb(idport); 456 (void)inb(idport); (void)inb(idport); 457 458 /* 459 * Read the SID byte. Possible values are : 460 * 461 * 01010xxx PC87334 462 * 0001xxxx PC87332 463 * 01110xxx PC87306 464 */ 465 outb(idport, PC873_SID); 466 val = inb(idport + 1); 467 if ((val & 0xf0) == 0x10) { 468 ppc->ppc_model = NS_PC87332; 469 } else if ((val & 0xf8) == 0x70) { 470 ppc->ppc_model = NS_PC87306; 471 } else if ((val & 0xf8) == 0x50) { 472 ppc->ppc_model = NS_PC87334; 473 } else { 474 if (bootverbose && (val != 0xff)) 475 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 476 continue ; /* not recognised */ 477 } 478 479 /* print registers */ 480 if (bootverbose) { 481 printf("PC873xx"); 482 for (i=0; pc873xx_regstab[i] != -1; i++) { 483 outb(idport, pc873xx_regstab[i]); 484 printf(" %s=0x%x", pc873xx_rnametab[i], 485 inb(idport + 1) & 0xff); 486 } 487 printf("\n"); 488 } 489 490 /* 491 * We think we have one. Is it enabled and where we want it to be? 492 */ 493 outb(idport, PC873_FER); 494 val = inb(idport + 1); 495 if (!(val & PC873_PPENABLE)) { 496 if (bootverbose) 497 printf("PC873xx parallel port disabled\n"); 498 continue; 499 } 500 outb(idport, PC873_FAR); 501 val = inb(idport + 1) & 0x3; 502 /* XXX we should create a driver instance for every port found */ 503 if (pc873xx_porttab[val] != ppc->ppc_base) { 504 if (bootverbose) 505 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 506 pc873xx_porttab[val], ppc->ppc_base); 507 continue; 508 } 509 510 outb(idport, PC873_PTR); 511 ptr = inb(idport + 1); 512 513 /* get irq settings */ 514 if (ppc->ppc_base == 0x378) 515 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 516 else 517 irq = pc873xx_irqtab[val]; 518 519 if (bootverbose) 520 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 521 522 /* 523 * Check if irq settings are correct 524 */ 525 if (irq != ppc->ppc_irq) { 526 /* 527 * If the chipset is not locked and base address is 0x378, 528 * we have another chance 529 */ 530 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 531 if (ppc->ppc_irq == 7) { 532 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 533 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 534 } else { 535 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 536 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 537 } 538 if (bootverbose) 539 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 540 } else { 541 if (bootverbose) 542 printf("PC873xx sorry, can't change irq setting\n"); 543 } 544 } else { 545 if (bootverbose) 546 printf("PC873xx irq settings are correct\n"); 547 } 548 549 outb(idport, PC873_PCR); 550 pcr = inb(idport + 1); 551 552 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 553 if (bootverbose) 554 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 555 556 ppc->ppc_avm |= PPB_NIBBLE; 557 if (bootverbose) 558 printf(", NIBBLE"); 559 560 if (pcr & PC873_EPPEN) { 561 ppc->ppc_avm |= PPB_EPP; 562 563 if (bootverbose) 564 printf(", EPP"); 565 566 if (pcr & PC873_EPP19) 567 ppc->ppc_epp = EPP_1_9; 568 else 569 ppc->ppc_epp = EPP_1_7; 570 571 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 572 outb(idport, PC873_PTR); 573 ptr = inb(idport + 1); 574 if (ptr & PC873_EPPRDIR) 575 printf(", Regular mode"); 576 else 577 printf(", Automatic mode"); 578 } 579 } else if (pcr & PC873_ECPEN) { 580 ppc->ppc_avm |= PPB_ECP; 581 if (bootverbose) 582 printf(", ECP"); 583 584 if (pcr & PC873_ECPCLK) { /* XXX */ 585 ppc->ppc_avm |= PPB_PS2; 586 if (bootverbose) 587 printf(", PS/2"); 588 } 589 } else { 590 outb(idport, PC873_PTR); 591 ptr = inb(idport + 1); 592 if (ptr & PC873_EXTENDED) { 593 ppc->ppc_avm |= PPB_SPP; 594 if (bootverbose) 595 printf(", SPP"); 596 } 597 } 598 } else { 599 if (bootverbose) 600 printf("PC873xx unlocked"); 601 602 if (chipset_mode & PPB_ECP) { 603 if ((chipset_mode & PPB_EPP) && bootverbose) 604 printf(", ECP+EPP not supported"); 605 606 pcr &= ~PC873_EPPEN; 607 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 608 outb(idport + 1, pcr); 609 outb(idport + 1, pcr); 610 611 if (bootverbose) 612 printf(", ECP"); 613 614 } else if (chipset_mode & PPB_EPP) { 615 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 616 pcr |= (PC873_EPPEN | PC873_EPP19); 617 outb(idport + 1, pcr); 618 outb(idport + 1, pcr); 619 620 ppc->ppc_epp = EPP_1_9; /* XXX */ 621 622 if (bootverbose) 623 printf(", EPP1.9"); 624 625 /* enable automatic direction turnover */ 626 if (ppc->ppc_model == NS_PC87332) { 627 outb(idport, PC873_PTR); 628 ptr = inb(idport + 1); 629 ptr &= ~PC873_EPPRDIR; 630 outb(idport + 1, ptr); 631 outb(idport + 1, ptr); 632 633 if (bootverbose) 634 printf(", Automatic mode"); 635 } 636 } else { 637 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 638 outb(idport + 1, pcr); 639 outb(idport + 1, pcr); 640 641 /* configure extended bit in PTR */ 642 outb(idport, PC873_PTR); 643 ptr = inb(idport + 1); 644 645 if (chipset_mode & PPB_PS2) { 646 ptr |= PC873_EXTENDED; 647 648 if (bootverbose) 649 printf(", PS/2"); 650 651 } else { 652 /* default to NIBBLE mode */ 653 ptr &= ~PC873_EXTENDED; 654 655 if (bootverbose) 656 printf(", NIBBLE"); 657 } 658 outb(idport + 1, ptr); 659 outb(idport + 1, ptr); 660 } 661 662 ppc->ppc_avm = chipset_mode; 663 } 664 665 if (bootverbose) 666 printf("\n"); 667 668 ppc->ppc_type = PPC_TYPE_GENERIC; 669 ppc_generic_setmode(ppc, chipset_mode); 670 671 return(chipset_mode); 672 } 673 return(-1); 674} 675 676/* 677 * ppc_smc37c66xgt_detect 678 * 679 * SMC FDC37C66xGT configuration. 680 */ 681static int 682ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 683{ 684 int s, i; 685 u_char r; 686 int type = -1; 687 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 688 689 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 690 691 692#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 693 694 /* 695 * Detection: enter configuration mode and read CRD register. 696 */ 697 698 s = splhigh(); 699 outb(csr, SMC665_iCODE); 700 outb(csr, SMC665_iCODE); 701 splx(s); 702 703 outb(csr, 0xd); 704 if (inb(cio) == 0x65) { 705 type = SMC_37C665GT; 706 goto config; 707 } 708 709 for (i = 0; i < 2; i++) { 710 s = splhigh(); 711 outb(csr, SMC666_iCODE); 712 outb(csr, SMC666_iCODE); 713 splx(s); 714 715 outb(csr, 0xd); 716 if (inb(cio) == 0x66) { 717 type = SMC_37C666GT; 718 break; 719 } 720 721 /* Another chance, CSR may be hard-configured to be at 0x370 */ 722 csr = SMC666_CSR; 723 } 724 725config: 726 /* 727 * If chipset not found, do not continue. 728 */ 729 if (type == -1) 730 return (-1); 731 732 /* select CR1 */ 733 outb(csr, 0x1); 734 735 /* read the port's address: bits 0 and 1 of CR1 */ 736 r = inb(cio) & SMC_CR1_ADDR; 737 if (port_address[(int)r] != ppc->ppc_base) 738 return (-1); 739 740 ppc->ppc_model = type; 741 742 /* 743 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 744 * If SPP mode is detected, try to set ECP+EPP mode 745 */ 746 747 if (bootverbose) { 748 outb(csr, 0x1); 749 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 750 inb(cio) & 0xff); 751 752 outb(csr, 0x4); 753 printf(" CR4=0x%x", inb(cio) & 0xff); 754 } 755 756 /* select CR1 */ 757 outb(csr, 0x1); 758 759 if (!chipset_mode) { 760 /* autodetect mode */ 761 762 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 763 if (type == SMC_37C666GT) { 764 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 765 if (bootverbose) 766 printf(" configuration hardwired, supposing " \ 767 "ECP+EPP SPP"); 768 769 } else 770 if ((inb(cio) & SMC_CR1_MODE) == 0) { 771 /* already in extended parallel port mode, read CR4 */ 772 outb(csr, 0x4); 773 r = (inb(cio) & SMC_CR4_EMODE); 774 775 switch (r) { 776 case SMC_SPP: 777 ppc->ppc_avm |= PPB_SPP; 778 if (bootverbose) 779 printf(" SPP"); 780 break; 781 782 case SMC_EPPSPP: 783 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 784 if (bootverbose) 785 printf(" EPP SPP"); 786 break; 787 788 case SMC_ECP: 789 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 790 if (bootverbose) 791 printf(" ECP SPP"); 792 break; 793 794 case SMC_ECPEPP: 795 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 796 if (bootverbose) 797 printf(" ECP+EPP SPP"); 798 break; 799 } 800 } else { 801 /* not an extended port mode */ 802 ppc->ppc_avm |= PPB_SPP; 803 if (bootverbose) 804 printf(" SPP"); 805 } 806 807 } else { 808 /* mode forced */ 809 ppc->ppc_avm = chipset_mode; 810 811 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 812 if (type == SMC_37C666GT) 813 goto end_detect; 814 815 r = inb(cio); 816 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 817 /* do not use ECP when the mode is not forced to */ 818 outb(cio, r | SMC_CR1_MODE); 819 if (bootverbose) 820 printf(" SPP"); 821 } else { 822 /* an extended mode is selected */ 823 outb(cio, r & ~SMC_CR1_MODE); 824 825 /* read CR4 register and reset mode field */ 826 outb(csr, 0x4); 827 r = inb(cio) & ~SMC_CR4_EMODE; 828 829 if (chipset_mode & PPB_ECP) { 830 if (chipset_mode & PPB_EPP) { 831 outb(cio, r | SMC_ECPEPP); 832 if (bootverbose) 833 printf(" ECP+EPP"); 834 } else { 835 outb(cio, r | SMC_ECP); 836 if (bootverbose) 837 printf(" ECP"); 838 } 839 } else { 840 /* PPB_EPP is set */ 841 outb(cio, r | SMC_EPPSPP); 842 if (bootverbose) 843 printf(" EPP SPP"); 844 } 845 } 846 ppc->ppc_avm = chipset_mode; 847 } 848 849 /* set FIFO threshold to 16 */ 850 if (ppc->ppc_avm & PPB_ECP) { 851 /* select CRA */ 852 outb(csr, 0xa); 853 outb(cio, 16); 854 } 855 856end_detect: 857 858 if (bootverbose) 859 printf ("\n"); 860 861 if (ppc->ppc_avm & PPB_EPP) { 862 /* select CR4 */ 863 outb(csr, 0x4); 864 r = inb(cio); 865 866 /* 867 * Set the EPP protocol... 868 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 869 */ 870 if (ppc->ppc_epp == EPP_1_9) 871 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 872 else 873 outb(cio, (r | SMC_CR4_EPPTYPE)); 874 } 875 876 /* end config mode */ 877 outb(csr, 0xaa); 878 879 ppc->ppc_type = PPC_TYPE_SMCLIKE; 880 ppc_smclike_setmode(ppc, chipset_mode); 881 882 return (chipset_mode); 883} 884 885/* 886 * Winbond W83877F stuff 887 * 888 * EFER: extended function enable register 889 * EFIR: extended function index register 890 * EFDR: extended function data register 891 */ 892#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 893#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 894 895static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 896static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 897static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 898static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 899 900static int 901ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 902{ 903 int i, j, efer; 904 unsigned char r, hefere, hefras; 905 906 for (i = 0; i < 4; i ++) { 907 /* first try to enable configuration registers */ 908 efer = w83877f_efers[i]; 909 910 /* write the key to the EFER */ 911 for (j = 0; j < w83877f_keyiter[i]; j ++) 912 outb (efer, w83877f_keys[i]); 913 914 /* then check HEFERE and HEFRAS bits */ 915 outb (efir, 0x0c); 916 hefere = inb(efdr) & WINB_HEFERE; 917 918 outb (efir, 0x16); 919 hefras = inb(efdr) & WINB_HEFRAS; 920 921 /* 922 * HEFRAS HEFERE 923 * 0 1 write 89h to 250h (power-on default) 924 * 1 0 write 86h twice to 3f0h 925 * 1 1 write 87h twice to 3f0h 926 * 0 0 write 88h to 250h 927 */ 928 if ((hefere | hefras) == w83877f_hefs[i]) 929 goto found; 930 } 931 932 return (-1); /* failed */ 933 934found: 935 /* check base port address - read from CR23 */ 936 outb(efir, 0x23); 937 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 938 return (-1); 939 940 /* read CHIP ID from CR9/bits0-3 */ 941 outb(efir, 0x9); 942 943 switch (inb(efdr) & WINB_CHIPID) { 944 case WINB_W83877F_ID: 945 ppc->ppc_model = WINB_W83877F; 946 break; 947 948 case WINB_W83877AF_ID: 949 ppc->ppc_model = WINB_W83877AF; 950 break; 951 952 default: 953 ppc->ppc_model = WINB_UNKNOWN; 954 } 955 956 if (bootverbose) { 957 /* dump of registers */ 958 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 959 for (i = 0; i <= 0xd; i ++) { 960 outb(efir, i); 961 printf("0x%x ", inb(efdr)); 962 } 963 for (i = 0x10; i <= 0x17; i ++) { 964 outb(efir, i); 965 printf("0x%x ", inb(efdr)); 966 } 967 outb(efir, 0x1e); 968 printf("0x%x ", inb(efdr)); 969 for (i = 0x20; i <= 0x29; i ++) { 970 outb(efir, i); 971 printf("0x%x ", inb(efdr)); 972 } 973 printf("\n"); 974 printf("ppc%d:", ppc->ppc_unit); 975 } 976 977 ppc->ppc_type = PPC_TYPE_GENERIC; 978 979 if (!chipset_mode) { 980 /* autodetect mode */ 981 982 /* select CR0 */ 983 outb(efir, 0x0); 984 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 985 986 /* select CR9 */ 987 outb(efir, 0x9); 988 r |= (inb(efdr) & WINB_PRTMODS2); 989 990 switch (r) { 991 case WINB_W83757: 992 if (bootverbose) 993 printf("ppc%d: W83757 compatible mode\n", 994 ppc->ppc_unit); 995 return (-1); /* generic or SMC-like */ 996 997 case WINB_EXTFDC: 998 case WINB_EXTADP: 999 case WINB_EXT2FDD: 1000 case WINB_JOYSTICK: 1001 if (bootverbose) 1002 printf(" not in parallel port mode\n"); 1003 return (-1); 1004 1005 case (WINB_PARALLEL | WINB_EPP_SPP): 1006 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1007 if (bootverbose) 1008 printf(" EPP SPP"); 1009 break; 1010 1011 case (WINB_PARALLEL | WINB_ECP): 1012 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1013 if (bootverbose) 1014 printf(" ECP SPP"); 1015 break; 1016 1017 case (WINB_PARALLEL | WINB_ECP_EPP): 1018 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1019 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1020 1021 if (bootverbose) 1022 printf(" ECP+EPP SPP"); 1023 break; 1024 default: 1025 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 1026 } 1027 1028 } else { 1029 /* mode forced */ 1030 1031 /* select CR9 and set PRTMODS2 bit */ 1032 outb(efir, 0x9); 1033 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1034 1035 /* select CR0 and reset PRTMODSx bits */ 1036 outb(efir, 0x0); 1037 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1038 1039 if (chipset_mode & PPB_ECP) { 1040 if (chipset_mode & PPB_EPP) { 1041 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1042 if (bootverbose) 1043 printf(" ECP+EPP"); 1044 1045 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1046 1047 } else { 1048 outb(efdr, inb(efdr) | WINB_ECP); 1049 if (bootverbose) 1050 printf(" ECP"); 1051 } 1052 } else { 1053 /* select EPP_SPP otherwise */ 1054 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1055 if (bootverbose) 1056 printf(" EPP SPP"); 1057 } 1058 ppc->ppc_avm = chipset_mode; 1059 } 1060 1061 if (bootverbose) 1062 printf("\n"); 1063 1064 /* exit configuration mode */ 1065 outb(efer, 0xaa); 1066 1067 switch (ppc->ppc_type) { 1068 case PPC_TYPE_SMCLIKE: 1069 ppc_smclike_setmode(ppc, chipset_mode); 1070 break; 1071 default: 1072 ppc_generic_setmode(ppc, chipset_mode); 1073 break; 1074 } 1075 1076 return (chipset_mode); 1077} 1078#endif 1079 1080/* 1081 * ppc_generic_detect 1082 */ 1083static int 1084ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1085{ 1086 /* default to generic */ 1087 ppc->ppc_type = PPC_TYPE_GENERIC; 1088 1089 if (bootverbose) 1090 printf("ppc%d:", ppc->ppc_unit); 1091 1092 if (!chipset_mode) { 1093 /* first, check for ECP */ 1094 w_ecr(ppc, PPC_ECR_PS2); 1095 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1096 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1097 if (bootverbose) 1098 printf(" ECP SPP"); 1099 1100 /* search for SMC style ECP+EPP mode */ 1101 w_ecr(ppc, PPC_ECR_EPP); 1102 } 1103 1104 /* try to reset EPP timeout bit */ 1105 if (ppc_check_epp_timeout(ppc)) { 1106 ppc->ppc_avm |= PPB_EPP; 1107 1108 if (ppc->ppc_avm & PPB_ECP) { 1109 /* SMC like chipset found */ 1110 ppc->ppc_model = SMC_LIKE; 1111 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1112 1113 if (bootverbose) 1114 printf(" ECP+EPP"); 1115 } else { 1116 if (bootverbose) 1117 printf(" EPP"); 1118 } 1119 } else { 1120 /* restore to standard mode */ 1121 w_ecr(ppc, PPC_ECR_STD); 1122 } 1123 1124 /* XXX try to detect NIBBLE and PS2 modes */ 1125 ppc->ppc_avm |= PPB_NIBBLE; 1126 1127 if (bootverbose) 1128 printf(" SPP"); 1129 1130 } else { 1131 ppc->ppc_avm = chipset_mode; 1132 } 1133 1134 if (bootverbose) 1135 printf("\n"); 1136 1137 switch (ppc->ppc_type) { 1138 case PPC_TYPE_SMCLIKE: 1139 ppc_smclike_setmode(ppc, chipset_mode); 1140 break; 1141 default: 1142 ppc_generic_setmode(ppc, chipset_mode); 1143 break; 1144 } 1145 1146 return (chipset_mode); 1147} 1148 1149/* 1150 * ppc_detect() 1151 * 1152 * mode is the mode suggested at boot 1153 */ 1154static int 1155ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1156 1157#ifdef PPC_PROBE_CHIPSET 1158 int i, mode; 1159 1160 /* list of supported chipsets */ 1161 int (*chipset_detect[])(struct ppc_data *, int) = { 1162 ppc_pc873xx_detect, 1163 ppc_smc37c66xgt_detect, 1164 ppc_w83877f_detect, 1165 ppc_generic_detect, 1166 NULL 1167 }; 1168#endif 1169 1170 /* if can't find the port and mode not forced return error */ 1171 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1172 return (EIO); /* failed, port not present */ 1173 1174 /* assume centronics compatible mode is supported */ 1175 ppc->ppc_avm = PPB_COMPATIBLE; 1176 1177#ifdef PPC_PROBE_CHIPSET 1178 /* we have to differenciate available chipset modes, 1179 * chipset running modes and IEEE-1284 operating modes 1180 * 1181 * after detection, the port must support running in compatible mode 1182 */ 1183 if (ppc->ppc_flags & 0x40) { 1184 if (bootverbose) 1185 printf("ppc: chipset forced to generic\n"); 1186#endif 1187 1188 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1189 1190#ifdef PPC_PROBE_CHIPSET 1191 } else { 1192 for (i=0; chipset_detect[i] != NULL; i++) { 1193 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1194 ppc->ppc_mode = mode; 1195 break; 1196 } 1197 } 1198 } 1199#endif 1200 1201 /* configure/detect ECP FIFO */ 1202 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1203 ppc_detect_fifo(ppc); 1204 1205 return (0); 1206} 1207 1208/* 1209 * ppc_exec_microseq() 1210 * 1211 * Execute a microsequence. 1212 * Microsequence mechanism is supposed to handle fast I/O operations. 1213 */ 1214static int 1215ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1216{ 1217 struct ppc_data *ppc = DEVTOSOFTC(dev); 1218 struct ppb_microseq *mi; 1219 char cc, *p; 1220 int i, iter, len; 1221 int error; 1222 1223 register int reg; 1224 register char mask; 1225 register int accum = 0; 1226 register char *ptr = 0; 1227 1228 struct ppb_microseq *stack = 0; 1229 1230/* microsequence registers are equivalent to PC-like port registers */ 1231#define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1232#define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1233 1234#define INCR_PC (mi ++) /* increment program counter */ 1235 1236 mi = *p_msq; 1237 for (;;) { 1238 switch (mi->opcode) { 1239 case MS_OP_RSET: 1240 cc = r_reg(mi->arg[0].i, ppc); 1241 cc &= (char)mi->arg[2].i; /* clear mask */ 1242 cc |= (char)mi->arg[1].i; /* assert mask */ 1243 w_reg(mi->arg[0].i, ppc, cc); 1244 INCR_PC; 1245 break; 1246 1247 case MS_OP_RASSERT_P: 1248 reg = mi->arg[1].i; 1249 ptr = ppc->ppc_ptr; 1250 1251 if ((len = mi->arg[0].i) == MS_ACCUM) { 1252 accum = ppc->ppc_accum; 1253 for (; accum; accum--) 1254 w_reg(reg, ppc, *ptr++); 1255 ppc->ppc_accum = accum; 1256 } else 1257 for (i=0; i<len; i++) 1258 w_reg(reg, ppc, *ptr++); 1259 ppc->ppc_ptr = ptr; 1260 1261 INCR_PC; 1262 break; 1263 1264 case MS_OP_RFETCH_P: 1265 reg = mi->arg[1].i; 1266 mask = (char)mi->arg[2].i; 1267 ptr = ppc->ppc_ptr; 1268 1269 if ((len = mi->arg[0].i) == MS_ACCUM) { 1270 accum = ppc->ppc_accum; 1271 for (; accum; accum--) 1272 *ptr++ = r_reg(reg, ppc) & mask; 1273 ppc->ppc_accum = accum; 1274 } else 1275 for (i=0; i<len; i++) 1276 *ptr++ = r_reg(reg, ppc) & mask; 1277 ppc->ppc_ptr = ptr; 1278 1279 INCR_PC; 1280 break; 1281 1282 case MS_OP_RFETCH: 1283 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1284 (char)mi->arg[1].i; 1285 INCR_PC; 1286 break; 1287 1288 case MS_OP_RASSERT: 1289 case MS_OP_DELAY: 1290 1291 /* let's suppose the next instr. is the same */ 1292 prefetch: 1293 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1294 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1295 1296 if (mi->opcode == MS_OP_DELAY) { 1297 DELAY(mi->arg[0].i); 1298 INCR_PC; 1299 goto prefetch; 1300 } 1301 break; 1302 1303 case MS_OP_ADELAY: 1304 if (mi->arg[0].i) 1305 tsleep(NULL, PPBPRI, "ppbdelay", 1306 mi->arg[0].i * (hz/1000)); 1307 INCR_PC; 1308 break; 1309 1310 case MS_OP_TRIG: 1311 reg = mi->arg[0].i; 1312 iter = mi->arg[1].i; 1313 p = (char *)mi->arg[2].p; 1314 1315 /* XXX delay limited to 255 us */ 1316 for (i=0; i<iter; i++) { 1317 w_reg(reg, ppc, *p++); 1318 DELAY((unsigned char)*p++); 1319 } 1320 INCR_PC; 1321 break; 1322 1323 case MS_OP_SET: 1324 ppc->ppc_accum = mi->arg[0].i; 1325 INCR_PC; 1326 break; 1327 1328 case MS_OP_DBRA: 1329 if (--ppc->ppc_accum > 0) 1330 mi += mi->arg[0].i; 1331 INCR_PC; 1332 break; 1333 1334 case MS_OP_BRSET: 1335 cc = r_str(ppc); 1336 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1337 mi += mi->arg[1].i; 1338 INCR_PC; 1339 break; 1340 1341 case MS_OP_BRCLEAR: 1342 cc = r_str(ppc); 1343 if ((cc & (char)mi->arg[0].i) == 0) 1344 mi += mi->arg[1].i; 1345 INCR_PC; 1346 break; 1347 1348 case MS_OP_BRSTAT: 1349 cc = r_str(ppc); 1350 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1351 (char)mi->arg[0].i) 1352 mi += mi->arg[2].i; 1353 INCR_PC; 1354 break; 1355 1356 case MS_OP_C_CALL: 1357 /* 1358 * If the C call returns !0 then end the microseq. 1359 * The current state of ptr is passed to the C function 1360 */ 1361 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1362 return (error); 1363 1364 INCR_PC; 1365 break; 1366 1367 case MS_OP_PTR: 1368 ppc->ppc_ptr = (char *)mi->arg[0].p; 1369 INCR_PC; 1370 break; 1371 1372 case MS_OP_CALL: 1373 if (stack) 1374 panic("%s: too much calls", __FUNCTION__); 1375 1376 if (mi->arg[0].p) { 1377 /* store the state of the actual 1378 * microsequence 1379 */ 1380 stack = mi; 1381 1382 /* jump to the new microsequence */ 1383 mi = (struct ppb_microseq *)mi->arg[0].p; 1384 } else 1385 INCR_PC; 1386 1387 break; 1388 1389 case MS_OP_SUBRET: 1390 /* retrieve microseq and pc state before the call */ 1391 mi = stack; 1392 1393 /* reset the stack */ 1394 stack = 0; 1395 1396 /* XXX return code */ 1397 1398 INCR_PC; 1399 break; 1400 1401 case MS_OP_PUT: 1402 case MS_OP_GET: 1403 case MS_OP_RET: 1404 /* can't return to ppb level during the execution 1405 * of a submicrosequence */ 1406 if (stack) 1407 panic("%s: can't return to ppb level", 1408 __FUNCTION__); 1409 1410 /* update pc for ppb level of execution */ 1411 *p_msq = mi; 1412 1413 /* return to ppb level of execution */ 1414 return (0); 1415 1416 default: 1417 panic("%s: unknown microsequence opcode 0x%x", 1418 __FUNCTION__, mi->opcode); 1419 } 1420 } 1421 1422 /* unreached */ 1423} 1424 1425static void 1426ppcintr(void *arg) 1427{ 1428 device_t dev = (device_t)arg; 1429 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1430 u_char ctr, ecr, str; 1431 1432 str = r_str(ppc); 1433 ctr = r_ctr(ppc); 1434 ecr = r_ecr(ppc); 1435 1436#if PPC_DEBUG > 1 1437 printf("![%x/%x/%x]", ctr, ecr, str); 1438#endif 1439 1440 /* don't use ecp mode with IRQENABLE set */ 1441 if (ctr & IRQENABLE) { 1442 return; 1443 } 1444 1445 /* interrupts are generated by nFault signal 1446 * only in ECP mode */ 1447 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1448 /* check if ppc driver has programmed the 1449 * nFault interrupt */ 1450 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1451 1452 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1453 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1454 } else { 1455 /* shall be handled by underlying layers XXX */ 1456 return; 1457 } 1458 } 1459 1460 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1461 /* disable interrupts (should be done by hardware though) */ 1462 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1463 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1464 ecr = r_ecr(ppc); 1465 1466 /* check if DMA completed */ 1467 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1468#ifdef PPC_DEBUG 1469 printf("a"); 1470#endif 1471 /* stop DMA */ 1472 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1473 ecr = r_ecr(ppc); 1474 1475 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1476#ifdef PPC_DEBUG 1477 printf("d"); 1478#endif 1479 isa_dmadone( 1480 ppc->ppc_dmaflags, 1481 ppc->ppc_dmaddr, 1482 ppc->ppc_dmacnt, 1483 ppc->ppc_dmachan); 1484 1485 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1486 1487 /* wakeup the waiting process */ 1488 wakeup((caddr_t)ppc); 1489 } 1490 } 1491 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1492 1493 /* classic interrupt I/O */ 1494 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1495 } 1496 1497 return; 1498} 1499 1500static int 1501ppc_read(device_t dev, char *buf, int len, int mode) 1502{ 1503 return (EINVAL); 1504} 1505 1506/* 1507 * Call this function if you want to send data in any advanced mode 1508 * of your parallel port: FIFO, DMA 1509 * 1510 * If what you want is not possible (no ECP, no DMA...), 1511 * EINVAL is returned 1512 */ 1513static int 1514ppc_write(device_t dev, char *buf, int len, int how) 1515{ 1516 struct ppc_data *ppc = DEVTOSOFTC(dev); 1517 char ecr, ecr_sav, ctr, ctr_sav; 1518 int s, error = 0; 1519 int spin; 1520 1521#ifdef PPC_DEBUG 1522 printf("w"); 1523#endif 1524 1525 ecr_sav = r_ecr(ppc); 1526 ctr_sav = r_ctr(ppc); 1527 1528 /* 1529 * Send buffer with DMA, FIFO and interrupts 1530 */ 1531 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { 1532 1533 if (ppc->ppc_dmachan >= 0) { 1534 1535 /* byte mode, no intr, no DMA, dir=0, flush fifo 1536 */ 1537 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1538 w_ecr(ppc, ecr); 1539 1540 /* disable nAck interrupts */ 1541 ctr = r_ctr(ppc); 1542 ctr &= ~IRQENABLE; 1543 w_ctr(ppc, ctr); 1544 1545 ppc->ppc_dmaflags = 0; 1546 ppc->ppc_dmaddr = (caddr_t)buf; 1547 ppc->ppc_dmacnt = (u_int)len; 1548 1549 switch (ppc->ppc_mode) { 1550 case PPB_COMPATIBLE: 1551 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1552 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1553 break; 1554 case PPB_ECP: 1555 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1556 break; 1557 default: 1558 error = EINVAL; 1559 goto error; 1560 } 1561 1562 w_ecr(ppc, ecr); 1563 ecr = r_ecr(ppc); 1564 1565 /* enter splhigh() not to be preempted 1566 * by the dma interrupt, we may miss 1567 * the wakeup otherwise 1568 */ 1569 s = splhigh(); 1570 1571 ppc->ppc_dmastat = PPC_DMA_INIT; 1572 1573 /* enable interrupts */ 1574 ecr &= ~PPC_SERVICE_INTR; 1575 ppc->ppc_irqstat = PPC_IRQ_DMA; 1576 w_ecr(ppc, ecr); 1577 1578 isa_dmastart( 1579 ppc->ppc_dmaflags, 1580 ppc->ppc_dmaddr, 1581 ppc->ppc_dmacnt, 1582 ppc->ppc_dmachan); 1583#ifdef PPC_DEBUG 1584 printf("s%d", ppc->ppc_dmacnt); 1585#endif 1586 ppc->ppc_dmastat = PPC_DMA_STARTED; 1587 1588 /* Wait for the DMA completed interrupt. We hope we won't 1589 * miss it, otherwise a signal will be necessary to unlock the 1590 * process. 1591 */ 1592 do { 1593 /* release CPU */ 1594 error = tsleep((caddr_t)ppc, 1595 PPBPRI | PCATCH, "ppcdma", 0); 1596 1597 } while (error == EWOULDBLOCK); 1598 1599 splx(s); 1600 1601 if (error) { 1602#ifdef PPC_DEBUG 1603 printf("i"); 1604#endif 1605 /* stop DMA */ 1606 isa_dmadone( 1607 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1608 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1609 1610 /* no dma, no interrupt, flush the fifo */ 1611 w_ecr(ppc, PPC_ECR_RESET); 1612 1613 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1614 goto error; 1615 } 1616 1617 /* wait for an empty fifo */ 1618 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1619 1620 for (spin=100; spin; spin--) 1621 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1622 goto fifo_empty; 1623#ifdef PPC_DEBUG 1624 printf("Z"); 1625#endif 1626 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1627 if (error != EWOULDBLOCK) { 1628#ifdef PPC_DEBUG 1629 printf("I"); 1630#endif 1631 /* no dma, no interrupt, flush the fifo */ 1632 w_ecr(ppc, PPC_ECR_RESET); 1633 1634 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1635 error = EINTR; 1636 goto error; 1637 } 1638 } 1639 1640fifo_empty: 1641 /* no dma, no interrupt, flush the fifo */ 1642 w_ecr(ppc, PPC_ECR_RESET); 1643 1644 } else 1645 error = EINVAL; /* XXX we should FIFO and 1646 * interrupts */ 1647 } else 1648 error = EINVAL; 1649 1650error: 1651 1652 /* PDRQ must be kept unasserted until nPDACK is 1653 * deasserted for a minimum of 350ns (SMC datasheet) 1654 * 1655 * Consequence may be a FIFO that never empty 1656 */ 1657 DELAY(1); 1658 1659 w_ecr(ppc, ecr_sav); 1660 w_ctr(ppc, ctr_sav); 1661 1662 return (error); 1663} 1664 1665static void 1666ppc_reset_epp(device_t dev) 1667{ 1668 struct ppc_data *ppc = DEVTOSOFTC(dev); 1669 1670 ppc_reset_epp_timeout(ppc); 1671 1672 return; 1673} 1674 1675static int 1676ppc_setmode(device_t dev, int mode) 1677{ 1678 struct ppc_data *ppc = DEVTOSOFTC(dev); 1679 1680 switch (ppc->ppc_type) { 1681 case PPC_TYPE_SMCLIKE: 1682 return (ppc_smclike_setmode(ppc, mode)); 1683 break; 1684 1685 case PPC_TYPE_GENERIC: 1686 default: 1687 return (ppc_generic_setmode(ppc, mode)); 1688 break; 1689 } 1690 1691 /* not reached */ 1692 return (ENXIO); 1693} 1694 1695static struct isa_pnp_id lpc_ids[] = { 1696 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */ 1697 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */ 1698 { 0 } 1699}; 1700 1701static int 1702ppc_probe(device_t dev) 1703{ 1704#ifdef __i386__ 1705 static short next_bios_ppc = 0; 1706#endif 1707 struct ppc_data *ppc; 1708 device_t parent; 1709 int error; 1710 u_long port; 1711 1712 parent = device_get_parent(dev); 1713 1714 error = ISA_PNP_PROBE(parent, dev, lpc_ids); 1715 if (error == ENXIO) 1716 return (ENXIO); 1717 else if (error != 0) /* XXX shall be set after detection */ 1718 device_set_desc(dev, "Parallel port"); 1719 1720 /* 1721 * Allocate the ppc_data structure. 1722 */ 1723 ppc = DEVTOSOFTC(dev); 1724 bzero(ppc, sizeof(struct ppc_data)); 1725 1726 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; 1727 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; 1728 1729 /* retrieve ISA parameters */ 1730 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); 1731 1732#ifdef __i386__ 1733 /* 1734 * If port not specified, use bios list. 1735 */ 1736 if (error) { 1737 if((next_bios_ppc < BIOS_MAX_PPC) && 1738 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1739 port = *(BIOS_PORTS+next_bios_ppc++); 1740 if (bootverbose) 1741 device_printf(dev, "parallel port found at 0x%x\n", 1742 (int) port); 1743 } else { 1744 device_printf(dev, "parallel port not found.\n"); 1745 return ENXIO; 1746 } 1747 bus_set_resource(dev, SYS_RES_IOPORT, 0, port, IO_LPTSIZE); 1748 } 1749#endif 1750#ifdef __alpha__ 1751 /* 1752 * There isn't a bios list on alpha. Put it in the usual place. 1753 */ 1754 if (error) { 1755 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, IO_LPTSIZE); 1756 } 1757#endif 1758 1759 /* IO port is mandatory */ 1760 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1761 &ppc->rid_ioport, 0, ~0, 1762 IO_LPTSIZE, RF_ACTIVE); 1763 if (ppc->res_ioport == 0) { 1764 device_printf(dev, "cannot reserve I/O port range\n"); 1765 goto error; 1766 } 1767 1768 /* Assume we support the extended IO range of some ppc chipsets...*/ 1769 1770 ppc->rid_extraio = 1; 1771 ppc->res_extraio = 1772 bus_alloc_resource(dev, 1773 SYS_RES_IOPORT, 1774 &ppc->rid_extraio, 1775 0, 1776 ~0, 1777 IO_LPTSIZE, 1778 RF_ACTIVE); 1779 1780 /* If we cannot reserve the extra ports for the extended IO range, 1781 indicate this with a non-threatening message (this is not an error, 1782 so don't treat it as such)... */ 1783 1784 if (ppc->res_extraio == 0) { 1785 1786 ppc->rid_extraio = 0; 1787 1788 if (bootverbose) 1789 device_printf(dev, 1790"This ppc chipset does not support the extended I/O port range...no problem\n"); 1791 } 1792 1793 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1794 1795 ppc->ppc_flags = device_get_flags(dev); 1796 1797 if (!(ppc->ppc_flags & 0x20)) { 1798 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq, 1799 0ul, ~0ul, 1, RF_SHAREABLE); 1800 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq, 1801 0ul, ~0ul, 1, RF_ACTIVE); 1802 } 1803 1804 if (ppc->res_irq) 1805 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1806 if (ppc->res_drq) 1807 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1808 1809 ppc->ppc_unit = device_get_unit(dev); 1810 ppc->ppc_model = GENERIC; 1811 1812 ppc->ppc_mode = PPB_COMPATIBLE; 1813 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1814 1815 ppc->ppc_type = PPC_TYPE_GENERIC; 1816 1817 /* 1818 * Try to detect the chipset and its mode. 1819 */ 1820 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1821 goto error; 1822 1823 return (0); 1824 1825error: 1826 if (ppc->res_irq != 0) { 1827 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1828 ppc->res_irq); 1829 } 1830 if (ppc->res_ioport != 0) { 1831 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1832 ppc->res_ioport); 1833 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1834 ppc->res_ioport); 1835 } 1836 if (ppc->res_drq != 0) { 1837 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1838 ppc->res_drq); 1839 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1840 ppc->res_drq); 1841 } 1842 return (ENXIO); 1843} 1844 1845static int 1846ppc_attach(device_t dev) 1847{ 1848 struct ppc_data *ppc = DEVTOSOFTC(dev); 1849 1850 device_t ppbus; 1851 device_t parent = device_get_parent(dev); 1852 1853 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1854 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1855 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1856 ppc_epp_protocol[ppc->ppc_epp] : ""); 1857 1858 if (ppc->ppc_fifo) 1859 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1860 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1861 1862 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1863 /* acquire the DMA channel forever */ /* XXX */ 1864 isa_dma_acquire(ppc->ppc_dmachan); 1865 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1866 } 1867 1868 /* add ppbus as a child of this isa to parallel bridge */ 1869 ppbus = device_add_child(dev, "ppbus", -1); 1870 1871 /* 1872 * Probe the ppbus and attach devices found. 1873 */ 1874 device_probe_and_attach(ppbus); 1875 1876 /* register the ppc interrupt handler as default */ 1877 if (ppc->res_irq) { 1878 /* default to the tty mask for registration */ /* XXX */ 1879 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, 1880 ppcintr, dev, &ppc->intr_cookie) == 0) { 1881 1882 /* remember the ppcintr is registered */ 1883 ppc->ppc_registered = 1; 1884 } 1885 } 1886 1887 return (0); 1888} 1889 1890static u_char 1891ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 1892{ 1893 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 1894 switch (iop) { 1895 case PPB_OUTSB_EPP: 1896 outsb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1897 break; 1898 case PPB_OUTSW_EPP: 1899 outsw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1900 break; 1901 case PPB_OUTSL_EPP: 1902 outsl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1903 break; 1904 case PPB_INSB_EPP: 1905 insb(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1906 break; 1907 case PPB_INSW_EPP: 1908 insw(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1909 break; 1910 case PPB_INSL_EPP: 1911 insl(ppc->ppc_base + PPC_EPP_DATA, addr, cnt); 1912 break; 1913 case PPB_RDTR: 1914 return (r_dtr(ppc)); 1915 break; 1916 case PPB_RSTR: 1917 return (r_str(ppc)); 1918 break; 1919 case PPB_RCTR: 1920 return (r_ctr(ppc)); 1921 break; 1922 case PPB_REPP_A: 1923 return (r_epp_A(ppc)); 1924 break; 1925 case PPB_REPP_D: 1926 return (r_epp_D(ppc)); 1927 break; 1928 case PPB_RECR: 1929 return (r_ecr(ppc)); 1930 break; 1931 case PPB_RFIFO: 1932 return (r_fifo(ppc)); 1933 break; 1934 case PPB_WDTR: 1935 w_dtr(ppc, byte); 1936 break; 1937 case PPB_WSTR: 1938 w_str(ppc, byte); 1939 break; 1940 case PPB_WCTR: 1941 w_ctr(ppc, byte); 1942 break; 1943 case PPB_WEPP_A: 1944 w_epp_A(ppc, byte); 1945 break; 1946 case PPB_WEPP_D: 1947 w_epp_D(ppc, byte); 1948 break; 1949 case PPB_WECR: 1950 w_ecr(ppc, byte); 1951 break; 1952 case PPB_WFIFO: 1953 w_fifo(ppc, byte); 1954 break; 1955 default: 1956 panic("%s: unknown I/O operation", __FUNCTION__); 1957 break; 1958 } 1959 1960 return (0); /* not significative */ 1961} 1962 1963static int 1964ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 1965{ 1966 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 1967 1968 switch (index) { 1969 case PPC_IVAR_EPP_PROTO: 1970 *val = (u_long)ppc->ppc_epp; 1971 break; 1972 case PPC_IVAR_IRQ: 1973 *val = (u_long)ppc->ppc_irq; 1974 break; 1975 default: 1976 return (ENOENT); 1977 } 1978 1979 return (0); 1980} 1981 1982/* 1983 * Resource is useless here since ppbus devices' interrupt handlers are 1984 * multiplexed to the same resource initially allocated by ppc 1985 */ 1986static int 1987ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 1988 void (*ihand)(void *), void *arg, void **cookiep) 1989{ 1990 int error; 1991 struct ppc_data *ppc = DEVTOSOFTC(bus); 1992 1993 if (ppc->ppc_registered) { 1994 /* XXX refuse registration if DMA is in progress */ 1995 1996 /* first, unregister the default interrupt handler */ 1997 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 1998 bus, ppc->res_irq, ppc->intr_cookie))) 1999 return (error); 2000 2001/* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 2002/* ppc->res_irq); */ 2003 2004 /* DMA/FIFO operation won't be possible anymore */ 2005 ppc->ppc_registered = 0; 2006 } 2007 2008 /* pass registration to the upper layer, ignore the incoming resource */ 2009 return (BUS_SETUP_INTR(device_get_parent(bus), child, 2010 r, flags, ihand, arg, cookiep)); 2011} 2012 2013/* 2014 * When no underlying device has a registered interrupt, register the ppc 2015 * layer one 2016 */ 2017static int 2018ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 2019{ 2020 int error; 2021 struct ppc_data *ppc = DEVTOSOFTC(bus); 2022 device_t parent = device_get_parent(bus); 2023 2024 /* pass unregistration to the upper layer */ 2025 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 2026 return (error); 2027 2028 /* default to the tty mask for registration */ /* XXX */ 2029 if (ppc->ppc_irq && 2030 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 2031 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { 2032 2033 /* remember the ppcintr is registered */ 2034 ppc->ppc_registered = 1; 2035 } 2036 2037 return (error); 2038} 2039 2040DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); 2041