ppc.c revision 50477
1/*- 2 * Copyright (c) 1997, 1998 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/ppc/ppc.c 50477 1999-08-28 01:08:13Z peter $ 27 * 28 */ 29#include "ppc.h" 30 31#if NPPC > 0 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/conf.h> 36#include <sys/malloc.h> 37#include <sys/kernel.h> 38 39#include <machine/clock.h> 40 41#include <vm/vm.h> 42#include <vm/vm_param.h> 43#include <vm/pmap.h> 44 45#include <i386/isa/isa_device.h> 46#include <i386/isa/isa.h> 47 48#include <dev/ppbus/ppbconf.h> 49#include <dev/ppbus/ppb_msq.h> 50 51#include <i386/isa/ppcreg.h> 52 53#include "opt_ppc.h" 54 55#define LOG_PPC(function, ppc, string) \ 56 if (bootverbose) printf("%s: %s\n", function, string) 57 58static int ppcprobe(struct isa_device *); 59static int ppcattach(struct isa_device *); 60 61struct isa_driver ppcdriver = { 62 ppcprobe, ppcattach, "ppc" 63}; 64 65static struct ppc_data *ppcdata[NPPC]; 66static int nppc = 0; 67 68static char *ppc_types[] = { 69 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 70 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0 71}; 72 73/* list of available modes */ 74static char *ppc_avms[] = { 75 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 76 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 77 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 78 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 79}; 80 81/* list of current executing modes 82 * Note that few modes do not actually exist. 83 */ 84static char *ppc_modes[] = { 85 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 86 "EPP", "EPP", "EPP", "ECP", 87 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 88 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 89}; 90 91static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 92 93/* 94 * BIOS printer list - used by BIOS probe. 95 */ 96#define BIOS_PPC_PORTS 0x408 97#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 98#define BIOS_MAX_PPC 4 99 100/* 101 * All these functions are default actions for IN/OUT operations. 102 * They may be redefined if needed. 103 */ 104static void ppc_outsb_epp(int unit, char *addr, int cnt) { 105 outsb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 106static void ppc_outsw_epp(int unit, char *addr, int cnt) { 107 outsw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 108static void ppc_outsl_epp(int unit, char *addr, int cnt) { 109 outsl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 110static void ppc_insb_epp(int unit, char *addr, int cnt) { 111 insb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 112static void ppc_insw_epp(int unit, char *addr, int cnt) { 113 insw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 114static void ppc_insl_epp(int unit, char *addr, int cnt) { 115 insl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 116 117static u_char ppc_rdtr(int unit) { return r_dtr(ppcdata[unit]); } 118static u_char ppc_rstr(int unit) { return r_str(ppcdata[unit]); } 119static u_char ppc_rctr(int unit) { return r_ctr(ppcdata[unit]); } 120static u_char ppc_repp_A(int unit) { return r_epp_A(ppcdata[unit]); } 121static u_char ppc_repp_D(int unit) { return r_epp_D(ppcdata[unit]); } 122static u_char ppc_recr(int unit) { return r_ecr(ppcdata[unit]); } 123static u_char ppc_rfifo(int unit) { return r_fifo(ppcdata[unit]); } 124 125static void ppc_wdtr(int unit, char byte) { w_dtr(ppcdata[unit], byte); } 126static void ppc_wstr(int unit, char byte) { w_str(ppcdata[unit], byte); } 127static void ppc_wctr(int unit, char byte) { w_ctr(ppcdata[unit], byte); } 128static void ppc_wepp_A(int unit, char byte) { w_epp_A(ppcdata[unit], byte); } 129static void ppc_wepp_D(int unit, char byte) { w_epp_D(ppcdata[unit], byte); } 130static void ppc_wecr(int unit, char byte) { w_ecr(ppcdata[unit], byte); } 131static void ppc_wfifo(int unit, char byte) { w_fifo(ppcdata[unit], byte); } 132 133static void ppc_reset_epp_timeout(int); 134static void ppc_ecp_sync(int); 135static ointhand2_t ppcintr; 136 137static int ppc_exec_microseq(int, struct ppb_microseq **); 138static int ppc_generic_setmode(int, int); 139static int ppc_smclike_setmode(int, int); 140 141static int ppc_read(int, char *, int, int); 142static int ppc_write(int, char *, int, int); 143 144static struct ppb_adapter ppc_smclike_adapter = { 145 146 0, /* no intr handler, filled by chipset dependent code */ 147 148 ppc_reset_epp_timeout, ppc_ecp_sync, 149 150 ppc_exec_microseq, 151 152 ppc_smclike_setmode, ppc_read, ppc_write, 153 154 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 155 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 156 157 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo, 158 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo 159}; 160 161static struct ppb_adapter ppc_generic_adapter = { 162 163 0, /* no intr handler, filled by chipset dependent code */ 164 165 ppc_reset_epp_timeout, ppc_ecp_sync, 166 167 ppc_exec_microseq, 168 169 ppc_generic_setmode, ppc_read, ppc_write, 170 171 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 172 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 173 174 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo, 175 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo 176}; 177 178/* 179 * ppc_ecp_sync() XXX 180 */ 181static void 182ppc_ecp_sync(int unit) { 183 184 struct ppc_data *ppc = ppcdata[unit]; 185 int i, r; 186 187 if (!(ppc->ppc_avm & PPB_ECP)) 188 return; 189 190 r = r_ecr(ppc); 191 if ((r & 0xe0) != PPC_ECR_EPP) 192 return; 193 194 for (i = 0; i < 100; i++) { 195 r = r_ecr(ppc); 196 if (r & 0x1) 197 return; 198 DELAY(100); 199 } 200 201 printf("ppc%d: ECP sync failed as data still " \ 202 "present in FIFO.\n", unit); 203 204 return; 205} 206 207/* 208 * ppc_detect_fifo() 209 * 210 * Detect parallel port FIFO 211 */ 212static int 213ppc_detect_fifo(struct ppc_data *ppc) 214{ 215 char ecr_sav; 216 char ctr_sav, ctr, cc; 217 short i; 218 219 /* save registers */ 220 ecr_sav = r_ecr(ppc); 221 ctr_sav = r_ctr(ppc); 222 223 /* enter ECP configuration mode, no interrupt, no DMA */ 224 w_ecr(ppc, 0xf4); 225 226 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 227 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 228 229 /* XXX 16 and 32 bits implementations not supported */ 230 if (ppc->ppc_pword != PPC_PWORD_8) { 231 LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 232 goto error; 233 } 234 235 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 236 ctr = r_ctr(ppc); 237 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 238 239 /* enter ECP test mode, no interrupt, no DMA */ 240 w_ecr(ppc, 0xd4); 241 242 /* flush the FIFO */ 243 for (i=0; i<1024; i++) { 244 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 245 break; 246 cc = r_fifo(ppc); 247 } 248 249 if (i >= 1024) { 250 LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 251 goto error; 252 } 253 254 /* enable interrupts, no DMA */ 255 w_ecr(ppc, 0xd0); 256 257 /* determine readIntrThreshold 258 * fill the FIFO until serviceIntr is set 259 */ 260 for (i=0; i<1024; i++) { 261 w_fifo(ppc, (char)i); 262 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 263 /* readThreshold reached */ 264 ppc->ppc_rthr = i+1; 265 } 266 if (r_ecr(ppc) & PPC_FIFO_FULL) { 267 ppc->ppc_fifo = i+1; 268 break; 269 } 270 } 271 272 if (i >= 1024) { 273 LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 274 goto error; 275 } 276 277 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 278 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 279 w_ecr(ppc, 0xd0); /* enable interrupts */ 280 281 /* determine writeIntrThreshold 282 * empty the FIFO until serviceIntr is set 283 */ 284 for (i=ppc->ppc_fifo; i>0; i--) { 285 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 286 LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 287 goto error; 288 } 289 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 290 /* writeIntrThreshold reached */ 291 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 292 } 293 /* if FIFO empty before the last byte, error */ 294 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 295 LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 296 goto error; 297 } 298 } 299 300 /* FIFO must be empty after the last byte */ 301 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 302 LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 303 goto error; 304 } 305 306 w_ctr(ppc, ctr_sav); 307 w_ecr(ppc, ecr_sav); 308 309 return (0); 310 311error: 312 w_ctr(ppc, ctr_sav); 313 w_ecr(ppc, ecr_sav); 314 315 return (EINVAL); 316} 317 318static int 319ppc_detect_port(struct ppc_data *ppc) 320{ 321 322 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 323 w_dtr(ppc, 0xaa); 324 if (r_dtr(ppc) != 0xaa) 325 return (0); 326 327 return (1); 328} 329 330/* 331 * ppc_pc873xx_detect 332 * 333 * Probe for a Natsemi PC873xx-family part. 334 * 335 * References in this function are to the National Semiconductor 336 * PC87332 datasheet TL/C/11930, May 1995 revision. 337 */ 338static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 339static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 340static int pc873xx_irqtab[] = {5, 7, 5, 0}; 341 342static int pc873xx_regstab[] = { 343 PC873_FER, PC873_FAR, PC873_PTR, 344 PC873_FCR, PC873_PCR, PC873_PMC, 345 PC873_TUP, PC873_SID, PC873_PNP0, 346 PC873_PNP1, PC873_LPTBA, -1 347}; 348 349static char *pc873xx_rnametab[] = { 350 "FER", "FAR", "PTR", "FCR", "PCR", 351 "PMC", "TUP", "SID", "PNP0", "PNP1", 352 "LPTBA", NULL 353}; 354 355static int 356ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 357{ 358 static int index = 0; 359 int idport, irq; 360 int ptr, pcr, val, i; 361 362 while ((idport = pc873xx_basetab[index++])) { 363 364 /* XXX should check first to see if this location is already claimed */ 365 366 /* 367 * Pull the 873xx through the power-on ID cycle (2.2,1.). 368 * We can't use this to locate the chip as it may already have 369 * been used by the BIOS. 370 */ 371 (void)inb(idport); (void)inb(idport); 372 (void)inb(idport); (void)inb(idport); 373 374 /* 375 * Read the SID byte. Possible values are : 376 * 377 * 01010xxx PC87334 378 * 0001xxxx PC87332 379 * 01110xxx PC87306 380 */ 381 outb(idport, PC873_SID); 382 val = inb(idport + 1); 383 if ((val & 0xf0) == 0x10) { 384 ppc->ppc_type = NS_PC87332; 385 } else if ((val & 0xf8) == 0x70) { 386 ppc->ppc_type = NS_PC87306; 387 } else if ((val & 0xf8) == 0x50) { 388 ppc->ppc_type = NS_PC87334; 389 } else { 390 if (bootverbose && (val != 0xff)) 391 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 392 continue ; /* not recognised */ 393 } 394 395 /* print registers */ 396 if (bootverbose) { 397 printf("PC873xx"); 398 for (i=0; pc873xx_regstab[i] != -1; i++) { 399 outb(idport, pc873xx_regstab[i]); 400 printf(" %s=0x%x", pc873xx_rnametab[i], 401 inb(idport + 1) & 0xff); 402 } 403 printf("\n"); 404 } 405 406 /* 407 * We think we have one. Is it enabled and where we want it to be? 408 */ 409 outb(idport, PC873_FER); 410 val = inb(idport + 1); 411 if (!(val & PC873_PPENABLE)) { 412 if (bootverbose) 413 printf("PC873xx parallel port disabled\n"); 414 continue; 415 } 416 outb(idport, PC873_FAR); 417 val = inb(idport + 1) & 0x3; 418 /* XXX we should create a driver instance for every port found */ 419 if (pc873xx_porttab[val] != ppc->ppc_base) { 420 if (bootverbose) 421 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 422 pc873xx_porttab[val], ppc->ppc_base); 423 continue; 424 } 425 426 outb(idport, PC873_PTR); 427 ptr = inb(idport + 1); 428 429 /* get irq settings */ 430 if (ppc->ppc_base == 0x378) 431 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 432 else 433 irq = pc873xx_irqtab[val]; 434 435 if (bootverbose) 436 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 437 438 /* 439 * Check if irq settings are correct 440 */ 441 if (irq != ppc->ppc_irq) { 442 /* 443 * If the chipset is not locked and base address is 0x378, 444 * we have another chance 445 */ 446 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 447 if (ppc->ppc_irq == 7) { 448 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 449 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 450 } else { 451 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 452 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 453 } 454 if (bootverbose) 455 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 456 } else { 457 if (bootverbose) 458 printf("PC873xx sorry, can't change irq setting\n"); 459 } 460 } else { 461 if (bootverbose) 462 printf("PC873xx irq settings are correct\n"); 463 } 464 465 outb(idport, PC873_PCR); 466 pcr = inb(idport + 1); 467 468 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 469 if (bootverbose) 470 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 471 472 ppc->ppc_avm |= PPB_NIBBLE; 473 if (bootverbose) 474 printf(", NIBBLE"); 475 476 if (pcr & PC873_EPPEN) { 477 ppc->ppc_avm |= PPB_EPP; 478 479 if (bootverbose) 480 printf(", EPP"); 481 482 if (pcr & PC873_EPP19) 483 ppc->ppc_epp = EPP_1_9; 484 else 485 ppc->ppc_epp = EPP_1_7; 486 487 if ((ppc->ppc_type == NS_PC87332) && bootverbose) { 488 outb(idport, PC873_PTR); 489 ptr = inb(idport + 1); 490 if (ptr & PC873_EPPRDIR) 491 printf(", Regular mode"); 492 else 493 printf(", Automatic mode"); 494 } 495 } else if (pcr & PC873_ECPEN) { 496 ppc->ppc_avm |= PPB_ECP; 497 if (bootverbose) 498 printf(", ECP"); 499 500 if (pcr & PC873_ECPCLK) { /* XXX */ 501 ppc->ppc_avm |= PPB_PS2; 502 if (bootverbose) 503 printf(", PS/2"); 504 } 505 } else { 506 outb(idport, PC873_PTR); 507 ptr = inb(idport + 1); 508 if (ptr & PC873_EXTENDED) { 509 ppc->ppc_avm |= PPB_SPP; 510 if (bootverbose) 511 printf(", SPP"); 512 } 513 } 514 } else { 515 if (bootverbose) 516 printf("PC873xx unlocked"); 517 518 if (chipset_mode & PPB_ECP) { 519 if ((chipset_mode & PPB_EPP) && bootverbose) 520 printf(", ECP+EPP not supported"); 521 522 pcr &= ~PC873_EPPEN; 523 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 524 outb(idport + 1, pcr); 525 outb(idport + 1, pcr); 526 527 if (bootverbose) 528 printf(", ECP"); 529 530 } else if (chipset_mode & PPB_EPP) { 531 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 532 pcr |= (PC873_EPPEN | PC873_EPP19); 533 outb(idport + 1, pcr); 534 outb(idport + 1, pcr); 535 536 ppc->ppc_epp = EPP_1_9; /* XXX */ 537 538 if (bootverbose) 539 printf(", EPP1.9"); 540 541 /* enable automatic direction turnover */ 542 if (ppc->ppc_type == NS_PC87332) { 543 outb(idport, PC873_PTR); 544 ptr = inb(idport + 1); 545 ptr &= ~PC873_EPPRDIR; 546 outb(idport + 1, ptr); 547 outb(idport + 1, ptr); 548 549 if (bootverbose) 550 printf(", Automatic mode"); 551 } 552 } else { 553 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 554 outb(idport + 1, pcr); 555 outb(idport + 1, pcr); 556 557 /* configure extended bit in PTR */ 558 outb(idport, PC873_PTR); 559 ptr = inb(idport + 1); 560 561 if (chipset_mode & PPB_PS2) { 562 ptr |= PC873_EXTENDED; 563 564 if (bootverbose) 565 printf(", PS/2"); 566 567 } else { 568 /* default to NIBBLE mode */ 569 ptr &= ~PC873_EXTENDED; 570 571 if (bootverbose) 572 printf(", NIBBLE"); 573 } 574 outb(idport + 1, ptr); 575 outb(idport + 1, ptr); 576 } 577 578 ppc->ppc_avm = chipset_mode; 579 } 580 581 if (bootverbose) 582 printf("\n"); 583 584 ppc->ppc_link.adapter = &ppc_generic_adapter; 585 ppc_generic_setmode(ppc->ppc_unit, chipset_mode); 586 587 return(chipset_mode); 588 } 589 return(-1); 590} 591 592static int 593ppc_check_epp_timeout(struct ppc_data *ppc) 594{ 595 ppc_reset_epp_timeout(ppc->ppc_unit); 596 597 return (!(r_str(ppc) & TIMEOUT)); 598} 599 600/* 601 * ppc_smc37c66xgt_detect 602 * 603 * SMC FDC37C66xGT configuration. 604 */ 605static int 606ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 607{ 608 int s, i; 609 u_char r; 610 int type = -1; 611 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 612 613 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 614 615 616#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 617 618 /* 619 * Detection: enter configuration mode and read CRD register. 620 */ 621 622 s = splhigh(); 623 outb(csr, SMC665_iCODE); 624 outb(csr, SMC665_iCODE); 625 splx(s); 626 627 outb(csr, 0xd); 628 if (inb(cio) == 0x65) { 629 type = SMC_37C665GT; 630 goto config; 631 } 632 633 for (i = 0; i < 2; i++) { 634 s = splhigh(); 635 outb(csr, SMC666_iCODE); 636 outb(csr, SMC666_iCODE); 637 splx(s); 638 639 outb(csr, 0xd); 640 if (inb(cio) == 0x66) { 641 type = SMC_37C666GT; 642 break; 643 } 644 645 /* Another chance, CSR may be hard-configured to be at 0x370 */ 646 csr = SMC666_CSR; 647 } 648 649config: 650 /* 651 * If chipset not found, do not continue. 652 */ 653 if (type == -1) 654 return (-1); 655 656 /* select CR1 */ 657 outb(csr, 0x1); 658 659 /* read the port's address: bits 0 and 1 of CR1 */ 660 r = inb(cio) & SMC_CR1_ADDR; 661 if (port_address[(int)r] != ppc->ppc_base) 662 return (-1); 663 664 ppc->ppc_type = type; 665 666 /* 667 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 668 * If SPP mode is detected, try to set ECP+EPP mode 669 */ 670 671 if (bootverbose) { 672 outb(csr, 0x1); 673 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 674 inb(cio) & 0xff); 675 676 outb(csr, 0x4); 677 printf(" CR4=0x%x", inb(cio) & 0xff); 678 } 679 680 /* select CR1 */ 681 outb(csr, 0x1); 682 683 if (!chipset_mode) { 684 /* autodetect mode */ 685 686 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 687 if (type == SMC_37C666GT) { 688 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 689 if (bootverbose) 690 printf(" configuration hardwired, supposing " \ 691 "ECP+EPP SPP"); 692 693 } else 694 if ((inb(cio) & SMC_CR1_MODE) == 0) { 695 /* already in extended parallel port mode, read CR4 */ 696 outb(csr, 0x4); 697 r = (inb(cio) & SMC_CR4_EMODE); 698 699 switch (r) { 700 case SMC_SPP: 701 ppc->ppc_avm |= PPB_SPP; 702 if (bootverbose) 703 printf(" SPP"); 704 break; 705 706 case SMC_EPPSPP: 707 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 708 if (bootverbose) 709 printf(" EPP SPP"); 710 break; 711 712 case SMC_ECP: 713 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 714 if (bootverbose) 715 printf(" ECP SPP"); 716 break; 717 718 case SMC_ECPEPP: 719 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 720 if (bootverbose) 721 printf(" ECP+EPP SPP"); 722 break; 723 } 724 } else { 725 /* not an extended port mode */ 726 ppc->ppc_avm |= PPB_SPP; 727 if (bootverbose) 728 printf(" SPP"); 729 } 730 731 } else { 732 /* mode forced */ 733 ppc->ppc_avm = chipset_mode; 734 735 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 736 if (type == SMC_37C666GT) 737 goto end_detect; 738 739 r = inb(cio); 740 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 741 /* do not use ECP when the mode is not forced to */ 742 outb(cio, r | SMC_CR1_MODE); 743 if (bootverbose) 744 printf(" SPP"); 745 } else { 746 /* an extended mode is selected */ 747 outb(cio, r & ~SMC_CR1_MODE); 748 749 /* read CR4 register and reset mode field */ 750 outb(csr, 0x4); 751 r = inb(cio) & ~SMC_CR4_EMODE; 752 753 if (chipset_mode & PPB_ECP) { 754 if (chipset_mode & PPB_EPP) { 755 outb(cio, r | SMC_ECPEPP); 756 if (bootverbose) 757 printf(" ECP+EPP"); 758 } else { 759 outb(cio, r | SMC_ECP); 760 if (bootverbose) 761 printf(" ECP"); 762 } 763 } else { 764 /* PPB_EPP is set */ 765 outb(cio, r | SMC_EPPSPP); 766 if (bootverbose) 767 printf(" EPP SPP"); 768 } 769 } 770 ppc->ppc_avm = chipset_mode; 771 } 772 773 /* set FIFO threshold to 16 */ 774 if (ppc->ppc_avm & PPB_ECP) { 775 /* select CRA */ 776 outb(csr, 0xa); 777 outb(cio, 16); 778 } 779 780end_detect: 781 782 if (bootverbose) 783 printf ("\n"); 784 785 if (ppc->ppc_avm & PPB_EPP) { 786 /* select CR4 */ 787 outb(csr, 0x4); 788 r = inb(cio); 789 790 /* 791 * Set the EPP protocol... 792 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 793 */ 794 if (ppc->ppc_epp == EPP_1_9) 795 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 796 else 797 outb(cio, (r | SMC_CR4_EPPTYPE)); 798 } 799 800 /* end config mode */ 801 outb(csr, 0xaa); 802 803 ppc->ppc_link.adapter = &ppc_smclike_adapter; 804 ppc_smclike_setmode(ppc->ppc_unit, chipset_mode); 805 806 return (chipset_mode); 807} 808 809/* 810 * Winbond W83877F stuff 811 * 812 * EFER: extended function enable register 813 * EFIR: extended function index register 814 * EFDR: extended function data register 815 */ 816#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 817#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 818 819static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 820static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 821static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 822static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 823 824static int 825ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 826{ 827 int i, j, efer; 828 unsigned char r, hefere, hefras; 829 830 for (i = 0; i < 4; i ++) { 831 /* first try to enable configuration registers */ 832 efer = w83877f_efers[i]; 833 834 /* write the key to the EFER */ 835 for (j = 0; j < w83877f_keyiter[i]; j ++) 836 outb (efer, w83877f_keys[i]); 837 838 /* then check HEFERE and HEFRAS bits */ 839 outb (efir, 0x0c); 840 hefere = inb(efdr) & WINB_HEFERE; 841 842 outb (efir, 0x16); 843 hefras = inb(efdr) & WINB_HEFRAS; 844 845 /* 846 * HEFRAS HEFERE 847 * 0 1 write 89h to 250h (power-on default) 848 * 1 0 write 86h twice to 3f0h 849 * 1 1 write 87h twice to 3f0h 850 * 0 0 write 88h to 250h 851 */ 852 if ((hefere | hefras) == w83877f_hefs[i]) 853 goto found; 854 } 855 856 return (-1); /* failed */ 857 858found: 859 /* check base port address - read from CR23 */ 860 outb(efir, 0x23); 861 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 862 return (-1); 863 864 /* read CHIP ID from CR9/bits0-3 */ 865 outb(efir, 0x9); 866 867 switch (inb(efdr) & WINB_CHIPID) { 868 case WINB_W83877F_ID: 869 ppc->ppc_type = WINB_W83877F; 870 break; 871 872 case WINB_W83877AF_ID: 873 ppc->ppc_type = WINB_W83877AF; 874 break; 875 876 default: 877 ppc->ppc_type = WINB_UNKNOWN; 878 } 879 880 if (bootverbose) { 881 /* dump of registers */ 882 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 883 for (i = 0; i <= 0xd; i ++) { 884 outb(efir, i); 885 printf("0x%x ", inb(efdr)); 886 } 887 for (i = 0x10; i <= 0x17; i ++) { 888 outb(efir, i); 889 printf("0x%x ", inb(efdr)); 890 } 891 outb(efir, 0x1e); 892 printf("0x%x ", inb(efdr)); 893 for (i = 0x20; i <= 0x29; i ++) { 894 outb(efir, i); 895 printf("0x%x ", inb(efdr)); 896 } 897 printf("\n"); 898 printf("ppc%d:", ppc->ppc_unit); 899 } 900 901 ppc->ppc_link.adapter = &ppc_generic_adapter; 902 903 if (!chipset_mode) { 904 /* autodetect mode */ 905 906 /* select CR0 */ 907 outb(efir, 0x0); 908 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 909 910 /* select CR9 */ 911 outb(efir, 0x9); 912 r |= (inb(efdr) & WINB_PRTMODS2); 913 914 switch (r) { 915 case WINB_W83757: 916 if (bootverbose) 917 printf("ppc%d: W83757 compatible mode\n", 918 ppc->ppc_unit); 919 return (-1); /* generic or SMC-like */ 920 921 case WINB_EXTFDC: 922 case WINB_EXTADP: 923 case WINB_EXT2FDD: 924 case WINB_JOYSTICK: 925 if (bootverbose) 926 printf(" not in parallel port mode\n"); 927 return (-1); 928 929 case (WINB_PARALLEL | WINB_EPP_SPP): 930 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 931 if (bootverbose) 932 printf(" EPP SPP"); 933 break; 934 935 case (WINB_PARALLEL | WINB_ECP): 936 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 937 if (bootverbose) 938 printf(" ECP SPP"); 939 break; 940 941 case (WINB_PARALLEL | WINB_ECP_EPP): 942 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 943 ppc->ppc_link.adapter = &ppc_smclike_adapter; 944 945 if (bootverbose) 946 printf(" ECP+EPP SPP"); 947 break; 948 default: 949 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 950 } 951 952 } else { 953 /* mode forced */ 954 955 /* select CR9 and set PRTMODS2 bit */ 956 outb(efir, 0x9); 957 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 958 959 /* select CR0 and reset PRTMODSx bits */ 960 outb(efir, 0x0); 961 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 962 963 if (chipset_mode & PPB_ECP) { 964 if (chipset_mode & PPB_EPP) { 965 outb(efdr, inb(efdr) | WINB_ECP_EPP); 966 if (bootverbose) 967 printf(" ECP+EPP"); 968 969 ppc->ppc_link.adapter = &ppc_smclike_adapter; 970 971 } else { 972 outb(efdr, inb(efdr) | WINB_ECP); 973 if (bootverbose) 974 printf(" ECP"); 975 } 976 } else { 977 /* select EPP_SPP otherwise */ 978 outb(efdr, inb(efdr) | WINB_EPP_SPP); 979 if (bootverbose) 980 printf(" EPP SPP"); 981 } 982 ppc->ppc_avm = chipset_mode; 983 } 984 985 if (bootverbose) 986 printf("\n"); 987 988 /* exit configuration mode */ 989 outb(efer, 0xaa); 990 991 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 992 993 return (chipset_mode); 994} 995 996/* 997 * ppc_generic_detect 998 */ 999static int 1000ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1001{ 1002 /* default to generic */ 1003 ppc->ppc_link.adapter = &ppc_generic_adapter; 1004 1005 if (bootverbose) 1006 printf("ppc%d:", ppc->ppc_unit); 1007 1008 if (!chipset_mode) { 1009 /* first, check for ECP */ 1010 w_ecr(ppc, PPC_ECR_PS2); 1011 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1012 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1013 if (bootverbose) 1014 printf(" ECP SPP"); 1015 1016 /* search for SMC style ECP+EPP mode */ 1017 w_ecr(ppc, PPC_ECR_EPP); 1018 } 1019 1020 /* try to reset EPP timeout bit */ 1021 if (ppc_check_epp_timeout(ppc)) { 1022 ppc->ppc_avm |= PPB_EPP; 1023 1024 if (ppc->ppc_avm & PPB_ECP) { 1025 /* SMC like chipset found */ 1026 ppc->ppc_type = SMC_LIKE; 1027 ppc->ppc_link.adapter = &ppc_smclike_adapter; 1028 1029 if (bootverbose) 1030 printf(" ECP+EPP"); 1031 } else { 1032 if (bootverbose) 1033 printf(" EPP"); 1034 } 1035 } else { 1036 /* restore to standard mode */ 1037 w_ecr(ppc, PPC_ECR_STD); 1038 } 1039 1040 /* XXX try to detect NIBBLE and PS2 modes */ 1041 ppc->ppc_avm |= PPB_NIBBLE; 1042 1043 if (bootverbose) 1044 printf(" SPP"); 1045 1046 } else { 1047 ppc->ppc_avm = chipset_mode; 1048 } 1049 1050 if (bootverbose) 1051 printf("\n"); 1052 1053 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 1054 1055 return (chipset_mode); 1056} 1057 1058/* 1059 * ppc_detect() 1060 * 1061 * mode is the mode suggested at boot 1062 */ 1063static int 1064ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1065 1066 int i, mode; 1067 1068 /* list of supported chipsets */ 1069 int (*chipset_detect[])(struct ppc_data *, int) = { 1070 ppc_pc873xx_detect, 1071 ppc_smc37c66xgt_detect, 1072 ppc_w83877f_detect, 1073 ppc_generic_detect, 1074 NULL 1075 }; 1076 1077 /* if can't find the port and mode not forced return error */ 1078 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1079 return (EIO); /* failed, port not present */ 1080 1081 /* assume centronics compatible mode is supported */ 1082 ppc->ppc_avm = PPB_COMPATIBLE; 1083 1084 /* we have to differenciate available chipset modes, 1085 * chipset running modes and IEEE-1284 operating modes 1086 * 1087 * after detection, the port must support running in compatible mode 1088 */ 1089 if (ppc->ppc_flags & 0x40) { 1090 if (bootverbose) 1091 printf("ppc: chipset forced to generic\n"); 1092 1093 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1094 1095 } else { 1096 for (i=0; chipset_detect[i] != NULL; i++) { 1097 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1098 ppc->ppc_mode = mode; 1099 break; 1100 } 1101 } 1102 } 1103 1104 /* configure/detect ECP FIFO */ 1105 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1106 ppc_detect_fifo(ppc); 1107 1108 return (0); 1109} 1110 1111/* 1112 * ppc_exec_microseq() 1113 * 1114 * Execute a microsequence. 1115 * Microsequence mechanism is supposed to handle fast I/O operations. 1116 */ 1117static int 1118ppc_exec_microseq(int unit, struct ppb_microseq **p_msq) 1119{ 1120 struct ppc_data *ppc = ppcdata[unit]; 1121 struct ppb_microseq *mi; 1122 char cc, *p; 1123 int i, iter, len; 1124 int error; 1125 1126 register int reg; 1127 register char mask; 1128 register int accum = 0; 1129 register char *ptr = 0; 1130 1131 struct ppb_microseq *stack = 0; 1132 1133/* microsequence registers are equivalent to PC-like port registers */ 1134#define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1135#define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1136 1137#define INCR_PC (mi ++) /* increment program counter */ 1138 1139 mi = *p_msq; 1140 for (;;) { 1141 switch (mi->opcode) { 1142 case MS_OP_RSET: 1143 cc = r_reg(mi->arg[0].i, ppc); 1144 cc &= (char)mi->arg[2].i; /* clear mask */ 1145 cc |= (char)mi->arg[1].i; /* assert mask */ 1146 w_reg(mi->arg[0].i, ppc, cc); 1147 INCR_PC; 1148 break; 1149 1150 case MS_OP_RASSERT_P: 1151 reg = mi->arg[1].i; 1152 ptr = ppc->ppc_ptr; 1153 1154 if ((len = mi->arg[0].i) == MS_ACCUM) { 1155 accum = ppc->ppc_accum; 1156 for (; accum; accum--) 1157 w_reg(reg, ppc, *ptr++); 1158 ppc->ppc_accum = accum; 1159 } else 1160 for (i=0; i<len; i++) 1161 w_reg(reg, ppc, *ptr++); 1162 ppc->ppc_ptr = ptr; 1163 1164 INCR_PC; 1165 break; 1166 1167 case MS_OP_RFETCH_P: 1168 reg = mi->arg[1].i; 1169 mask = (char)mi->arg[2].i; 1170 ptr = ppc->ppc_ptr; 1171 1172 if ((len = mi->arg[0].i) == MS_ACCUM) { 1173 accum = ppc->ppc_accum; 1174 for (; accum; accum--) 1175 *ptr++ = r_reg(reg, ppc) & mask; 1176 ppc->ppc_accum = accum; 1177 } else 1178 for (i=0; i<len; i++) 1179 *ptr++ = r_reg(reg, ppc) & mask; 1180 ppc->ppc_ptr = ptr; 1181 1182 INCR_PC; 1183 break; 1184 1185 case MS_OP_RFETCH: 1186 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1187 (char)mi->arg[1].i; 1188 INCR_PC; 1189 break; 1190 1191 case MS_OP_RASSERT: 1192 case MS_OP_DELAY: 1193 1194 /* let's suppose the next instr. is the same */ 1195 prefetch: 1196 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1197 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1198 1199 if (mi->opcode == MS_OP_DELAY) { 1200 DELAY(mi->arg[0].i); 1201 INCR_PC; 1202 goto prefetch; 1203 } 1204 break; 1205 1206 case MS_OP_ADELAY: 1207 if (mi->arg[0].i) 1208 tsleep(NULL, PPBPRI, "ppbdelay", 1209 mi->arg[0].i * (hz/1000)); 1210 INCR_PC; 1211 break; 1212 1213 case MS_OP_TRIG: 1214 reg = mi->arg[0].i; 1215 iter = mi->arg[1].i; 1216 p = (char *)mi->arg[2].p; 1217 1218 /* XXX delay limited to 255 us */ 1219 for (i=0; i<iter; i++) { 1220 w_reg(reg, ppc, *p++); 1221 DELAY((unsigned char)*p++); 1222 } 1223 INCR_PC; 1224 break; 1225 1226 case MS_OP_SET: 1227 ppc->ppc_accum = mi->arg[0].i; 1228 INCR_PC; 1229 break; 1230 1231 case MS_OP_DBRA: 1232 if (--ppc->ppc_accum > 0) 1233 mi += mi->arg[0].i; 1234 INCR_PC; 1235 break; 1236 1237 case MS_OP_BRSET: 1238 cc = r_str(ppc); 1239 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1240 mi += mi->arg[1].i; 1241 INCR_PC; 1242 break; 1243 1244 case MS_OP_BRCLEAR: 1245 cc = r_str(ppc); 1246 if ((cc & (char)mi->arg[0].i) == 0) 1247 mi += mi->arg[1].i; 1248 INCR_PC; 1249 break; 1250 1251 case MS_OP_BRSTAT: 1252 cc = r_str(ppc); 1253 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1254 (char)mi->arg[0].i) 1255 mi += mi->arg[2].i; 1256 INCR_PC; 1257 break; 1258 1259 case MS_OP_C_CALL: 1260 /* 1261 * If the C call returns !0 then end the microseq. 1262 * The current state of ptr is passed to the C function 1263 */ 1264 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1265 return (error); 1266 1267 INCR_PC; 1268 break; 1269 1270 case MS_OP_PTR: 1271 ppc->ppc_ptr = (char *)mi->arg[0].p; 1272 INCR_PC; 1273 break; 1274 1275 case MS_OP_CALL: 1276 if (stack) 1277 panic("%s: too much calls", __FUNCTION__); 1278 1279 if (mi->arg[0].p) { 1280 /* store the state of the actual 1281 * microsequence 1282 */ 1283 stack = mi; 1284 1285 /* jump to the new microsequence */ 1286 mi = (struct ppb_microseq *)mi->arg[0].p; 1287 } else 1288 INCR_PC; 1289 1290 break; 1291 1292 case MS_OP_SUBRET: 1293 /* retrieve microseq and pc state before the call */ 1294 mi = stack; 1295 1296 /* reset the stack */ 1297 stack = 0; 1298 1299 /* XXX return code */ 1300 1301 INCR_PC; 1302 break; 1303 1304 case MS_OP_PUT: 1305 case MS_OP_GET: 1306 case MS_OP_RET: 1307 /* can't return to ppb level during the execution 1308 * of a submicrosequence */ 1309 if (stack) 1310 panic("%s: can't return to ppb level", 1311 __FUNCTION__); 1312 1313 /* update pc for ppb level of execution */ 1314 *p_msq = mi; 1315 1316 /* return to ppb level of execution */ 1317 return (0); 1318 1319 default: 1320 panic("%s: unknown microsequence opcode 0x%x", 1321 __FUNCTION__, mi->opcode); 1322 } 1323 } 1324 1325 /* unreached */ 1326} 1327 1328static void 1329ppcintr(int unit) 1330{ 1331 struct ppc_data *ppc = ppcdata[unit]; 1332 u_char ctr, ecr, str; 1333 1334 str = r_str(ppc); 1335 ctr = r_ctr(ppc); 1336 ecr = r_ecr(ppc); 1337 1338#if PPC_DEBUG > 1 1339 printf("![%x/%x/%x]", ctr, ecr, str); 1340#endif 1341 1342 /* don't use ecp mode with IRQENABLE set */ 1343 if (ctr & IRQENABLE) { 1344 /* call upper code */ 1345 ppb_intr(&ppc->ppc_link); 1346 return; 1347 } 1348 1349 /* interrupts are generated by nFault signal 1350 * only in ECP mode */ 1351 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1352 /* check if ppc driver has programmed the 1353 * nFault interrupt */ 1354 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1355 1356 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1357 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1358 } else { 1359 /* call upper code */ 1360 ppb_intr(&ppc->ppc_link); 1361 return; 1362 } 1363 } 1364 1365 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1366 /* disable interrupts (should be done by hardware though) */ 1367 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1368 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1369 ecr = r_ecr(ppc); 1370 1371 /* check if DMA completed */ 1372 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1373#ifdef PPC_DEBUG 1374 printf("a"); 1375#endif 1376 /* stop DMA */ 1377 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1378 ecr = r_ecr(ppc); 1379 1380 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1381#ifdef PPC_DEBUG 1382 printf("d"); 1383#endif 1384 isa_dmadone( 1385 ppc->ppc_dmaflags, 1386 ppc->ppc_dmaddr, 1387 ppc->ppc_dmacnt, 1388 ppc->ppc_dmachan); 1389 1390 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1391 1392 /* wakeup the waiting process */ 1393 wakeup((caddr_t)ppc); 1394 } 1395 } 1396 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1397 1398 /* classic interrupt I/O */ 1399 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1400 1401 } 1402 1403 return; 1404} 1405 1406static int 1407ppc_read(int unit, char *buf, int len, int mode) 1408{ 1409 return (EINVAL); 1410} 1411 1412/* 1413 * Call this function if you want to send data in any advanced mode 1414 * of your parallel port: FIFO, DMA 1415 * 1416 * If what you want is not possible (no ECP, no DMA...), 1417 * EINVAL is returned 1418 */ 1419static int 1420ppc_write(int unit, char *buf, int len, int how) 1421{ 1422 struct ppc_data *ppc = ppcdata[unit]; 1423 char ecr, ecr_sav, ctr, ctr_sav; 1424 int s, error = 0; 1425 int spin; 1426 1427#ifdef PPC_DEBUG 1428 printf("w"); 1429#endif 1430 1431 ecr_sav = r_ecr(ppc); 1432 ctr_sav = r_ctr(ppc); 1433 1434 /* 1435 * Send buffer with DMA, FIFO and interrupts 1436 */ 1437 if (ppc->ppc_avm & PPB_ECP) { 1438 1439 if (ppc->ppc_dmachan >= 0) { 1440 1441 /* byte mode, no intr, no DMA, dir=0, flush fifo 1442 */ 1443 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1444 w_ecr(ppc, ecr); 1445 1446 /* disable nAck interrupts */ 1447 ctr = r_ctr(ppc); 1448 ctr &= ~IRQENABLE; 1449 w_ctr(ppc, ctr); 1450 1451 ppc->ppc_dmaflags = 0; 1452 ppc->ppc_dmaddr = (caddr_t)buf; 1453 ppc->ppc_dmacnt = (u_int)len; 1454 1455 switch (ppc->ppc_mode) { 1456 case PPB_COMPATIBLE: 1457 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1458 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1459 break; 1460 case PPB_ECP: 1461 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1462 break; 1463 default: 1464 error = EINVAL; 1465 goto error; 1466 } 1467 1468 w_ecr(ppc, ecr); 1469 ecr = r_ecr(ppc); 1470 1471 /* enter splhigh() not to be preempted 1472 * by the dma interrupt, we may miss 1473 * the wakeup otherwise 1474 */ 1475 s = splhigh(); 1476 1477 ppc->ppc_dmastat = PPC_DMA_INIT; 1478 1479 /* enable interrupts */ 1480 ecr &= ~PPC_SERVICE_INTR; 1481 ppc->ppc_irqstat = PPC_IRQ_DMA; 1482 w_ecr(ppc, ecr); 1483 1484 isa_dmastart( 1485 ppc->ppc_dmaflags, 1486 ppc->ppc_dmaddr, 1487 ppc->ppc_dmacnt, 1488 ppc->ppc_dmachan); 1489#ifdef PPC_DEBUG 1490 printf("s%d", ppc->ppc_dmacnt); 1491#endif 1492 ppc->ppc_dmastat = PPC_DMA_STARTED; 1493 1494 /* Wait for the DMA completed interrupt. We hope we won't 1495 * miss it, otherwise a signal will be necessary to unlock the 1496 * process. 1497 */ 1498 do { 1499 /* release CPU */ 1500 error = tsleep((caddr_t)ppc, 1501 PPBPRI | PCATCH, "ppcdma", 0); 1502 1503 } while (error == EWOULDBLOCK); 1504 1505 splx(s); 1506 1507 if (error) { 1508#ifdef PPC_DEBUG 1509 printf("i"); 1510#endif 1511 /* stop DMA */ 1512 isa_dmadone( 1513 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1514 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1515 1516 /* no dma, no interrupt, flush the fifo */ 1517 w_ecr(ppc, PPC_ECR_RESET); 1518 1519 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1520 goto error; 1521 } 1522 1523 /* wait for an empty fifo */ 1524 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1525 1526 for (spin=100; spin; spin--) 1527 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1528 goto fifo_empty; 1529#ifdef PPC_DEBUG 1530 printf("Z"); 1531#endif 1532 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1533 if (error != EWOULDBLOCK) { 1534#ifdef PPC_DEBUG 1535 printf("I"); 1536#endif 1537 /* no dma, no interrupt, flush the fifo */ 1538 w_ecr(ppc, PPC_ECR_RESET); 1539 1540 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1541 error = EINTR; 1542 goto error; 1543 } 1544 } 1545 1546fifo_empty: 1547 /* no dma, no interrupt, flush the fifo */ 1548 w_ecr(ppc, PPC_ECR_RESET); 1549 1550 } else 1551 error = EINVAL; /* XXX we should FIFO and 1552 * interrupts */ 1553 } else 1554 error = EINVAL; 1555 1556error: 1557 1558 /* PDRQ must be kept unasserted until nPDACK is 1559 * deasserted for a minimum of 350ns (SMC datasheet) 1560 * 1561 * Consequence may be a FIFO that never empty 1562 */ 1563 DELAY(1); 1564 1565 w_ecr(ppc, ecr_sav); 1566 w_ctr(ppc, ctr_sav); 1567 1568 return (error); 1569} 1570 1571/* 1572 * Configure current operating mode 1573 */ 1574static int 1575ppc_generic_setmode(int unit, int mode) 1576{ 1577 struct ppc_data *ppc = ppcdata[unit]; 1578 u_char ecr = 0; 1579 1580 /* check if mode is available */ 1581 if (mode && !(ppc->ppc_avm & mode)) 1582 return (EINVAL); 1583 1584 /* if ECP mode, configure ecr register */ 1585 if (ppc->ppc_avm & PPB_ECP) { 1586 /* return to byte mode (keeping direction bit), 1587 * no interrupt, no DMA to be able to change to 1588 * ECP 1589 */ 1590 w_ecr(ppc, PPC_ECR_RESET); 1591 ecr = PPC_DISABLE_INTR; 1592 1593 if (mode & PPB_EPP) 1594 return (EINVAL); 1595 else if (mode & PPB_ECP) 1596 /* select ECP mode */ 1597 ecr |= PPC_ECR_ECP; 1598 else if (mode & PPB_PS2) 1599 /* select PS2 mode with ECP */ 1600 ecr |= PPC_ECR_PS2; 1601 else 1602 /* select COMPATIBLE/NIBBLE mode */ 1603 ecr |= PPC_ECR_STD; 1604 1605 w_ecr(ppc, ecr); 1606 } 1607 1608 ppc->ppc_mode = mode; 1609 1610 return (0); 1611} 1612 1613/* 1614 * The ppc driver is free to choose options like FIFO or DMA 1615 * if ECP mode is available. 1616 * 1617 * The 'RAW' option allows the upper drivers to force the ppc mode 1618 * even with FIFO, DMA available. 1619 */ 1620int 1621ppc_smclike_setmode(int unit, int mode) 1622{ 1623 struct ppc_data *ppc = ppcdata[unit]; 1624 u_char ecr = 0; 1625 1626 /* check if mode is available */ 1627 if (mode && !(ppc->ppc_avm & mode)) 1628 return (EINVAL); 1629 1630 /* if ECP mode, configure ecr register */ 1631 if (ppc->ppc_avm & PPB_ECP) { 1632 /* return to byte mode (keeping direction bit), 1633 * no interrupt, no DMA to be able to change to 1634 * ECP or EPP mode 1635 */ 1636 w_ecr(ppc, PPC_ECR_RESET); 1637 ecr = PPC_DISABLE_INTR; 1638 1639 if (mode & PPB_EPP) 1640 /* select EPP mode */ 1641 ecr |= PPC_ECR_EPP; 1642 else if (mode & PPB_ECP) 1643 /* select ECP mode */ 1644 ecr |= PPC_ECR_ECP; 1645 else if (mode & PPB_PS2) 1646 /* select PS2 mode with ECP */ 1647 ecr |= PPC_ECR_PS2; 1648 else 1649 /* select COMPATIBLE/NIBBLE mode */ 1650 ecr |= PPC_ECR_STD; 1651 1652 w_ecr(ppc, ecr); 1653 } 1654 1655 ppc->ppc_mode = mode; 1656 1657 return (0); 1658} 1659 1660/* 1661 * EPP timeout, according to the PC87332 manual 1662 * Semantics of clearing EPP timeout bit. 1663 * PC87332 - reading SPP_STR does it... 1664 * SMC - write 1 to EPP timeout bit XXX 1665 * Others - (?) write 0 to EPP timeout bit 1666 */ 1667static void 1668ppc_reset_epp_timeout(int unit) 1669{ 1670 struct ppc_data *ppc = ppcdata[unit]; 1671 register char r; 1672 1673 r = r_str(ppc); 1674 w_str(ppc, r | 0x1); 1675 w_str(ppc, r & 0xfe); 1676 1677 return; 1678} 1679 1680static int 1681ppcprobe(struct isa_device *dvp) 1682{ 1683 static short next_bios_ppc = 0; 1684 struct ppc_data *ppc; 1685 1686 /* 1687 * If port not specified, use bios list. 1688 */ 1689 if(dvp->id_iobase < 0) { 1690 if((next_bios_ppc < BIOS_MAX_PPC) && 1691 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1692 dvp->id_iobase = *(BIOS_PORTS+next_bios_ppc++); 1693 if (bootverbose) 1694 printf("ppc: parallel port found at 0x%x\n", 1695 dvp->id_iobase); 1696 } else 1697 return (0); 1698 } 1699 1700 /* 1701 * Port was explicitly specified. 1702 * This allows probing of ports unknown to the BIOS. 1703 */ 1704 1705 /* 1706 * Allocate the ppc_data structure. 1707 */ 1708 ppc = malloc(sizeof(struct ppc_data), M_DEVBUF, M_NOWAIT); 1709 if (!ppc) { 1710 printf("ppc: cannot malloc!\n"); 1711 goto error; 1712 } 1713 bzero(ppc, sizeof(struct ppc_data)); 1714 1715 ppc->ppc_base = dvp->id_iobase; 1716 ppc->ppc_unit = dvp->id_unit; 1717 ppc->ppc_type = GENERIC; 1718 1719 /* store boot flags */ 1720 ppc->ppc_flags = dvp->id_flags; 1721 1722 ppc->ppc_mode = PPB_COMPATIBLE; 1723 ppc->ppc_epp = (dvp->id_flags & 0x10) >> 4; 1724 1725 /* 1726 * XXX Try and detect if interrupts are working 1727 */ 1728 if (!(dvp->id_flags & 0x20) && dvp->id_irq) 1729 ppc->ppc_irq = ffs(dvp->id_irq) - 1; 1730 1731 ppc->ppc_dmachan = dvp->id_drq; 1732 1733 ppcdata[ppc->ppc_unit] = ppc; 1734 nppc ++; 1735 1736 /* 1737 * Link the Parallel Port Chipset (adapter) to 1738 * the future ppbus. Default to a generic chipset 1739 */ 1740 ppc->ppc_link.adapter_unit = ppc->ppc_unit; 1741 ppc->ppc_link.adapter = &ppc_generic_adapter; 1742 1743 /* 1744 * Try to detect the chipset and its mode. 1745 */ 1746 if (ppc_detect(ppc, dvp->id_flags & 0xf)) 1747 goto error; 1748 1749 return (IO_LPTSIZE); 1750 1751error: 1752 return (0); 1753} 1754 1755static int 1756ppcattach(struct isa_device *isdp) 1757{ 1758 struct ppc_data *ppc = ppcdata[isdp->id_unit]; 1759 struct ppb_data *ppbus; 1760 1761 printf("ppc%d: %s chipset (%s) in %s mode%s\n", ppc->ppc_unit, 1762 ppc_types[ppc->ppc_type], ppc_avms[ppc->ppc_avm], 1763 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1764 ppc_epp_protocol[ppc->ppc_epp] : ""); 1765 1766 if (ppc->ppc_fifo) 1767 printf("ppc%d: FIFO with %d/%d/%d bytes threshold\n", 1768 ppc->ppc_unit, ppc->ppc_fifo, ppc->ppc_wthr, 1769 ppc->ppc_rthr); 1770 1771 isdp->id_ointr = ppcintr; 1772 1773 /* 1774 * Prepare ppbus data area for upper level code. 1775 */ 1776 ppbus = ppb_alloc_bus(); 1777 1778 if (!ppbus) 1779 return (0); 1780 1781 ppc->ppc_link.ppbus = ppbus; 1782 ppbus->ppb_link = &ppc->ppc_link; 1783 1784 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1785 1786 /* acquire the DMA channel forever */ 1787 isa_dma_acquire(ppc->ppc_dmachan); 1788 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1789 } 1790 1791 /* 1792 * Probe the ppbus and attach devices found. 1793 */ 1794 ppb_attachdevs(ppbus); 1795 1796 return (1); 1797} 1798#endif 1799