ppc.c revision 45935
151973Smsmith/*- 251973Smsmith * Copyright (c) 1997, 1998 Nicolas Souchu 351973Smsmith * All rights reserved. 451973Smsmith * 551973Smsmith * Redistribution and use in source and binary forms, with or without 651973Smsmith * modification, are permitted provided that the following conditions 751973Smsmith * are met: 851973Smsmith * 1. Redistributions of source code must retain the above copyright 951973Smsmith * notice, this list of conditions and the following disclaimer. 1051973Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1151973Smsmith * notice, this list of conditions and the following disclaimer in the 1251973Smsmith * documentation and/or other materials provided with the distribution. 1351973Smsmith * 1451973Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1551973Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1651973Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1751973Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1851973Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1951973Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2051973Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2151973Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2251973Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2351973Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2451973Smsmith * SUCH DAMAGE. 2551973Smsmith * 2651973Smsmith * $Id: ppc.c,v 1.20 1999/02/14 22:02:47 nsouch Exp $ 2751973Smsmith * 2851973Smsmith */ 2952544Smsmith#include "ppc.h" 30138090Sscottl 3152544Smsmith#if NPPC > 0 3251973Smsmith 3351973Smsmith#include <sys/param.h> 3451973Smsmith#include <sys/systm.h> 3558188Smsmith#include <sys/conf.h> 3651973Smsmith#include <sys/malloc.h> 3751973Smsmith#include <sys/kernel.h> 3851973Smsmith 3958188Smsmith#include <machine/clock.h> 4058188Smsmith 4158188Smsmith#include <vm/vm.h> 4258188Smsmith#include <vm/vm_param.h> 4351973Smsmith#include <vm/pmap.h> 4451973Smsmith 4551973Smsmith#include <i386/isa/isa_device.h> 4651973Smsmith#include <i386/isa/isa.h> 4751973Smsmith 4851973Smsmith#include <dev/ppbus/ppbconf.h> 4951973Smsmith#include <dev/ppbus/ppb_msq.h> 5058188Smsmith 5158188Smsmith#include <i386/isa/ppcreg.h> 5259136Smsmith 5351973Smsmith#include "opt_ppc.h" 5458188Smsmith 5558188Smsmith#define LOG_PPC(function, ppc, string) \ 5658188Smsmith if (bootverbose) printf("%s: %s\n", function, string) 5758188Smsmith 5858188Smsmithstatic int ppcprobe(struct isa_device *); 5951973Smsmithstatic int ppcattach(struct isa_device *); 6051973Smsmith 6151973Smsmithstruct isa_driver ppcdriver = { 6251973Smsmith ppcprobe, ppcattach, "ppc" 6351973Smsmith}; 6451973Smsmith 6554419Smsmithstatic struct ppc_data *ppcdata[NPPC]; 6651973Smsmithstatic int nppc = 0; 6751973Smsmith 6851973Smsmithstatic char *ppc_types[] = { 6952225Smsmith "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 7052225Smsmith "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 0 7152225Smsmith}; 7252225Smsmith 7352225Smsmith/* list of available modes */ 7452225Smsmithstatic char *ppc_avms[] = { 7552225Smsmith "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 7652225Smsmith "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 7758188Smsmith "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 7858188Smsmith "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 7958188Smsmith}; 8052225Smsmith 81240608Sjhb/* list of current executing modes 82240608Sjhb * Note that few modes do not actually exist. 83240608Sjhb */ 84240608Sjhbstatic char *ppc_modes[] = { 85240608Sjhb "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 86240608Sjhb "EPP", "EPP", "EPP", "ECP", 87240608Sjhb "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 88240608Sjhb "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 89240608Sjhb}; 90240608Sjhb 91240608Sjhbstatic char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 92240608Sjhb 9352225Smsmith/* 9452225Smsmith * BIOS printer list - used by BIOS probe. 9558188Smsmith */ 9658188Smsmith#define BIOS_PPC_PORTS 0x408 9752225Smsmith#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 9852225Smsmith#define BIOS_MAX_PPC 4 9952225Smsmith 10052225Smsmith/* 10158188Smsmith * All these functions are default actions for IN/OUT operations. 10258188Smsmith * They may be redefined if needed. 10352225Smsmith */ 10452225Smsmithstatic void ppc_outsb_epp(int unit, char *addr, int cnt) { 10552225Smsmith outsb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 10652225Smsmithstatic void ppc_outsw_epp(int unit, char *addr, int cnt) { 10758188Smsmith outsw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 10858188Smsmithstatic void ppc_outsl_epp(int unit, char *addr, int cnt) { 10952225Smsmith outsl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 11052225Smsmithstatic void ppc_insb_epp(int unit, char *addr, int cnt) { 11152225Smsmith insb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 11252225Smsmithstatic void ppc_insw_epp(int unit, char *addr, int cnt) { 11358188Smsmith insw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 11458188Smsmithstatic void ppc_insl_epp(int unit, char *addr, int cnt) { 11558188Smsmith insl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 11652225Smsmith 11752225Smsmithstatic u_char ppc_rdtr(int unit) { return r_dtr(ppcdata[unit]); } 118240608Sjhbstatic u_char ppc_rstr(int unit) { return r_str(ppcdata[unit]); } 119240608Sjhbstatic u_char ppc_rctr(int unit) { return r_ctr(ppcdata[unit]); } 120240608Sjhbstatic u_char ppc_repp_A(int unit) { return r_epp_A(ppcdata[unit]); } 121240608Sjhbstatic u_char ppc_repp_D(int unit) { return r_epp_D(ppcdata[unit]); } 122240608Sjhbstatic u_char ppc_recr(int unit) { return r_ecr(ppcdata[unit]); } 123240608Sjhbstatic u_char ppc_rfifo(int unit) { return r_fifo(ppcdata[unit]); } 124240608Sjhb 125240608Sjhbstatic void ppc_wdtr(int unit, char byte) { w_dtr(ppcdata[unit], byte); } 126240608Sjhbstatic void ppc_wstr(int unit, char byte) { w_str(ppcdata[unit], byte); } 127240608Sjhbstatic void ppc_wctr(int unit, char byte) { w_ctr(ppcdata[unit], byte); } 128240608Sjhbstatic void ppc_wepp_A(int unit, char byte) { w_epp_A(ppcdata[unit], byte); } 129240608Sjhbstatic void ppc_wepp_D(int unit, char byte) { w_epp_D(ppcdata[unit], byte); } 13052225Smsmithstatic void ppc_wecr(int unit, char byte) { w_ecr(ppcdata[unit], byte); } 13152225Smsmithstatic void ppc_wfifo(int unit, char byte) { w_fifo(ppcdata[unit], byte); } 13258188Smsmith 13352225Smsmithstatic void ppc_reset_epp_timeout(int); 13452225Smsmithstatic void ppc_ecp_sync(int); 13552225Smsmithstatic ointhand2_t ppcintr; 13652225Smsmith 13752225Smsmithstatic int ppc_exec_microseq(int, struct ppb_microseq **); 13852225Smsmithstatic int ppc_generic_setmode(int, int); 13952225Smsmithstatic int ppc_smclike_setmode(int, int); 14052225Smsmith 14152225Smsmithstatic int ppc_read(int, char *, int, int); 14252225Smsmithstatic int ppc_write(int, char *, int, int); 14352225Smsmith 14452225Smsmithstatic struct ppb_adapter ppc_smclike_adapter = { 14552225Smsmith 14652225Smsmith 0, /* no intr handler, filled by chipset dependent code */ 14758188Smsmith 14858188Smsmith ppc_reset_epp_timeout, ppc_ecp_sync, 14952225Smsmith 15054419Smsmith ppc_exec_microseq, 15154419Smsmith 15254419Smsmith ppc_smclike_setmode, ppc_read, ppc_write, 15358188Smsmith 15454419Smsmith ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 15554419Smsmith ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 15654419Smsmith 15754419Smsmith ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo, 15854419Smsmith ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo 15958188Smsmith}; 16058188Smsmith 16158188Smsmithstatic struct ppb_adapter ppc_generic_adapter = { 16254419Smsmith 163240608Sjhb 0, /* no intr handler, filled by chipset dependent code */ 164240608Sjhb 165240608Sjhb ppc_reset_epp_timeout, ppc_ecp_sync, 166240608Sjhb 167240608Sjhb ppc_exec_microseq, 168240608Sjhb 169240608Sjhb ppc_generic_setmode, ppc_read, ppc_write, 170240608Sjhb 171240608Sjhb ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 172240608Sjhb ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 173240608Sjhb 174240608Sjhb ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp_A, ppc_repp_D, ppc_recr, ppc_rfifo, 17554419Smsmith ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp_A, ppc_wepp_D, ppc_wecr, ppc_wfifo 17654419Smsmith}; 17758188Smsmith 17854419Smsmith/* 17954419Smsmith * ppc_ecp_sync() XXX 18054419Smsmith */ 18158188Smsmithstatic void 18254419Smsmithppc_ecp_sync(int unit) { 18354419Smsmith 18454419Smsmith struct ppc_data *ppc = ppcdata[unit]; 18554419Smsmith int i, r; 18654419Smsmith 18754419Smsmith if (!(ppc->ppc_avm & PPB_ECP)) 18854419Smsmith return; 18954419Smsmith 19054419Smsmith r = r_ecr(ppc); 19154419Smsmith if ((r & 0xe0) != PPC_ECR_EPP) 19258188Smsmith return; 19354419Smsmith 19458188Smsmith for (i = 0; i < 100; i++) { 19558188Smsmith r = r_ecr(ppc); 19654419Smsmith if (r & 0x1) 19751973Smsmith return; 19851973Smsmith DELAY(100); 19951973Smsmith } 20051973Smsmith 20151973Smsmith printf("ppc%d: ECP sync failed as data still " \ 20251973Smsmith "present in FIFO.\n", unit); 203103870Salfred 20451973Smsmith return; 20551973Smsmith} 20651973Smsmith 20751973Smsmith/* 20858188Smsmith * ppc_detect_fifo() 20958188Smsmith * 21058188Smsmith * Detect parallel port FIFO 21158188Smsmith */ 21258188Smsmithstatic int 21358188Smsmithppc_detect_fifo(struct ppc_data *ppc) 21458188Smsmith{ 21558188Smsmith char ecr_sav; 21658188Smsmith char ctr_sav, ctr, cc; 21758188Smsmith short i; 21858188Smsmith 21958188Smsmith /* save registers */ 22058188Smsmith ecr_sav = r_ecr(ppc); 22158188Smsmith ctr_sav = r_ctr(ppc); 22258188Smsmith 22358188Smsmith /* enter ECP configuration mode, no interrupt, no DMA */ 22458188Smsmith w_ecr(ppc, 0xf4); 22558188Smsmith 22658188Smsmith /* read PWord size - transfers in FIFO mode must be PWord aligned */ 22758188Smsmith ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 22858188Smsmith 22958188Smsmith /* XXX 16 and 32 bits implementations not supported */ 23058188Smsmith if (ppc->ppc_pword != PPC_PWORD_8) { 23158188Smsmith LOG_PPC(__FUNCTION__, ppc, "PWord not supported"); 23258188Smsmith goto error; 233103870Salfred } 234103870Salfred 23558188Smsmith w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 23651973Smsmith ctr = r_ctr(ppc); 23751973Smsmith w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 23851973Smsmith 23951973Smsmith /* enter ECP test mode, no interrupt, no DMA */ 24051973Smsmith w_ecr(ppc, 0xd4); 24151973Smsmith 24251973Smsmith /* flush the FIFO */ 24351973Smsmith for (i=0; i<1024; i++) { 24451973Smsmith if (r_ecr(ppc) & PPC_FIFO_EMPTY) 24551973Smsmith break; 24651973Smsmith cc = r_fifo(ppc); 24751973Smsmith } 24851973Smsmith 24951973Smsmith if (i >= 1024) { 25051973Smsmith LOG_PPC(__FUNCTION__, ppc, "can't flush FIFO"); 25151973Smsmith goto error; 25251973Smsmith } 25351973Smsmith 25451973Smsmith /* enable interrupts, no DMA */ 25551973Smsmith w_ecr(ppc, 0xd0); 25651973Smsmith 25751973Smsmith /* determine readIntrThreshold 25851973Smsmith * fill the FIFO until serviceIntr is set 25951973Smsmith */ 26051973Smsmith for (i=0; i<1024; i++) { 26151973Smsmith w_fifo(ppc, (char)i); 26251973Smsmith if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 26351973Smsmith /* readThreshold reached */ 264103870Salfred ppc->ppc_rthr = i+1; 265103870Salfred } 26651973Smsmith if (r_ecr(ppc) & PPC_FIFO_FULL) { 26751973Smsmith ppc->ppc_fifo = i+1; 26851973Smsmith break; 26951973Smsmith } 27051973Smsmith } 27151973Smsmith 27251973Smsmith if (i >= 1024) { 27351973Smsmith LOG_PPC(__FUNCTION__, ppc, "can't fill FIFO"); 27451973Smsmith goto error; 27551973Smsmith } 27651973Smsmith 27751973Smsmith w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 27851973Smsmith w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 27951973Smsmith w_ecr(ppc, 0xd0); /* enable interrupts */ 28051973Smsmith 28151973Smsmith /* determine writeIntrThreshold 28251973Smsmith * empty the FIFO until serviceIntr is set 28351973Smsmith */ 28451973Smsmith for (i=ppc->ppc_fifo; i>0; i--) { 28551973Smsmith if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 28651973Smsmith LOG_PPC(__FUNCTION__, ppc, "invalid data in FIFO"); 28751973Smsmith goto error; 28851973Smsmith } 28954979Smsmith if (r_ecr(ppc) & PPC_SERVICE_INTR) { 29051973Smsmith /* writeIntrThreshold reached */ 29151973Smsmith ppc->ppc_wthr = ppc->ppc_fifo - i+1; 29251973Smsmith } 29351973Smsmith /* if FIFO empty before the last byte, error */ 29451973Smsmith if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 29551973Smsmith LOG_PPC(__FUNCTION__, ppc, "data lost in FIFO"); 29651973Smsmith goto error; 29751973Smsmith } 29851973Smsmith } 29951973Smsmith 30051973Smsmith /* FIFO must be empty after the last byte */ 30151973Smsmith if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 30251973Smsmith LOG_PPC(__FUNCTION__, ppc, "can't empty the FIFO"); 30351973Smsmith goto error; 30451973Smsmith } 30551973Smsmith 30651973Smsmith w_ctr(ppc, ctr_sav); 30751973Smsmith w_ecr(ppc, ecr_sav); 30851973Smsmith 30951973Smsmith return (0); 31054979Smsmith 31151973Smsmitherror: 31251973Smsmith w_ctr(ppc, ctr_sav); 31351973Smsmith w_ecr(ppc, ecr_sav); 31451973Smsmith 315103870Salfred return (EINVAL); 31651973Smsmith} 31751973Smsmith 31851973Smsmithstatic int 31951973Smsmithppc_detect_port(struct ppc_data *ppc) 32051973Smsmith{ 32151973Smsmith 32251973Smsmith w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 323103870Salfred w_dtr(ppc, 0xaa); 32451973Smsmith if (r_dtr(ppc) != 0xaa) 32551973Smsmith return (0); 32651973Smsmith 32751973Smsmith return (1); 32851973Smsmith} 32951973Smsmith 33051973Smsmith/* 33151973Smsmith * ppc_pc873xx_detect 33251973Smsmith * 33351973Smsmith * Probe for a Natsemi PC873xx-family part. 33451973Smsmith * 33551973Smsmith * References in this function are to the National Semiconductor 33651973Smsmith * PC87332 datasheet TL/C/11930, May 1995 revision. 33751973Smsmith */ 33851973Smsmithstatic int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 33951973Smsmithstatic int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 34051973Smsmithstatic int pc873xx_irqtab[] = {5, 7, 5, 0}; 34151973Smsmith 34251973Smsmithstatic int pc873xx_regstab[] = { 34351973Smsmith PC873_FER, PC873_FAR, PC873_PTR, 34451973Smsmith PC873_FCR, PC873_PCR, PC873_PMC, 34551973Smsmith PC873_TUP, PC873_SID, PC873_PNP0, 34651973Smsmith PC873_PNP1, PC873_LPTBA, -1 34751973Smsmith}; 348103870Salfred 34951973Smsmithstatic char *pc873xx_rnametab[] = { 35051973Smsmith "FER", "FAR", "PTR", "FCR", "PCR", 35151973Smsmith "PMC", "TUP", "SID", "PNP0", "PNP1", 35251973Smsmith "LPTBA", NULL 35351973Smsmith}; 35451973Smsmith 35551973Smsmithstatic int 35651973Smsmithppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 35751973Smsmith{ 358103870Salfred static int index = 0; 35951973Smsmith int idport, irq; 36058188Smsmith int ptr, pcr, val, i; 36158188Smsmith 36258188Smsmith while ((idport = pc873xx_basetab[index++])) { 36358188Smsmith 36458188Smsmith /* XXX should check first to see if this location is already claimed */ 36558188Smsmith 36658188Smsmith /* 36758188Smsmith * Pull the 873xx through the power-on ID cycle (2.2,1.). 36858188Smsmith * We can't use this to locate the chip as it may already have 36958188Smsmith * been used by the BIOS. 37058188Smsmith */ 37158188Smsmith (void)inb(idport); (void)inb(idport); 37258188Smsmith (void)inb(idport); (void)inb(idport); 37358188Smsmith 37458188Smsmith /* 37558188Smsmith * Read the SID byte. Possible values are : 37658188Smsmith * 37758188Smsmith * 01010xxx PC87334 37858188Smsmith * 0001xxxx PC87332 37958188Smsmith * 01110xxx PC87306 38058188Smsmith */ 38158188Smsmith outb(idport, PC873_SID); 38258188Smsmith val = inb(idport + 1); 38358188Smsmith if ((val & 0xf0) == 0x10) { 38458188Smsmith ppc->ppc_type = NS_PC87332; 38558188Smsmith } else if ((val & 0xf8) == 0x70) { 38658188Smsmith ppc->ppc_type = NS_PC87306; 38758188Smsmith } else if ((val & 0xf8) == 0x50) { 38858188Smsmith ppc->ppc_type = NS_PC87334; 38958188Smsmith } else { 39058188Smsmith if (bootverbose && (val != 0xff)) 39158188Smsmith printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 39258188Smsmith continue ; /* not recognised */ 39358188Smsmith } 39458188Smsmith 39558188Smsmith /* print registers */ 39658188Smsmith if (bootverbose) { 39758188Smsmith printf("PC873xx"); 39858188Smsmith for (i=0; pc873xx_regstab[i] != -1; i++) { 399103870Salfred outb(idport, pc873xx_regstab[i]); 40058188Smsmith printf(" %s=0x%x", pc873xx_rnametab[i], 40158188Smsmith inb(idport + 1) & 0xff); 40258188Smsmith } 40358188Smsmith printf("\n"); 40458188Smsmith } 40558188Smsmith 406103870Salfred /* 40758188Smsmith * We think we have one. Is it enabled and where we want it to be? 40858188Smsmith */ 40958188Smsmith outb(idport, PC873_FER); 41058188Smsmith val = inb(idport + 1); 41158188Smsmith if (!(val & PC873_PPENABLE)) { 41258188Smsmith if (bootverbose) 41358188Smsmith printf("PC873xx parallel port disabled\n"); 41458188Smsmith continue; 41558188Smsmith } 41658188Smsmith outb(idport, PC873_FAR); 41758188Smsmith val = inb(idport + 1) & 0x3; 41858188Smsmith /* XXX we should create a driver instance for every port found */ 41958188Smsmith if (pc873xx_porttab[val] != ppc->ppc_base) { 42058188Smsmith if (bootverbose) 42158188Smsmith printf("PC873xx at 0x%x not for driver at port 0x%x\n", 42258188Smsmith pc873xx_porttab[val], ppc->ppc_base); 42358188Smsmith continue; 42458188Smsmith } 42558188Smsmith 42658188Smsmith outb(idport, PC873_PTR); 427103870Salfred ptr = inb(idport + 1); 42858188Smsmith 42958188Smsmith /* get irq settings */ 43058188Smsmith if (ppc->ppc_base == 0x378) 43158188Smsmith irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 43258188Smsmith else 43358188Smsmith irq = pc873xx_irqtab[val]; 43458188Smsmith 43558188Smsmith if (bootverbose) 43658188Smsmith printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 43758188Smsmith 43858188Smsmith /* 43958188Smsmith * Check if irq settings are correct 44058188Smsmith */ 44158188Smsmith if (irq != ppc->ppc_irq) { 44258188Smsmith /* 44358188Smsmith * If the chipset is not locked and base address is 0x378, 44458188Smsmith * we have another chance 44558188Smsmith */ 44658188Smsmith if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 44758188Smsmith if (ppc->ppc_irq == 7) { 44858188Smsmith outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 44958188Smsmith outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 45058188Smsmith } else { 45158188Smsmith outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 452103870Salfred outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 45358188Smsmith } 45458188Smsmith if (bootverbose) 45558188Smsmith printf("PC873xx irq set to %d\n", ppc->ppc_irq); 45658188Smsmith } else { 45758188Smsmith if (bootverbose) 45858188Smsmith printf("PC873xx sorry, can't change irq setting\n"); 45958188Smsmith } 460103870Salfred } else { 46158188Smsmith if (bootverbose) 46258188Smsmith printf("PC873xx irq settings are correct\n"); 46358188Smsmith } 46458188Smsmith 46558188Smsmith outb(idport, PC873_PCR); 46658188Smsmith pcr = inb(idport + 1); 46758188Smsmith 46858188Smsmith if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 46958188Smsmith if (bootverbose) 47058188Smsmith printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 47158188Smsmith 47258188Smsmith ppc->ppc_avm |= PPB_NIBBLE; 47358188Smsmith if (bootverbose) 47458188Smsmith printf(", NIBBLE"); 47558188Smsmith 47658188Smsmith if (pcr & PC873_EPPEN) { 47758188Smsmith ppc->ppc_avm |= PPB_EPP; 47858188Smsmith 47958188Smsmith if (bootverbose) 48058188Smsmith printf(", EPP"); 48158188Smsmith 48258188Smsmith if (pcr & PC873_EPP19) 48358188Smsmith ppc->ppc_epp = EPP_1_9; 48458188Smsmith else 48558188Smsmith ppc->ppc_epp = EPP_1_7; 486103870Salfred 48758188Smsmith if ((ppc->ppc_type == NS_PC87332) && bootverbose) { 48859136Smsmith outb(idport, PC873_PTR); 48959136Smsmith ptr = inb(idport + 1); 49059136Smsmith if (ptr & PC873_EPPRDIR) 49159136Smsmith printf(", Regular mode"); 49259136Smsmith else 49359136Smsmith printf(", Automatic mode"); 49459136Smsmith } 49559136Smsmith } else if (pcr & PC873_ECPEN) { 496103870Salfred ppc->ppc_avm |= PPB_ECP; 49759136Smsmith if (bootverbose) 49858188Smsmith printf(", ECP"); 49952544Smsmith 50052544Smsmith if (pcr & PC873_ECPCLK) { /* XXX */ 50152544Smsmith ppc->ppc_avm |= PPB_PS2; 50252544Smsmith if (bootverbose) 50352544Smsmith printf(", PS/2"); 50452544Smsmith } 50552544Smsmith } else { 50652544Smsmith outb(idport, PC873_PTR); 50752544Smsmith ptr = inb(idport + 1); 50852544Smsmith if (ptr & PC873_EXTENDED) { 50952544Smsmith ppc->ppc_avm |= PPB_SPP; 51052544Smsmith if (bootverbose) 51152544Smsmith printf(", SPP"); 51252544Smsmith } 51352544Smsmith } 51452544Smsmith } else { 51552544Smsmith if (bootverbose) 51652544Smsmith printf("PC873xx unlocked"); 51752544Smsmith 51852544Smsmith if (chipset_mode & PPB_ECP) { 51952544Smsmith if ((chipset_mode & PPB_EPP) && bootverbose) 52052544Smsmith printf(", ECP+EPP not supported"); 52152544Smsmith 52252544Smsmith pcr &= ~PC873_EPPEN; 52352544Smsmith pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 52452544Smsmith outb(idport + 1, pcr); 52552544Smsmith outb(idport + 1, pcr); 52652544Smsmith 52752544Smsmith if (bootverbose) 52852544Smsmith printf(", ECP"); 52952544Smsmith 53052544Smsmith } else if (chipset_mode & PPB_EPP) { 53152544Smsmith pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 53252544Smsmith pcr |= (PC873_EPPEN | PC873_EPP19); 53352544Smsmith outb(idport + 1, pcr); 53452544Smsmith outb(idport + 1, pcr); 53552544Smsmith 53652544Smsmith ppc->ppc_epp = EPP_1_9; /* XXX */ 53752544Smsmith 53852544Smsmith if (bootverbose) 53952544Smsmith printf(", EPP1.9"); 54052544Smsmith 54152544Smsmith /* enable automatic direction turnover */ 54252544Smsmith if (ppc->ppc_type == NS_PC87332) { 54352544Smsmith outb(idport, PC873_PTR); 54452544Smsmith ptr = inb(idport + 1); 54552544Smsmith ptr &= ~PC873_EPPRDIR; 54652544Smsmith outb(idport + 1, ptr); 54752544Smsmith outb(idport + 1, ptr); 54852544Smsmith 54952544Smsmith if (bootverbose) 55052544Smsmith printf(", Automatic mode"); 55152544Smsmith } 55252544Smsmith } else { 55352544Smsmith pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 55452544Smsmith outb(idport + 1, pcr); 55552544Smsmith outb(idport + 1, pcr); 55652544Smsmith 55752544Smsmith /* configure extended bit in PTR */ 55852544Smsmith outb(idport, PC873_PTR); 55952544Smsmith ptr = inb(idport + 1); 56052544Smsmith 56152544Smsmith if (chipset_mode & PPB_PS2) { 56252544Smsmith ptr |= PC873_EXTENDED; 56352544Smsmith 56452544Smsmith if (bootverbose) 56552544Smsmith printf(", PS/2"); 56652544Smsmith 56752544Smsmith } else { 56852544Smsmith /* default to NIBBLE mode */ 56952544Smsmith ptr &= ~PC873_EXTENDED; 57052544Smsmith 57152544Smsmith if (bootverbose) 57252544Smsmith printf(", NIBBLE"); 57352544Smsmith } 57452544Smsmith outb(idport + 1, ptr); 57552544Smsmith outb(idport + 1, ptr); 57652544Smsmith } 57752544Smsmith 57852544Smsmith ppc->ppc_avm = chipset_mode; 57952544Smsmith } 58052544Smsmith 58152544Smsmith if (bootverbose) 58252544Smsmith printf("\n"); 58352544Smsmith 58452544Smsmith ppc->ppc_link.adapter = &ppc_generic_adapter; 58552544Smsmith ppc_generic_setmode(ppc->ppc_unit, chipset_mode); 58652544Smsmith 58752544Smsmith return(chipset_mode); 58852544Smsmith } 58952544Smsmith return(-1); 59052544Smsmith} 59152544Smsmith 59252544Smsmithstatic int 59352544Smsmithppc_check_epp_timeout(struct ppc_data *ppc) 59452544Smsmith{ 59552544Smsmith ppc_reset_epp_timeout(ppc->ppc_unit); 59652544Smsmith 59752544Smsmith return (!(r_str(ppc) & TIMEOUT)); 59852544Smsmith} 59952544Smsmith 60052544Smsmith/* 60152544Smsmith * ppc_smc37c66xgt_detect 60252544Smsmith * 60352544Smsmith * SMC FDC37C66xGT configuration. 60452544Smsmith */ 60552544Smsmithstatic int 60652544Smsmithppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 60752544Smsmith{ 60852544Smsmith int s, i; 60952544Smsmith u_char r; 61052544Smsmith int type = -1; 61152544Smsmith int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 61252544Smsmith 61352544Smsmith int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 61452544Smsmith 61552544Smsmith 61652544Smsmith#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 61752544Smsmith 61852544Smsmith /* 61952544Smsmith * Detection: enter configuration mode and read CRD register. 62058188Smsmith */ 62158188Smsmith 622 s = splhigh(); 623 outb(csr, SMC665_iCODE); 624 outb(csr, SMC665_iCODE); 625 splx(s); 626 627 outb(csr, 0xd); 628 if (inb(cio) == 0x65) { 629 type = SMC_37C665GT; 630 goto config; 631 } 632 633 for (i = 0; i < 2; i++) { 634 s = splhigh(); 635 outb(csr, SMC666_iCODE); 636 outb(csr, SMC666_iCODE); 637 splx(s); 638 639 outb(csr, 0xd); 640 if (inb(cio) == 0x66) { 641 type = SMC_37C666GT; 642 break; 643 } 644 645 /* Another chance, CSR may be hard-configured to be at 0x370 */ 646 csr = SMC666_CSR; 647 } 648 649config: 650 /* 651 * If chipset not found, do not continue. 652 */ 653 if (type == -1) 654 return (-1); 655 656 /* select CR1 */ 657 outb(csr, 0x1); 658 659 /* read the port's address: bits 0 and 1 of CR1 */ 660 r = inb(cio) & SMC_CR1_ADDR; 661 if (port_address[(int)r] != ppc->ppc_base) 662 return (-1); 663 664 ppc->ppc_type = type; 665 666 /* 667 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 668 * If SPP mode is detected, try to set ECP+EPP mode 669 */ 670 671 if (bootverbose) { 672 outb(csr, 0x1); 673 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 674 inb(cio) & 0xff); 675 676 outb(csr, 0x4); 677 printf(" CR4=0x%x", inb(cio) & 0xff); 678 } 679 680 /* select CR1 */ 681 outb(csr, 0x1); 682 683 if (!chipset_mode) { 684 /* autodetect mode */ 685 686 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 687 if (type == SMC_37C666GT) { 688 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 689 if (bootverbose) 690 printf(" configuration hardwired, supposing " \ 691 "ECP+EPP SPP"); 692 693 } else 694 if ((inb(cio) & SMC_CR1_MODE) == 0) { 695 /* already in extended parallel port mode, read CR4 */ 696 outb(csr, 0x4); 697 r = (inb(cio) & SMC_CR4_EMODE); 698 699 switch (r) { 700 case SMC_SPP: 701 ppc->ppc_avm |= PPB_SPP; 702 if (bootverbose) 703 printf(" SPP"); 704 break; 705 706 case SMC_EPPSPP: 707 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 708 if (bootverbose) 709 printf(" EPP SPP"); 710 break; 711 712 case SMC_ECP: 713 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 714 if (bootverbose) 715 printf(" ECP SPP"); 716 break; 717 718 case SMC_ECPEPP: 719 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 720 if (bootverbose) 721 printf(" ECP+EPP SPP"); 722 break; 723 } 724 } else { 725 /* not an extended port mode */ 726 ppc->ppc_avm |= PPB_SPP; 727 if (bootverbose) 728 printf(" SPP"); 729 } 730 731 } else { 732 /* mode forced */ 733 ppc->ppc_avm = chipset_mode; 734 735 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 736 if (type == SMC_37C666GT) 737 goto end_detect; 738 739 r = inb(cio); 740 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 741 /* do not use ECP when the mode is not forced to */ 742 outb(cio, r | SMC_CR1_MODE); 743 if (bootverbose) 744 printf(" SPP"); 745 } else { 746 /* an extended mode is selected */ 747 outb(cio, r & ~SMC_CR1_MODE); 748 749 /* read CR4 register and reset mode field */ 750 outb(csr, 0x4); 751 r = inb(cio) & ~SMC_CR4_EMODE; 752 753 if (chipset_mode & PPB_ECP) { 754 if (chipset_mode & PPB_EPP) { 755 outb(cio, r | SMC_ECPEPP); 756 if (bootverbose) 757 printf(" ECP+EPP"); 758 } else { 759 outb(cio, r | SMC_ECP); 760 if (bootverbose) 761 printf(" ECP"); 762 } 763 } else { 764 /* PPB_EPP is set */ 765 outb(cio, r | SMC_EPPSPP); 766 if (bootverbose) 767 printf(" EPP SPP"); 768 } 769 } 770 ppc->ppc_avm = chipset_mode; 771 } 772 773 /* set FIFO threshold to 16 */ 774 if (ppc->ppc_avm & PPB_ECP) { 775 /* select CRA */ 776 outb(csr, 0xa); 777 outb(cio, 16); 778 } 779 780end_detect: 781 782 if (bootverbose) 783 printf ("\n"); 784 785 if (ppc->ppc_avm & PPB_EPP) { 786 /* select CR4 */ 787 outb(csr, 0x4); 788 r = inb(cio); 789 790 /* 791 * Set the EPP protocol... 792 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 793 */ 794 if (ppc->ppc_epp == EPP_1_9) 795 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 796 else 797 outb(cio, (r | SMC_CR4_EPPTYPE)); 798 } 799 800 /* end config mode */ 801 outb(csr, 0xaa); 802 803 ppc->ppc_link.adapter = &ppc_smclike_adapter; 804 ppc_smclike_setmode(ppc->ppc_unit, chipset_mode); 805 806 return (chipset_mode); 807} 808 809/* 810 * Winbond W83877F stuff 811 * 812 * EFER: extended function enable register 813 * EFIR: extended function index register 814 * EFDR: extended function data register 815 */ 816#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 817#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 818 819static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 820static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 821static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 822static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 823 824static int 825ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 826{ 827 int i, j, efer; 828 unsigned char r, hefere, hefras; 829 830 for (i = 0; i < 4; i ++) { 831 /* first try to enable configuration registers */ 832 efer = w83877f_efers[i]; 833 834 /* write the key to the EFER */ 835 for (j = 0; j < w83877f_keyiter[i]; j ++) 836 outb (efer, w83877f_keys[i]); 837 838 /* then check HEFERE and HEFRAS bits */ 839 outb (efir, 0x0c); 840 hefere = inb(efdr) & WINB_HEFERE; 841 842 outb (efir, 0x16); 843 hefras = inb(efdr) & WINB_HEFRAS; 844 845 /* 846 * HEFRAS HEFERE 847 * 0 1 write 89h to 250h (power-on default) 848 * 1 0 write 86h twice to 3f0h 849 * 1 1 write 87h twice to 3f0h 850 * 0 0 write 88h to 250h 851 */ 852 if ((hefere | hefras) == w83877f_hefs[i]) 853 goto found; 854 } 855 856 return (-1); /* failed */ 857 858found: 859 /* check base port address - read from CR23 */ 860 outb(efir, 0x23); 861 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 862 return (-1); 863 864 /* read CHIP ID from CR9/bits0-3 */ 865 outb(efir, 0x9); 866 867 switch (inb(efdr) & WINB_CHIPID) { 868 case WINB_W83877F_ID: 869 ppc->ppc_type = WINB_W83877F; 870 break; 871 872 case WINB_W83877AF_ID: 873 ppc->ppc_type = WINB_W83877AF; 874 break; 875 876 default: 877 ppc->ppc_type = WINB_UNKNOWN; 878 } 879 880 if (bootverbose) { 881 /* dump of registers */ 882 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 883 for (i = 0; i <= 0xd; i ++) { 884 outb(efir, i); 885 printf("0x%x ", inb(efdr)); 886 } 887 for (i = 0x10; i <= 0x17; i ++) { 888 outb(efir, i); 889 printf("0x%x ", inb(efdr)); 890 } 891 outb(efir, 0x1e); 892 printf("0x%x ", inb(efdr)); 893 for (i = 0x20; i <= 0x29; i ++) { 894 outb(efir, i); 895 printf("0x%x ", inb(efdr)); 896 } 897 printf("\n"); 898 printf("ppc%d:", ppc->ppc_unit); 899 } 900 901 ppc->ppc_link.adapter = &ppc_generic_adapter; 902 903 if (!chipset_mode) { 904 /* autodetect mode */ 905 906 /* select CR0 */ 907 outb(efir, 0x0); 908 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 909 910 /* select CR9 */ 911 outb(efir, 0x9); 912 r |= (inb(efdr) & WINB_PRTMODS2); 913 914 switch (r) { 915 case WINB_W83757: 916 if (bootverbose) 917 printf("ppc%d: W83757 compatible mode\n", 918 ppc->ppc_unit); 919 return (-1); /* generic or SMC-like */ 920 921 case WINB_EXTFDC: 922 case WINB_EXTADP: 923 case WINB_EXT2FDD: 924 case WINB_JOYSTICK: 925 if (bootverbose) 926 printf(" not in parallel port mode\n"); 927 return (-1); 928 929 case (WINB_PARALLEL | WINB_EPP_SPP): 930 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 931 if (bootverbose) 932 printf(" EPP SPP"); 933 break; 934 935 case (WINB_PARALLEL | WINB_ECP): 936 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 937 if (bootverbose) 938 printf(" ECP SPP"); 939 break; 940 941 case (WINB_PARALLEL | WINB_ECP_EPP): 942 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 943 ppc->ppc_link.adapter = &ppc_smclike_adapter; 944 945 if (bootverbose) 946 printf(" ECP+EPP SPP"); 947 break; 948 default: 949 printf("%s: unknown case (0x%x)!\n", __FUNCTION__, r); 950 } 951 952 } else { 953 /* mode forced */ 954 955 /* select CR9 and set PRTMODS2 bit */ 956 outb(efir, 0x9); 957 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 958 959 /* select CR0 and reset PRTMODSx bits */ 960 outb(efir, 0x0); 961 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 962 963 if (chipset_mode & PPB_ECP) { 964 if (chipset_mode & PPB_EPP) { 965 outb(efdr, inb(efdr) | WINB_ECP_EPP); 966 if (bootverbose) 967 printf(" ECP+EPP"); 968 969 ppc->ppc_link.adapter = &ppc_smclike_adapter; 970 971 } else { 972 outb(efdr, inb(efdr) | WINB_ECP); 973 if (bootverbose) 974 printf(" ECP"); 975 } 976 } else { 977 /* select EPP_SPP otherwise */ 978 outb(efdr, inb(efdr) | WINB_EPP_SPP); 979 if (bootverbose) 980 printf(" EPP SPP"); 981 } 982 ppc->ppc_avm = chipset_mode; 983 } 984 985 if (bootverbose) 986 printf("\n"); 987 988 /* exit configuration mode */ 989 outb(efer, 0xaa); 990 991 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 992 993 return (chipset_mode); 994} 995 996/* 997 * ppc_generic_detect 998 */ 999static int 1000ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1001{ 1002 /* default to generic */ 1003 ppc->ppc_link.adapter = &ppc_generic_adapter; 1004 1005 if (bootverbose) 1006 printf("ppc%d:", ppc->ppc_unit); 1007 1008 if (!chipset_mode) { 1009 /* first, check for ECP */ 1010 w_ecr(ppc, PPC_ECR_PS2); 1011 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1012 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1013 if (bootverbose) 1014 printf(" ECP SPP"); 1015 1016 /* search for SMC style ECP+EPP mode */ 1017 w_ecr(ppc, PPC_ECR_EPP); 1018 } 1019 1020 /* try to reset EPP timeout bit */ 1021 if (ppc_check_epp_timeout(ppc)) { 1022 ppc->ppc_avm |= PPB_EPP; 1023 1024 if (ppc->ppc_avm & PPB_ECP) { 1025 /* SMC like chipset found */ 1026 ppc->ppc_type = SMC_LIKE; 1027 ppc->ppc_link.adapter = &ppc_smclike_adapter; 1028 1029 if (bootverbose) 1030 printf(" ECP+EPP"); 1031 } else { 1032 if (bootverbose) 1033 printf(" EPP"); 1034 } 1035 } else { 1036 /* restore to standard mode */ 1037 w_ecr(ppc, PPC_ECR_STD); 1038 } 1039 1040 /* XXX try to detect NIBBLE and PS2 modes */ 1041 ppc->ppc_avm |= PPB_NIBBLE; 1042 1043 if (bootverbose) 1044 printf(" SPP"); 1045 1046 } else { 1047 ppc->ppc_avm = chipset_mode; 1048 } 1049 1050 if (bootverbose) 1051 printf("\n"); 1052 1053 ppc->ppc_link.adapter->setmode(ppc->ppc_unit, chipset_mode); 1054 1055 return (chipset_mode); 1056} 1057 1058/* 1059 * ppc_detect() 1060 * 1061 * mode is the mode suggested at boot 1062 */ 1063static int 1064ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1065 1066 int i, mode; 1067 1068 /* list of supported chipsets */ 1069 int (*chipset_detect[])(struct ppc_data *, int) = { 1070 ppc_pc873xx_detect, 1071 ppc_smc37c66xgt_detect, 1072 ppc_w83877f_detect, 1073 ppc_generic_detect, 1074 NULL 1075 }; 1076 1077 /* if can't find the port and mode not forced return error */ 1078 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1079 return (EIO); /* failed, port not present */ 1080 1081 /* assume centronics compatible mode is supported */ 1082 ppc->ppc_avm = PPB_COMPATIBLE; 1083 1084 /* we have to differenciate available chipset modes, 1085 * chipset running modes and IEEE-1284 operating modes 1086 * 1087 * after detection, the port must support running in compatible mode 1088 */ 1089 if (ppc->ppc_flags & 0x40) { 1090 if (bootverbose) 1091 printf("ppc: chipset forced to generic\n"); 1092 1093 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1094 1095 } else { 1096 for (i=0; chipset_detect[i] != NULL; i++) { 1097 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1098 ppc->ppc_mode = mode; 1099 break; 1100 } 1101 } 1102 } 1103 1104 /* configure/detect ECP FIFO */ 1105 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1106 ppc_detect_fifo(ppc); 1107 1108 return (0); 1109} 1110 1111/* 1112 * ppc_exec_microseq() 1113 * 1114 * Execute a microsequence. 1115 * Microsequence mechanism is supposed to handle fast I/O operations. 1116 */ 1117static int 1118ppc_exec_microseq(int unit, struct ppb_microseq **p_msq) 1119{ 1120 struct ppc_data *ppc = ppcdata[unit]; 1121 struct ppb_microseq *mi; 1122 char cc, *p; 1123 int i, iter, len; 1124 int error; 1125 1126 register int reg; 1127 register char mask; 1128 register int accum = 0; 1129 register char *ptr = 0; 1130 1131 struct ppb_microseq *stack = 0; 1132 1133/* microsequence registers are equivalent to PC-like port registers */ 1134#define r_reg(register,ppc) (inb((ppc)->ppc_base + register)) 1135#define w_reg(register,ppc,byte) outb((ppc)->ppc_base + register, byte) 1136 1137#define INCR_PC (mi ++) /* increment program counter */ 1138 1139 mi = *p_msq; 1140 for (;;) { 1141 switch (mi->opcode) { 1142 case MS_OP_RSET: 1143 cc = r_reg(mi->arg[0].i, ppc); 1144 cc &= (char)mi->arg[2].i; /* clear mask */ 1145 cc |= (char)mi->arg[1].i; /* assert mask */ 1146 w_reg(mi->arg[0].i, ppc, cc); 1147 INCR_PC; 1148 break; 1149 1150 case MS_OP_RASSERT_P: 1151 reg = mi->arg[1].i; 1152 ptr = ppc->ppc_ptr; 1153 1154 if ((len = mi->arg[0].i) == MS_ACCUM) { 1155 accum = ppc->ppc_accum; 1156 for (; accum; accum--) 1157 w_reg(reg, ppc, *ptr++); 1158 ppc->ppc_accum = accum; 1159 } else 1160 for (i=0; i<len; i++) 1161 w_reg(reg, ppc, *ptr++); 1162 ppc->ppc_ptr = ptr; 1163 1164 INCR_PC; 1165 break; 1166 1167 case MS_OP_RFETCH_P: 1168 reg = mi->arg[1].i; 1169 mask = (char)mi->arg[2].i; 1170 ptr = ppc->ppc_ptr; 1171 1172 if ((len = mi->arg[0].i) == MS_ACCUM) { 1173 accum = ppc->ppc_accum; 1174 for (; accum; accum--) 1175 *ptr++ = r_reg(reg, ppc) & mask; 1176 ppc->ppc_accum = accum; 1177 } else 1178 for (i=0; i<len; i++) 1179 *ptr++ = r_reg(reg, ppc) & mask; 1180 ppc->ppc_ptr = ptr; 1181 1182 INCR_PC; 1183 break; 1184 1185 case MS_OP_RFETCH: 1186 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1187 (char)mi->arg[1].i; 1188 INCR_PC; 1189 break; 1190 1191 case MS_OP_RASSERT: 1192 case MS_OP_DELAY: 1193 1194 /* let's suppose the next instr. is the same */ 1195 prefetch: 1196 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1197 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1198 1199 if (mi->opcode == MS_OP_DELAY) { 1200 DELAY(mi->arg[0].i); 1201 INCR_PC; 1202 goto prefetch; 1203 } 1204 break; 1205 1206 case MS_OP_ADELAY: 1207 if (mi->arg[0].i) 1208 tsleep(NULL, PPBPRI, "ppbdelay", 1209 mi->arg[0].i * (hz/1000)); 1210 INCR_PC; 1211 break; 1212 1213 case MS_OP_TRIG: 1214 reg = mi->arg[0].i; 1215 iter = mi->arg[1].i; 1216 p = (char *)mi->arg[2].p; 1217 1218 /* XXX delay limited to 255 us */ 1219 for (i=0; i<iter; i++) { 1220 w_reg(reg, ppc, *p++); 1221 DELAY((unsigned char)*p++); 1222 } 1223 INCR_PC; 1224 break; 1225 1226 case MS_OP_SET: 1227 ppc->ppc_accum = mi->arg[0].i; 1228 INCR_PC; 1229 break; 1230 1231 case MS_OP_DBRA: 1232 if (--ppc->ppc_accum > 0) 1233 mi += mi->arg[0].i; 1234 INCR_PC; 1235 break; 1236 1237 case MS_OP_BRSET: 1238 cc = r_str(ppc); 1239 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1240 mi += mi->arg[1].i; 1241 INCR_PC; 1242 break; 1243 1244 case MS_OP_BRCLEAR: 1245 cc = r_str(ppc); 1246 if ((cc & (char)mi->arg[0].i) == 0) 1247 mi += mi->arg[1].i; 1248 INCR_PC; 1249 break; 1250 1251 case MS_OP_BRSTAT: 1252 cc = r_str(ppc); 1253 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1254 (char)mi->arg[0].i) 1255 mi += mi->arg[2].i; 1256 INCR_PC; 1257 break; 1258 1259 case MS_OP_C_CALL: 1260 /* 1261 * If the C call returns !0 then end the microseq. 1262 * The current state of ptr is passed to the C function 1263 */ 1264 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1265 return (error); 1266 1267 INCR_PC; 1268 break; 1269 1270 case MS_OP_PTR: 1271 ppc->ppc_ptr = (char *)mi->arg[0].p; 1272 INCR_PC; 1273 break; 1274 1275 case MS_OP_CALL: 1276 if (stack) 1277 panic("%s: too much calls", __FUNCTION__); 1278 1279 if (mi->arg[0].p) { 1280 /* store the state of the actual 1281 * microsequence 1282 */ 1283 stack = mi; 1284 1285 /* jump to the new microsequence */ 1286 mi = (struct ppb_microseq *)mi->arg[0].p; 1287 } else 1288 INCR_PC; 1289 1290 break; 1291 1292 case MS_OP_SUBRET: 1293 /* retrieve microseq and pc state before the call */ 1294 mi = stack; 1295 1296 /* reset the stack */ 1297 stack = 0; 1298 1299 /* XXX return code */ 1300 1301 INCR_PC; 1302 break; 1303 1304 case MS_OP_PUT: 1305 case MS_OP_GET: 1306 case MS_OP_RET: 1307 /* can't return to ppb level during the execution 1308 * of a submicrosequence */ 1309 if (stack) 1310 panic("%s: can't return to ppb level", 1311 __FUNCTION__); 1312 1313 /* update pc for ppb level of execution */ 1314 *p_msq = mi; 1315 1316 /* return to ppb level of execution */ 1317 return (0); 1318 1319 default: 1320 panic("%s: unknown microsequence opcode 0x%x", 1321 __FUNCTION__, mi->opcode); 1322 } 1323 } 1324 1325 /* unreached */ 1326} 1327 1328static void 1329ppcintr(int unit) 1330{ 1331 struct ppc_data *ppc = ppcdata[unit]; 1332 u_char ctr, ecr, str; 1333 1334 str = r_str(ppc); 1335 ctr = r_ctr(ppc); 1336 ecr = r_ecr(ppc); 1337 1338#if PPC_DEBUG > 1 1339 printf("![%x/%x/%x]", ctr, ecr, str); 1340#endif 1341 1342 /* don't use ecp mode with IRQENABLE set */ 1343 if (ctr & IRQENABLE) { 1344 /* call upper code */ 1345 ppb_intr(&ppc->ppc_link); 1346 return; 1347 } 1348 1349 /* interrupts are generated by nFault signal 1350 * only in ECP mode */ 1351 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1352 /* check if ppc driver has programmed the 1353 * nFault interrupt */ 1354 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1355 1356 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1357 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1358 } else { 1359 /* call upper code */ 1360 ppb_intr(&ppc->ppc_link); 1361 return; 1362 } 1363 } 1364 1365 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1366 /* disable interrupts (should be done by hardware though) */ 1367 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1368 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1369 ecr = r_ecr(ppc); 1370 1371 /* check if DMA completed */ 1372 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1373#ifdef PPC_DEBUG 1374 printf("a"); 1375#endif 1376 /* stop DMA */ 1377 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1378 ecr = r_ecr(ppc); 1379 1380 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1381#ifdef PPC_DEBUG 1382 printf("d"); 1383#endif 1384 isa_dmadone( 1385 ppc->ppc_dmaflags, 1386 ppc->ppc_dmaddr, 1387 ppc->ppc_dmacnt, 1388 ppc->ppc_dmachan); 1389 1390 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1391 1392 /* wakeup the waiting process */ 1393 wakeup((caddr_t)ppc); 1394 } 1395 } 1396 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1397 1398 /* classic interrupt I/O */ 1399 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1400 1401 } 1402 1403 return; 1404} 1405 1406static int 1407ppc_read(int unit, char *buf, int len, int mode) 1408{ 1409 return (EINVAL); 1410} 1411 1412/* 1413 * Call this function if you want to send data in any advanced mode 1414 * of your parallel port: FIFO, DMA 1415 * 1416 * If what you want is not possible (no ECP, no DMA...), 1417 * EINVAL is returned 1418 */ 1419static int 1420ppc_write(int unit, char *buf, int len, int how) 1421{ 1422 struct ppc_data *ppc = ppcdata[unit]; 1423 char ecr, ecr_sav, ctr, ctr_sav; 1424 int s, error = 0; 1425 int spin; 1426 1427#ifdef PPC_DEBUG 1428 printf("w"); 1429#endif 1430 1431 ecr_sav = r_ecr(ppc); 1432 ctr_sav = r_ctr(ppc); 1433 1434 /* 1435 * Send buffer with DMA, FIFO and interrupts 1436 */ 1437 if (ppc->ppc_avm & PPB_ECP) { 1438 1439 if (ppc->ppc_dmachan >= 0) { 1440 1441 /* byte mode, no intr, no DMA, dir=0, flush fifo 1442 */ 1443 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1444 w_ecr(ppc, ecr); 1445 1446 /* disable nAck interrupts */ 1447 ctr = r_ctr(ppc); 1448 ctr &= ~IRQENABLE; 1449 w_ctr(ppc, ctr); 1450 1451 ppc->ppc_dmaflags = 0; 1452 ppc->ppc_dmaddr = (caddr_t)buf; 1453 ppc->ppc_dmacnt = (u_int)len; 1454 1455 switch (ppc->ppc_mode) { 1456 case PPB_COMPATIBLE: 1457 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1458 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1459 break; 1460 case PPB_ECP: 1461 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1462 break; 1463 default: 1464 error = EINVAL; 1465 goto error; 1466 } 1467 1468 w_ecr(ppc, ecr); 1469 ecr = r_ecr(ppc); 1470 1471 /* enter splhigh() not to be preempted 1472 * by the dma interrupt, we may miss 1473 * the wakeup otherwise 1474 */ 1475 s = splhigh(); 1476 1477 ppc->ppc_dmastat = PPC_DMA_INIT; 1478 1479 /* enable interrupts */ 1480 ecr &= ~PPC_SERVICE_INTR; 1481 ppc->ppc_irqstat = PPC_IRQ_DMA; 1482 w_ecr(ppc, ecr); 1483 1484 isa_dmastart( 1485 ppc->ppc_dmaflags, 1486 ppc->ppc_dmaddr, 1487 ppc->ppc_dmacnt, 1488 ppc->ppc_dmachan); 1489#ifdef PPC_DEBUG 1490 printf("s%d", ppc->ppc_dmacnt); 1491#endif 1492 ppc->ppc_dmastat = PPC_DMA_STARTED; 1493 1494 /* Wait for the DMA completed interrupt. We hope we won't 1495 * miss it, otherwise a signal will be necessary to unlock the 1496 * process. 1497 */ 1498 do { 1499 /* release CPU */ 1500 error = tsleep((caddr_t)ppc, 1501 PPBPRI | PCATCH, "ppcdma", 0); 1502 1503 } while (error == EWOULDBLOCK); 1504 1505 splx(s); 1506 1507 if (error) { 1508#ifdef PPC_DEBUG 1509 printf("i"); 1510#endif 1511 /* stop DMA */ 1512 isa_dmadone( 1513 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1514 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1515 1516 /* no dma, no interrupt, flush the fifo */ 1517 w_ecr(ppc, PPC_ECR_RESET); 1518 1519 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1520 goto error; 1521 } 1522 1523 /* wait for an empty fifo */ 1524 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1525 1526 for (spin=100; spin; spin--) 1527 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1528 goto fifo_empty; 1529#ifdef PPC_DEBUG 1530 printf("Z"); 1531#endif 1532 error = tsleep((caddr_t)ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1533 if (error != EWOULDBLOCK) { 1534#ifdef PPC_DEBUG 1535 printf("I"); 1536#endif 1537 /* no dma, no interrupt, flush the fifo */ 1538 w_ecr(ppc, PPC_ECR_RESET); 1539 1540 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1541 error = EINTR; 1542 goto error; 1543 } 1544 } 1545 1546fifo_empty: 1547 /* no dma, no interrupt, flush the fifo */ 1548 w_ecr(ppc, PPC_ECR_RESET); 1549 1550 } else 1551 error = EINVAL; /* XXX we should FIFO and 1552 * interrupts */ 1553 } else 1554 error = EINVAL; 1555 1556error: 1557 1558 /* PDRQ must be kept unasserted until nPDACK is 1559 * deasserted for a minimum of 350ns (SMC datasheet) 1560 * 1561 * Consequence may be a FIFO that never empty 1562 */ 1563 DELAY(1); 1564 1565 w_ecr(ppc, ecr_sav); 1566 w_ctr(ppc, ctr_sav); 1567 1568 return (error); 1569} 1570 1571/* 1572 * Configure current operating mode 1573 */ 1574static int 1575ppc_generic_setmode(int unit, int mode) 1576{ 1577 struct ppc_data *ppc = ppcdata[unit]; 1578 u_char ecr = 0; 1579 1580 /* check if mode is available */ 1581 if (mode && !(ppc->ppc_avm & mode)) 1582 return (EINVAL); 1583 1584 /* if ECP mode, configure ecr register */ 1585 if (ppc->ppc_avm & PPB_ECP) { 1586 /* return to byte mode (keeping direction bit), 1587 * no interrupt, no DMA to be able to change to 1588 * ECP 1589 */ 1590 w_ecr(ppc, PPC_ECR_RESET); 1591 ecr = PPC_DISABLE_INTR; 1592 1593 if (mode & PPB_EPP) 1594 return (EINVAL); 1595 else if (mode & PPB_ECP) 1596 /* select ECP mode */ 1597 ecr |= PPC_ECR_ECP; 1598 else if (mode & PPB_PS2) 1599 /* select PS2 mode with ECP */ 1600 ecr |= PPC_ECR_PS2; 1601 else 1602 /* select COMPATIBLE/NIBBLE mode */ 1603 ecr |= PPC_ECR_STD; 1604 1605 w_ecr(ppc, ecr); 1606 } 1607 1608 ppc->ppc_mode = mode; 1609 1610 return (0); 1611} 1612 1613/* 1614 * The ppc driver is free to choose options like FIFO or DMA 1615 * if ECP mode is available. 1616 * 1617 * The 'RAW' option allows the upper drivers to force the ppc mode 1618 * even with FIFO, DMA available. 1619 */ 1620int 1621ppc_smclike_setmode(int unit, int mode) 1622{ 1623 struct ppc_data *ppc = ppcdata[unit]; 1624 u_char ecr = 0; 1625 1626 /* check if mode is available */ 1627 if (mode && !(ppc->ppc_avm & mode)) 1628 return (EINVAL); 1629 1630 /* if ECP mode, configure ecr register */ 1631 if (ppc->ppc_avm & PPB_ECP) { 1632 /* return to byte mode (keeping direction bit), 1633 * no interrupt, no DMA to be able to change to 1634 * ECP or EPP mode 1635 */ 1636 w_ecr(ppc, PPC_ECR_RESET); 1637 ecr = PPC_DISABLE_INTR; 1638 1639 if (mode & PPB_EPP) 1640 /* select EPP mode */ 1641 ecr |= PPC_ECR_EPP; 1642 else if (mode & PPB_ECP) 1643 /* select ECP mode */ 1644 ecr |= PPC_ECR_ECP; 1645 else if (mode & PPB_PS2) 1646 /* select PS2 mode with ECP */ 1647 ecr |= PPC_ECR_PS2; 1648 else 1649 /* select COMPATIBLE/NIBBLE mode */ 1650 ecr |= PPC_ECR_STD; 1651 1652 w_ecr(ppc, ecr); 1653 } 1654 1655 ppc->ppc_mode = mode; 1656 1657 return (0); 1658} 1659 1660/* 1661 * EPP timeout, according to the PC87332 manual 1662 * Semantics of clearing EPP timeout bit. 1663 * PC87332 - reading SPP_STR does it... 1664 * SMC - write 1 to EPP timeout bit XXX 1665 * Others - (?) write 0 to EPP timeout bit 1666 */ 1667static void 1668ppc_reset_epp_timeout(int unit) 1669{ 1670 struct ppc_data *ppc = ppcdata[unit]; 1671 register char r; 1672 1673 r = r_str(ppc); 1674 w_str(ppc, r | 0x1); 1675 w_str(ppc, r & 0xfe); 1676 1677 return; 1678} 1679 1680static int 1681ppcprobe(struct isa_device *dvp) 1682{ 1683 static short next_bios_ppc = 0; 1684 struct ppc_data *ppc; 1685 1686 /* 1687 * If port not specified, use bios list. 1688 */ 1689 if(dvp->id_iobase < 0) { 1690 if((next_bios_ppc < BIOS_MAX_PPC) && 1691 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1692 dvp->id_iobase = *(BIOS_PORTS+next_bios_ppc++); 1693 if (bootverbose) 1694 printf("ppc: parallel port found at 0x%x\n", 1695 dvp->id_iobase); 1696 } else 1697 return (0); 1698 } 1699 1700 /* 1701 * Port was explicitly specified. 1702 * This allows probing of ports unknown to the BIOS. 1703 */ 1704 1705 /* 1706 * Allocate the ppc_data structure. 1707 */ 1708 ppc = malloc(sizeof(struct ppc_data), M_DEVBUF, M_NOWAIT); 1709 if (!ppc) { 1710 printf("ppc: cannot malloc!\n"); 1711 goto error; 1712 } 1713 bzero(ppc, sizeof(struct ppc_data)); 1714 1715 ppc->ppc_base = dvp->id_iobase; 1716 ppc->ppc_unit = dvp->id_unit; 1717 ppc->ppc_type = GENERIC; 1718 1719 /* store boot flags */ 1720 ppc->ppc_flags = dvp->id_flags; 1721 1722 ppc->ppc_mode = PPB_COMPATIBLE; 1723 ppc->ppc_epp = (dvp->id_flags & 0x10) >> 4; 1724 1725 /* 1726 * XXX Try and detect if interrupts are working 1727 */ 1728 if (!(dvp->id_flags & 0x20) && dvp->id_irq) 1729 ppc->ppc_irq = ffs(dvp->id_irq) - 1; 1730 1731 ppc->ppc_dmachan = dvp->id_drq; 1732 1733 ppcdata[ppc->ppc_unit] = ppc; 1734 nppc ++; 1735 1736 /* 1737 * Link the Parallel Port Chipset (adapter) to 1738 * the future ppbus. Default to a generic chipset 1739 */ 1740 ppc->ppc_link.adapter_unit = ppc->ppc_unit; 1741 ppc->ppc_link.adapter = &ppc_generic_adapter; 1742 1743 /* 1744 * Try to detect the chipset and its mode. 1745 */ 1746 if (ppc_detect(ppc, dvp->id_flags & 0xf)) 1747 goto error; 1748 1749 return (IO_LPTSIZE); 1750 1751error: 1752 return (0); 1753} 1754 1755static int 1756ppcattach(struct isa_device *isdp) 1757{ 1758 struct ppc_data *ppc = ppcdata[isdp->id_unit]; 1759 struct ppb_data *ppbus; 1760 1761 printf("ppc%d: %s chipset (%s) in %s mode%s\n", ppc->ppc_unit, 1762 ppc_types[ppc->ppc_type], ppc_avms[ppc->ppc_avm], 1763 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1764 ppc_epp_protocol[ppc->ppc_epp] : ""); 1765 1766 if (ppc->ppc_fifo) 1767 printf("ppc%d: FIFO with %d/%d/%d bytes threshold\n", 1768 ppc->ppc_unit, ppc->ppc_fifo, ppc->ppc_wthr, 1769 ppc->ppc_rthr); 1770 1771 isdp->id_ointr = ppcintr; 1772 1773 /* 1774 * Prepare ppbus data area for upper level code. 1775 */ 1776 ppbus = ppb_alloc_bus(); 1777 1778 if (!ppbus) 1779 return (0); 1780 1781 ppc->ppc_link.ppbus = ppbus; 1782 ppbus->ppb_link = &ppc->ppc_link; 1783 1784 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1785 1786 /* acquire the DMA channel forever */ 1787 isa_dma_acquire(ppc->ppc_dmachan); 1788 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1789 } 1790 1791 /* 1792 * Probe the ppbus and attach devices found. 1793 */ 1794 ppb_attachdevs(ppbus); 1795 1796 return (1); 1797} 1798#endif 1799