ppc.c revision 28221
1/*- 2 * Copyright (c) 1997 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id$ 27 * 28 */ 29#include "ppc.h" 30 31#if NPPC > 0 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/errno.h> 36#include <sys/conf.h> 37#include <sys/proc.h> 38#include <sys/buf.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/uio.h> 42#include <sys/syslog.h> 43 44#include <machine/clock.h> 45 46#include <vm/vm.h> 47#include <vm/vm_param.h> 48#include <vm/pmap.h> 49 50#include <i386/isa/isa.h> 51#include <i386/isa/isa_device.h> 52 53#include <dev/ppbus/ppbconf.h> 54#include <i386/isa/ppcreg.h> 55 56static int ppcprobe(struct isa_device *); 57static int ppcattach(struct isa_device *); 58 59struct isa_driver ppcdriver = { 60 ppcprobe, ppcattach, "ppc" 61}; 62 63static struct ppc_data *ppcdata[NPPC]; 64static int nppc = 0; 65 66static char *ppc_types[] = { 67 "SMC", "SMC FDC37C665GT", "SMC FDC37C666GT", 68 "NatSemi", "PC87332", "PC87306", 69 "Intel 82091AA", "Generic", 0 70}; 71 72static char *ppc_modes[] = { 73 "AUTODETECT", "NIBBLE", "PS/2", "EPP", "ECP+EPP", "ECP+PS/2", "ECP", 74 "UNKNOWN", 0 75}; 76 77static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 78 79/* 80 * BIOS printer list - used by BIOS probe. 81 */ 82#define BIOS_PPC_PORTS 0x408 83#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 84#define BIOS_MAX_PPC 4 85 86/* 87 * All these functions are default actions for IN/OUT operations. 88 * They may be redefined if needed. 89 */ 90static void ppc_outsb_epp(int unit, char *addr, int cnt) { 91 outsb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 92static void ppc_outsw_epp(int unit, char *addr, int cnt) { 93 outsw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 94static void ppc_outsl_epp(int unit, char *addr, int cnt) { 95 outsl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 96static void ppc_insb_epp(int unit, char *addr, int cnt) { 97 insb(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 98static void ppc_insw_epp(int unit, char *addr, int cnt) { 99 insw(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 100static void ppc_insl_epp(int unit, char *addr, int cnt) { 101 insl(ppcdata[unit]->ppc_base + PPC_EPP_DATA, addr, cnt); } 102 103static char ppc_rdtr(int unit) { return r_dtr(ppcdata[unit]); } 104static char ppc_rstr(int unit) { return r_str(ppcdata[unit]); } 105static char ppc_rctr(int unit) { return r_ctr(ppcdata[unit]); } 106static char ppc_repp(int unit) { return r_epp(ppcdata[unit]); } 107static char ppc_recr(int unit) { return r_ecr(ppcdata[unit]); } 108static char ppc_rfifo(int unit) { return r_fifo(ppcdata[unit]); } 109 110static void ppc_wdtr(int unit, char byte) { w_dtr(ppcdata[unit], byte); } 111static void ppc_wstr(int unit, char byte) { w_str(ppcdata[unit], byte); } 112static void ppc_wctr(int unit, char byte) { w_ctr(ppcdata[unit], byte); } 113static void ppc_wepp(int unit, char byte) { w_epp(ppcdata[unit], byte); } 114static void ppc_wecr(int unit, char byte) { w_ecr(ppcdata[unit], byte); } 115static void ppc_wfifo(int unit, char byte) { w_fifo(ppcdata[unit], byte); } 116 117static void ppc_reset_epp_timeout(int); 118static void ppc_ecp_sync(int); 119 120static struct ppb_adapter ppc_adapter = { 121 122 0, /* no intr handler, filled by chipset dependent code */ 123 124 ppc_reset_epp_timeout, ppc_ecp_sync, 125 126 ppc_outsb_epp, ppc_outsw_epp, ppc_outsl_epp, 127 ppc_insb_epp, ppc_insw_epp, ppc_insl_epp, 128 129 ppc_rdtr, ppc_rstr, ppc_rctr, ppc_repp, ppc_recr, ppc_rfifo, 130 ppc_wdtr, ppc_wstr, ppc_wctr, ppc_wepp, ppc_wecr, ppc_wfifo 131}; 132 133/* 134 * ppc_ecp_sync() XXX 135 */ 136static void 137ppc_ecp_sync(int unit) { 138 139 struct ppc_data *ppc = ppcdata[unit]; 140 int i, r; 141 142 r = r_ecr(ppc); 143 if ((r & 0xe0) != 0x80) 144 return; 145 146 for (i = 0; i < 100; i++) { 147 r = r_ecr(ppc); 148 if (r & 0x1) 149 return; 150 DELAY(100); 151 } 152 153 printf("ppc: ECP sync failed as data still " \ 154 "present in FIFO.\n"); 155 156 return; 157} 158 159void 160ppcintr(int unit) 161{ 162 /* call directly upper code */ 163 ppb_intr(&ppcdata[unit]->ppc_link); 164 165 return; 166} 167 168/* 169 * ppc_pc873xx_detect 170 * 171 * Probe for a Natsemi PC873xx-family part. 172 * 173 * References in this function are to the National Semiconductor 174 * PC87332 datasheet TL/C/11930, May 1995 revision. 175 */ 176static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 177static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 178 179static int 180ppc_pc873xx_detect(struct ppc_data *ppc) 181{ 182 static int index = 0; 183 int base, idport; 184 int val, mode; 185 186 while ((idport = pc873xx_basetab[index++])) { 187 188 /* XXX should check first to see if this location is already claimed */ 189 190 /* 191 * Pull the 873xx through the power-on ID cycle (2.2,1.). We can't use this 192 * to locate the chip as it may already have been used by the BIOS. 193 */ 194 (void)inb(idport); (void)inb(idport); (void)inb(idport); (void)inb(idport); 195 196 /* 197 * Read the SID byte. Possible values are : 198 * 199 * 0001xxxx PC87332 200 * 01110xxx PC87306 201 */ 202 outb(idport, PC873_SID); 203 val = inb(idport + 1); 204 if ((val & 0xf0) == 0x10) { 205 ppc->ppc_type = NS_PC87332; 206 } else if ((val & 0xf8) == 0x70) { 207 ppc->ppc_type = NS_PC87306; 208 } else { 209 if (bootverbose && (val != 0xff)) 210 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 211 continue ; /* not recognised */ 212 } 213 214 /* 215 * We think we have one. Is it enabled and where we want it to be? 216 */ 217 outb(idport, PC873_FER); 218 val = inb(idport + 1); 219 if (!(val & PC873_PPENABLE)) { 220 if (bootverbose) 221 printf("PC873xx parallel port disabled\n"); 222 continue; 223 } 224 outb(idport, PC873_FAR); 225 val = inb(idport + 1) & 0x3; 226 /* XXX we should create a driver instance for every port found */ 227 if (pc873xx_porttab[val] != ppc->ppc_base) { 228 if (bootverbose) 229 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 230 pc873xx_porttab[val], ppc->ppc_base); 231 continue; 232 } 233 234 /* 235 * This is the port we want. Can we dink with it to improve 236 * our chances? 237 */ 238 outb(idport, PC873_PTR); 239 val = inb(idport + 1); 240 if (val & PC873_CFGLOCK) { 241 if (bootverbose) 242 printf("PC873xx locked\n"); 243 244 /* work out what mode we're in */ 245 mode = PPB_NIBBLE; /* worst case */ 246 247 outb(idport, PC873_PCR); 248 val = inb(idport + 1); 249 if ((val & PC873_EPPEN) && (val & PC873_EPP19)) { 250 outb(idport, PC873_PTR); 251 val = inb(idport + 1); 252 if (!(val & PC873_EPPRDIR)) { 253 mode = PPB_EPP; /* As we would have done it anwyay */ 254 } 255 } else if ((val & PC873_ECPEN) && (val & PC873_ECPCLK)) { 256 mode = PPB_PS2; /* tolerable alternative */ 257 } 258 } else { 259 if (bootverbose) 260 printf("PC873xx unlocked, "); 261 262#if 0 /* broken */ 263 /* 264 * Frob the zero-wait-state option if possible; it causes 265 * unreliable operation. 266 */ 267 outb(idport, PC873_FCR); 268 val = inb(idport + 1); 269 if ((ppc->ppc_type == NS_PC87306) || /* we are a '306 */ 270 !(val & PC873_ZWSPWDN)) { /* or pin _is_ ZWS */ 271 val &= ~PC873_ZWS; 272 outb(idport + 1, val); /* must disable ZWS */ 273 outb(idport + 1, val); 274 275 if (bootverbose) 276 printf("ZWS %s, ", (val & PC873_ZWS) ? "enabled" : "disabled"); 277 } 278 279#endif 280 if (bootverbose) 281 printf("reconfiguring for "); 282 283 /* 284 * if the chip is at 0x3bc, we can't use EPP as there's no room 285 * for the extra registers. 286 * 287 * XXX should we use ECP mode always and use the EPP submode? 288 */ 289 if (ppc->ppc_base != 0x3bc) { 290 if (bootverbose) 291 printf("EPP 1.9\n"); 292 293 /* configure for EPP 1.9 operation XXX should be configurable */ 294 outb(idport, PC873_PCR); 295 val = inb(idport + 1); 296 val &= ~(PC873_ECPEN | PC873_ECPCLK); /* disable ECP */ 297 val |= (PC873_EPPEN | PC873_EPP19); /* enable EPP */ 298 outb(idport + 1, val); 299 outb(idport + 1, val); 300 301 /* enable automatic direction turnover */ 302 outb(idport, PC873_PTR); 303 val = inb(idport + 1); 304 val &= ~PC873_EPPRDIR; /* disable "regular" direction change */ 305 outb(idport + 1, val); 306 outb(idport + 1, val); 307 308 /* we are an EPP-32 port */ 309 mode = PPB_EPP; 310 } else { 311 if (bootverbose) 312 printf("ECP\n"); 313 314 /* configure as an ECP port to get bidirectional operation for now */ 315 outb(idport, PC873_PCR); 316 outb(idport + 1, inb(idport + 1) | PC873_ECPEN | PC873_ECPCLK); 317 318 /* we look like a PS/2 port */ 319 mode = PPB_PS2; 320 } 321 } 322 return(mode); 323 } 324 return(0); 325} 326 327static int 328ppc_detect_ps2(struct ppc_data *ppc) 329{ 330 char save_control, r; 331 332 save_control = r_ctr(ppc); 333 334 /* Try PS/2 mode */ 335 w_ctr(ppc, 0xec); 336 w_dtr(ppc, 0x55); 337 338 /* needed if in ECP mode */ 339 if (ppc->ppc_mode == PPB_ECP) 340 w_ctr(ppc, PCD | 0xec); 341 r = r_dtr(ppc); 342 343 if (r != (char) 0xff) { 344 if (r != (char) 0x55) 345 return 0; 346 347 w_dtr(ppc, 0xaa); 348 r = r_dtr(ppc); 349 if (r != (char) 0xaa) 350 return 0; 351 352 return (PPB_NIBBLE); 353 } else 354 w_ctr(ppc, save_control); 355 356 return (PPB_PS2); 357} 358 359/* 360 * ppc_smc37c66xgt_detect 361 * 362 * SMC FDC37C66xGT configuration. 363 */ 364static int 365ppc_smc37c66xgt_detect(struct ppc_data *ppc, int mode) 366{ 367 int s, i; 368 char r; 369 int retry = 0; /* boolean */ 370 int type = -1; 371 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 372 373 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 374 375 376#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 377 378 /* 379 * Detection: enter configuration mode and read CRD register. 380 */ 381 382 s = splhigh(); 383 outb(csr, SMC665_iCODE); 384 outb(csr, SMC665_iCODE); 385 splx(s); 386 387 outb(csr, 0xd); 388 if (inb(cio) == 0x65) { 389 type = SMC_37C665GT; 390 goto config; 391 } 392 393 for (i = 0; i < 2; i++) { 394 s = splhigh(); 395 outb(csr, SMC666_iCODE); 396 outb(csr, SMC666_iCODE); 397 splx(s); 398 399 outb(csr, 0xd); 400 if (inb(cio) == 0x66) { 401 type = SMC_37C666GT; 402 break; 403 } 404 405 /* Another chance, CSR may be hard-configured to be at 0x370 */ 406 csr = SMC666_CSR; 407 } 408 409config: 410 /* 411 * If chipset not found, do not continue. 412 */ 413 if (type == -1) 414 return (0); 415 416 /* select CR1 */ 417 outb(csr, 0x1); 418 419 /* read the port's address: bits 0 and 1 of CR1 */ 420 r = inb(cio) & SMC_CR1_ADDR; 421 if (port_address[r] != ppc->ppc_base) 422 return (0); 423 424 ppc->ppc_type = type; 425 426 /* 427 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 428 * If SPP mode is detected, try to set ECP+EPP mode end retry 429 * detection to verify. 430 */ 431 432retry: 433 /* select CR1 register */ 434 outb(csr, 0x1); 435 436 if (!mode) { 437 /* autodetect mode */ 438 439 /* 666GT chipset is hardwired to an extended mode */ 440 if (type == SMC_37C666GT) 441 mode = PPB_ECP_EPP; 442 443 else if ((inb(cio) & SMC_CR1_MODE) == 0) { 444 /* already in extended parallel port mode, read CR4 */ 445 outb(csr, 0x4); 446 r = (inb(cio) & SMC_CR4_EMODE); 447 448 switch (r) { 449 case SMC_SPP: 450 /* let's detect NIBBLE or PS/2 later */ 451 break; 452 453 case SMC_EPPSPP: 454 mode = PPB_EPP; 455 break; 456 457 case SMC_ECP: 458 /* 459 * Yet, don't know what to do with it! XXX 460 * So, consider ECP mode as PS/2. 461 * (see configuration later). 462 */ 463 mode = PPB_ECP; 464 break; 465 466 case SMC_ECPEPP: 467 mode = PPB_ECP_EPP; 468 break; 469 } 470 } 471 } else { 472 /* mode forced */ 473 474 /* 666GT chipset is hardwired to an extended mode */ 475 if (type == SMC_37C666GT) 476 goto end_detect; 477 478 r = inb(cio); 479 if (mode == PPB_NIBBLE || mode == PPB_PS2) { 480 /* do not use ECP when the mode is forced to SPP */ 481 outb(cio, r | SMC_CR1_MODE); 482 } else { 483 /* an extended mode is selected */ 484 outb(cio, r & ~SMC_CR1_MODE); 485 486 /* read CR4 register and reset mode field */ 487 outb(csr, 0x4); 488 r = inb(cio) & ~SMC_CR4_EMODE; 489 490 switch (mode) { 491 case PPB_EPP: 492 outb(cio, r | SMC_EPPSPP); 493 break; 494 495 case PPB_ECP: 496 case PPB_ECP_PS2: 497 outb(cio, r | SMC_ECP); 498 break; 499 500 case PPB_ECP_EPP: 501 outb(cio, r | SMC_ECPEPP); 502 break; 503 504 default: 505 printf("ppc: unknown mode (%d)\n", 506 mode); 507 return (0); 508 } 509 } 510 } 511 512end_detect: 513 if (PPB_IS_EPP(mode)) { 514 /* select CR4 */ 515 outb(csr, 0x4); 516 r = inb(cio); 517 518 /* 519 * Set the EPP protocol... 520 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 521 * ...then check the result. 522 */ 523 if (ppc->ppc_epp == EPP_1_9) 524 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 525 526 else 527 outb(cio, (r | SMC_CR4_EPPTYPE)); 528 } 529 530 /* end config mode */ 531 outb(csr, 0xaa); 532 533 /* 534 * Write 100 to the mode bits and disable DMA, enable intr. 535 */ 536 if (mode == PPB_ECP_EPP) 537 w_ecr(ppc, 0x80); 538 539 /* 540 * Write 001 to the mode bits and disable DMA, enable intr. 541 */ 542 if (mode == PPB_ECP) 543 w_ecr(ppc, 0x20); 544 545 if (PPB_IS_EPP(mode)) { 546 /* 547 * Try to reset EPP timeout bit. 548 * If it fails, try PS/2 and NIBBLE modes. 549 */ 550 ppc_reset_epp_timeout(ppc->ppc_unit); 551 552 r = r_str(ppc); 553 if (!(r & TIMEOUT)) 554 return (mode); 555 } else { 556 if (mode) 557 return (mode); 558 } 559 560 /* detect PS/2 or NIBBLE mode */ 561 return (ppc_detect_ps2(ppc)); 562} 563 564static int 565ppc_check_ecpepp_timeout(struct ppc_data *ppc) 566{ 567 char r; 568 569 ppc_reset_epp_timeout(ppc->ppc_unit); 570 571 r = r_str(ppc); 572 if (!(r & TIMEOUT)) { 573 return (PPB_ECP_EPP); 574 } 575 576 /* If EPP timeout bit is not reset, DON'T use EPP */ 577 w_ecr(ppc, 0x20); 578 579 return (PPB_ECP_PS2); 580} 581 582/* 583 * ppc_generic_detect 584 */ 585static int 586ppc_generic_detect(struct ppc_data *ppc, int mode) 587{ 588 char save_control, r; 589 590 /* don't know what to do here */ 591 if (mode) 592 return (mode); 593 594 /* try to reset EPP timeout bit */ 595 ppc_reset_epp_timeout(ppc->ppc_unit); 596 597 r = r_str(ppc); 598 if (!(r & TIMEOUT)) { 599 return (PPB_EPP); 600 } 601 602 /* Now check for ECP */ 603 w_ecr(ppc, 0x20); 604 r = r_ecr(ppc); 605 if ((r & 0xe0) == 0x20) { 606 /* Search for SMC style EPP+ECP mode */ 607 w_ecr(ppc, 0x80); 608 609 return (ppc_check_ecpepp_timeout(ppc)); 610 } 611 612 return (ppc_detect_ps2(ppc)); 613} 614 615/* 616 * ppc_detect() 617 * 618 * mode is the mode suggested at boot 619 */ 620static int 621ppc_detect(struct ppc_data *ppc, int mode) { 622 623 if (!ppc->ppc_mode && (ppc->ppc_mode = ppc_pc873xx_detect(ppc))) 624 goto end_detect; 625 626 if (!ppc->ppc_mode && (ppc->ppc_mode = 627 ppc_smc37c66xgt_detect(ppc, mode))) 628 goto end_detect; 629 630 if (!ppc->ppc_mode && (ppc->ppc_mode = ppc_generic_detect(ppc, mode))) 631 goto end_detect; 632 633 printf("ppc: port not present at 0x%x.\n", ppc->ppc_base); 634 return (PPC_ENOPORT); 635 636end_detect: 637 638 return (0); 639} 640 641/* 642 * EPP timeout, according to the PC87332 manual 643 * Semantics of clearing EPP timeout bit. 644 * PC87332 - reading SPP_STR does it... 645 * SMC - write 1 to EPP timeout bit XXX 646 * Others - (???) write 0 to EPP timeout bit 647 */ 648static void 649ppc_reset_epp_timeout(int unit) 650{ 651 struct ppc_data *ppc = ppcdata[unit]; 652 register char r; 653 654 r = r_str(ppc); 655 w_str(ppc, r | 0x1); 656 w_str(ppc, r & 0xfe); 657 658 return; 659} 660 661static int 662ppcprobe(struct isa_device *dvp) 663{ 664 static short next_bios_ppc = 0; 665 struct ppc_data *ppc; 666 int error; 667 668 /* 669 * If port not specified, use bios list. 670 */ 671 if(dvp->id_iobase < 0) { 672 if((next_bios_ppc < BIOS_MAX_PPC) && 673 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 674 dvp->id_iobase = *(BIOS_PORTS+next_bios_ppc++); 675 } else 676 return (0); 677 } 678 679 /* 680 * Port was explicitly specified. 681 * This allows probing of ports unknown to the BIOS. 682 */ 683 684 /* 685 * Allocate the ppc_data structure. 686 */ 687 ppc = malloc(sizeof(struct ppc_data), M_DEVBUF, M_NOWAIT); 688 if (!ppc) { 689 printf("ppc: cannot malloc!\n"); 690 goto error; 691 } 692 bzero(ppc, sizeof(struct ppc_data)); 693 694 ppc->ppc_base = dvp->id_iobase; 695 ppc->ppc_unit = dvp->id_unit; 696 ppc->ppc_type = GENERIC; 697 698 /* PPB_AUTODETECT is default to allow chipset detection even if 699 * mode is forced by dvp->id_flags (see later, ppc_detect() call) */ 700 ppc->ppc_mode = PPB_AUTODETECT; 701 ppc->ppc_epp = (dvp->id_flags & 0x8) >> 3; 702 703 /* 704 * XXX 705 * Try and detect if interrupts are working. 706 */ 707 if (!(dvp->id_flags & 0x10)) 708 ppc->ppc_irq = (dvp->id_irq); 709 710 ppcdata[ppc->ppc_unit] = ppc; 711 nppc ++; 712 713 /* 714 * Try to detect the chipset and it's mode. 715 */ 716 if (ppc_detect(ppc, dvp->id_flags & 0x7)) 717 goto error; 718 719end_probe: 720 721 return (1); 722 723error: 724 return (0); 725} 726 727static int 728ppcattach(struct isa_device *isdp) 729{ 730 struct ppc_data *ppc = ppcdata[isdp->id_unit]; 731 struct ppb_data *ppbus; 732 733 /* 734 * Link the Parallel Port Chipset (adapter) to 735 * the future ppbus. 736 */ 737 ppc->ppc_link.adapter_unit = ppc->ppc_unit; 738 ppc->ppc_link.adapter = &ppc_adapter; 739 740 printf("ppc%d: %s chipset in %s mode%s\n", ppc->ppc_unit, 741 ppc_types[ppc->ppc_type], ppc_modes[ppc->ppc_mode], 742 (PPB_IS_EPP(ppc->ppc_mode)) ? 743 ppc_epp_protocol[ppc->ppc_epp] : ""); 744 745 /* 746 * Prepare ppbus data area for upper level code. 747 */ 748 ppbus = ppb_alloc_bus(); 749 750 if (!ppbus) 751 return (0); 752 753 ppc->ppc_link.ppbus = ppbus; 754 ppbus->ppb_link = &ppc->ppc_link; 755 756 /* 757 * Probe the ppbus and attach devices found. 758 */ 759 ppb_attachdevs(ppbus); 760 761 return (1); 762} 763#endif 764