ppc.c revision 129879
1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * Copyright (c) 2001 Alcove - Nicolas Souchu 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ppc/ppc.c 129879 2004-05-30 20:08:47Z phk $"); 30 31#include "opt_ppc.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/bus.h> 38#include <sys/malloc.h> 39 40#include <vm/vm.h> 41#include <vm/pmap.h> 42#include <machine/clock.h> 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/vmparam.h> 46#include <sys/rman.h> 47 48#include <isa/isareg.h> 49#include <isa/isavar.h> 50 51#include <dev/ppbus/ppbconf.h> 52#include <dev/ppbus/ppb_msq.h> 53 54#include <dev/ppc/ppcvar.h> 55#include <dev/ppc/ppcreg.h> 56 57#include "ppbus_if.h" 58 59static int ppc_isa_probe(device_t dev); 60 61static void ppcintr(void *arg); 62 63#define LOG_PPC(function, ppc, string) \ 64 if (bootverbose) printf("%s: %s\n", function, string) 65 66 67#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 68 69devclass_t ppc_devclass; 70 71static device_method_t ppc_methods[] = { 72 /* device interface */ 73 DEVMETHOD(device_probe, ppc_isa_probe), 74 DEVMETHOD(device_attach, ppc_attach), 75 76 /* bus interface */ 77 DEVMETHOD(bus_read_ivar, ppc_read_ivar), 78 DEVMETHOD(bus_setup_intr, ppc_setup_intr), 79 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), 80 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 81 82 /* ppbus interface */ 83 DEVMETHOD(ppbus_io, ppc_io), 84 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), 85 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), 86 DEVMETHOD(ppbus_setmode, ppc_setmode), 87 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), 88 DEVMETHOD(ppbus_read, ppc_read), 89 DEVMETHOD(ppbus_write, ppc_write), 90 91 { 0, 0 } 92 }; 93 94static driver_t ppc_driver = { 95 "ppc", 96 ppc_methods, 97 sizeof(struct ppc_data), 98}; 99 100static char *ppc_models[] = { 101 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 102 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 103 "SMC FDC37C935", "PC87303", 0 104}; 105 106/* list of available modes */ 107static char *ppc_avms[] = { 108 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 109 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 110 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 111 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 112}; 113 114/* list of current executing modes 115 * Note that few modes do not actually exist. 116 */ 117static char *ppc_modes[] = { 118 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 119 "EPP", "EPP", "EPP", "ECP", 120 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 121 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 122}; 123 124static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 125 126#ifdef __i386__ 127/* 128 * BIOS printer list - used by BIOS probe. 129 */ 130#define BIOS_PPC_PORTS 0x408 131#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 132#define BIOS_MAX_PPC 4 133#endif 134 135/* 136 * ppc_ecp_sync() XXX 137 */ 138void 139ppc_ecp_sync(device_t dev) { 140 141 int i, r; 142 struct ppc_data *ppc = DEVTOSOFTC(dev); 143 144 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 145 return; 146 147 r = r_ecr(ppc); 148 if ((r & 0xe0) != PPC_ECR_EPP) 149 return; 150 151 for (i = 0; i < 100; i++) { 152 r = r_ecr(ppc); 153 if (r & 0x1) 154 return; 155 DELAY(100); 156 } 157 158 printf("ppc%d: ECP sync failed as data still " \ 159 "present in FIFO.\n", ppc->ppc_unit); 160 161 return; 162} 163 164/* 165 * ppc_detect_fifo() 166 * 167 * Detect parallel port FIFO 168 */ 169static int 170ppc_detect_fifo(struct ppc_data *ppc) 171{ 172 char ecr_sav; 173 char ctr_sav, ctr, cc; 174 short i; 175 176 /* save registers */ 177 ecr_sav = r_ecr(ppc); 178 ctr_sav = r_ctr(ppc); 179 180 /* enter ECP configuration mode, no interrupt, no DMA */ 181 w_ecr(ppc, 0xf4); 182 183 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 184 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 185 186 /* XXX 16 and 32 bits implementations not supported */ 187 if (ppc->ppc_pword != PPC_PWORD_8) { 188 LOG_PPC(__func__, ppc, "PWord not supported"); 189 goto error; 190 } 191 192 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 193 ctr = r_ctr(ppc); 194 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 195 196 /* enter ECP test mode, no interrupt, no DMA */ 197 w_ecr(ppc, 0xd4); 198 199 /* flush the FIFO */ 200 for (i=0; i<1024; i++) { 201 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 202 break; 203 cc = r_fifo(ppc); 204 } 205 206 if (i >= 1024) { 207 LOG_PPC(__func__, ppc, "can't flush FIFO"); 208 goto error; 209 } 210 211 /* enable interrupts, no DMA */ 212 w_ecr(ppc, 0xd0); 213 214 /* determine readIntrThreshold 215 * fill the FIFO until serviceIntr is set 216 */ 217 for (i=0; i<1024; i++) { 218 w_fifo(ppc, (char)i); 219 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 220 /* readThreshold reached */ 221 ppc->ppc_rthr = i+1; 222 } 223 if (r_ecr(ppc) & PPC_FIFO_FULL) { 224 ppc->ppc_fifo = i+1; 225 break; 226 } 227 } 228 229 if (i >= 1024) { 230 LOG_PPC(__func__, ppc, "can't fill FIFO"); 231 goto error; 232 } 233 234 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 235 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 236 w_ecr(ppc, 0xd0); /* enable interrupts */ 237 238 /* determine writeIntrThreshold 239 * empty the FIFO until serviceIntr is set 240 */ 241 for (i=ppc->ppc_fifo; i>0; i--) { 242 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 243 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 244 goto error; 245 } 246 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 247 /* writeIntrThreshold reached */ 248 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 249 } 250 /* if FIFO empty before the last byte, error */ 251 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 252 LOG_PPC(__func__, ppc, "data lost in FIFO"); 253 goto error; 254 } 255 } 256 257 /* FIFO must be empty after the last byte */ 258 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 259 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 260 goto error; 261 } 262 263 w_ctr(ppc, ctr_sav); 264 w_ecr(ppc, ecr_sav); 265 266 return (0); 267 268error: 269 w_ctr(ppc, ctr_sav); 270 w_ecr(ppc, ecr_sav); 271 272 return (EINVAL); 273} 274 275static int 276ppc_detect_port(struct ppc_data *ppc) 277{ 278 279 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 280 w_dtr(ppc, 0xaa); 281 if (r_dtr(ppc) != 0xaa) 282 return (0); 283 284 return (1); 285} 286 287/* 288 * EPP timeout, according to the PC87332 manual 289 * Semantics of clearing EPP timeout bit. 290 * PC87332 - reading SPP_STR does it... 291 * SMC - write 1 to EPP timeout bit XXX 292 * Others - (?) write 0 to EPP timeout bit 293 */ 294static void 295ppc_reset_epp_timeout(struct ppc_data *ppc) 296{ 297 register char r; 298 299 r = r_str(ppc); 300 w_str(ppc, r | 0x1); 301 w_str(ppc, r & 0xfe); 302 303 return; 304} 305 306static int 307ppc_check_epp_timeout(struct ppc_data *ppc) 308{ 309 ppc_reset_epp_timeout(ppc); 310 311 return (!(r_str(ppc) & TIMEOUT)); 312} 313 314/* 315 * Configure current operating mode 316 */ 317static int 318ppc_generic_setmode(struct ppc_data *ppc, int mode) 319{ 320 u_char ecr = 0; 321 322 /* check if mode is available */ 323 if (mode && !(ppc->ppc_avm & mode)) 324 return (EINVAL); 325 326 /* if ECP mode, configure ecr register */ 327 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 328 /* return to byte mode (keeping direction bit), 329 * no interrupt, no DMA to be able to change to 330 * ECP 331 */ 332 w_ecr(ppc, PPC_ECR_RESET); 333 ecr = PPC_DISABLE_INTR; 334 335 if (mode & PPB_EPP) 336 return (EINVAL); 337 else if (mode & PPB_ECP) 338 /* select ECP mode */ 339 ecr |= PPC_ECR_ECP; 340 else if (mode & PPB_PS2) 341 /* select PS2 mode with ECP */ 342 ecr |= PPC_ECR_PS2; 343 else 344 /* select COMPATIBLE/NIBBLE mode */ 345 ecr |= PPC_ECR_STD; 346 347 w_ecr(ppc, ecr); 348 } 349 350 ppc->ppc_mode = mode; 351 352 return (0); 353} 354 355/* 356 * The ppc driver is free to choose options like FIFO or DMA 357 * if ECP mode is available. 358 * 359 * The 'RAW' option allows the upper drivers to force the ppc mode 360 * even with FIFO, DMA available. 361 */ 362static int 363ppc_smclike_setmode(struct ppc_data *ppc, int mode) 364{ 365 u_char ecr = 0; 366 367 /* check if mode is available */ 368 if (mode && !(ppc->ppc_avm & mode)) 369 return (EINVAL); 370 371 /* if ECP mode, configure ecr register */ 372 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 373 /* return to byte mode (keeping direction bit), 374 * no interrupt, no DMA to be able to change to 375 * ECP or EPP mode 376 */ 377 w_ecr(ppc, PPC_ECR_RESET); 378 ecr = PPC_DISABLE_INTR; 379 380 if (mode & PPB_EPP) 381 /* select EPP mode */ 382 ecr |= PPC_ECR_EPP; 383 else if (mode & PPB_ECP) 384 /* select ECP mode */ 385 ecr |= PPC_ECR_ECP; 386 else if (mode & PPB_PS2) 387 /* select PS2 mode with ECP */ 388 ecr |= PPC_ECR_PS2; 389 else 390 /* select COMPATIBLE/NIBBLE mode */ 391 ecr |= PPC_ECR_STD; 392 393 w_ecr(ppc, ecr); 394 } 395 396 ppc->ppc_mode = mode; 397 398 return (0); 399} 400 401#ifdef PPC_PROBE_CHIPSET 402/* 403 * ppc_pc873xx_detect 404 * 405 * Probe for a Natsemi PC873xx-family part. 406 * 407 * References in this function are to the National Semiconductor 408 * PC87332 datasheet TL/C/11930, May 1995 revision. 409 */ 410static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 411static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 412static int pc873xx_irqtab[] = {5, 7, 5, 0}; 413 414static int pc873xx_regstab[] = { 415 PC873_FER, PC873_FAR, PC873_PTR, 416 PC873_FCR, PC873_PCR, PC873_PMC, 417 PC873_TUP, PC873_SID, PC873_PNP0, 418 PC873_PNP1, PC873_LPTBA, -1 419}; 420 421static char *pc873xx_rnametab[] = { 422 "FER", "FAR", "PTR", "FCR", "PCR", 423 "PMC", "TUP", "SID", "PNP0", "PNP1", 424 "LPTBA", NULL 425}; 426 427static int 428ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 429{ 430 static int index = 0; 431 int idport, irq; 432 int ptr, pcr, val, i; 433 434 while ((idport = pc873xx_basetab[index++])) { 435 436 /* XXX should check first to see if this location is already claimed */ 437 438 /* 439 * Pull the 873xx through the power-on ID cycle (2.2,1.). 440 * We can't use this to locate the chip as it may already have 441 * been used by the BIOS. 442 */ 443 (void)inb(idport); (void)inb(idport); 444 (void)inb(idport); (void)inb(idport); 445 446 /* 447 * Read the SID byte. Possible values are : 448 * 449 * 01010xxx PC87334 450 * 0001xxxx PC87332 451 * 01110xxx PC87306 452 * 00110xxx PC87303 453 */ 454 outb(idport, PC873_SID); 455 val = inb(idport + 1); 456 if ((val & 0xf0) == 0x10) { 457 ppc->ppc_model = NS_PC87332; 458 } else if ((val & 0xf8) == 0x70) { 459 ppc->ppc_model = NS_PC87306; 460 } else if ((val & 0xf8) == 0x50) { 461 ppc->ppc_model = NS_PC87334; 462 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 463 documentation, but probing 464 yielded 0x40... */ 465 ppc->ppc_model = NS_PC87303; 466 } else { 467 if (bootverbose && (val != 0xff)) 468 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 469 continue ; /* not recognised */ 470 } 471 472 /* print registers */ 473 if (bootverbose) { 474 printf("PC873xx"); 475 for (i=0; pc873xx_regstab[i] != -1; i++) { 476 outb(idport, pc873xx_regstab[i]); 477 printf(" %s=0x%x", pc873xx_rnametab[i], 478 inb(idport + 1) & 0xff); 479 } 480 printf("\n"); 481 } 482 483 /* 484 * We think we have one. Is it enabled and where we want it to be? 485 */ 486 outb(idport, PC873_FER); 487 val = inb(idport + 1); 488 if (!(val & PC873_PPENABLE)) { 489 if (bootverbose) 490 printf("PC873xx parallel port disabled\n"); 491 continue; 492 } 493 outb(idport, PC873_FAR); 494 val = inb(idport + 1); 495 /* XXX we should create a driver instance for every port found */ 496 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 497 498 /* First try to change the port address to that requested... */ 499 500 switch(ppc->ppc_base) { 501 case 0x378: 502 val &= 0xfc; 503 break; 504 505 case 0x3bc: 506 val &= 0xfd; 507 break; 508 509 case 0x278: 510 val &= 0xfe; 511 break; 512 513 default: 514 val &= 0xfd; 515 break; 516 } 517 518 outb(idport, PC873_FAR); 519 outb(idport + 1, val); 520 outb(idport + 1, val); 521 522 /* Check for success by reading back the value we supposedly 523 wrote and comparing...*/ 524 525 outb(idport, PC873_FAR); 526 val = inb(idport + 1) & 0x3; 527 528 /* If we fail, report the failure... */ 529 530 if (pc873xx_porttab[val] != ppc->ppc_base) { 531 if (bootverbose) 532 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 533 pc873xx_porttab[val], ppc->ppc_base); 534 } 535 continue; 536 } 537 538 outb(idport, PC873_PTR); 539 ptr = inb(idport + 1); 540 541 /* get irq settings */ 542 if (ppc->ppc_base == 0x378) 543 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 544 else 545 irq = pc873xx_irqtab[val]; 546 547 if (bootverbose) 548 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 549 550 /* 551 * Check if irq settings are correct 552 */ 553 if (irq != ppc->ppc_irq) { 554 /* 555 * If the chipset is not locked and base address is 0x378, 556 * we have another chance 557 */ 558 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 559 if (ppc->ppc_irq == 7) { 560 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 561 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 562 } else { 563 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 564 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 565 } 566 if (bootverbose) 567 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 568 } else { 569 if (bootverbose) 570 printf("PC873xx sorry, can't change irq setting\n"); 571 } 572 } else { 573 if (bootverbose) 574 printf("PC873xx irq settings are correct\n"); 575 } 576 577 outb(idport, PC873_PCR); 578 pcr = inb(idport + 1); 579 580 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 581 if (bootverbose) 582 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 583 584 ppc->ppc_avm |= PPB_NIBBLE; 585 if (bootverbose) 586 printf(", NIBBLE"); 587 588 if (pcr & PC873_EPPEN) { 589 ppc->ppc_avm |= PPB_EPP; 590 591 if (bootverbose) 592 printf(", EPP"); 593 594 if (pcr & PC873_EPP19) 595 ppc->ppc_epp = EPP_1_9; 596 else 597 ppc->ppc_epp = EPP_1_7; 598 599 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 600 outb(idport, PC873_PTR); 601 ptr = inb(idport + 1); 602 if (ptr & PC873_EPPRDIR) 603 printf(", Regular mode"); 604 else 605 printf(", Automatic mode"); 606 } 607 } else if (pcr & PC873_ECPEN) { 608 ppc->ppc_avm |= PPB_ECP; 609 if (bootverbose) 610 printf(", ECP"); 611 612 if (pcr & PC873_ECPCLK) { /* XXX */ 613 ppc->ppc_avm |= PPB_PS2; 614 if (bootverbose) 615 printf(", PS/2"); 616 } 617 } else { 618 outb(idport, PC873_PTR); 619 ptr = inb(idport + 1); 620 if (ptr & PC873_EXTENDED) { 621 ppc->ppc_avm |= PPB_SPP; 622 if (bootverbose) 623 printf(", SPP"); 624 } 625 } 626 } else { 627 if (bootverbose) 628 printf("PC873xx unlocked"); 629 630 if (chipset_mode & PPB_ECP) { 631 if ((chipset_mode & PPB_EPP) && bootverbose) 632 printf(", ECP+EPP not supported"); 633 634 pcr &= ~PC873_EPPEN; 635 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 636 outb(idport + 1, pcr); 637 outb(idport + 1, pcr); 638 639 if (bootverbose) 640 printf(", ECP"); 641 642 } else if (chipset_mode & PPB_EPP) { 643 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 644 pcr |= (PC873_EPPEN | PC873_EPP19); 645 outb(idport + 1, pcr); 646 outb(idport + 1, pcr); 647 648 ppc->ppc_epp = EPP_1_9; /* XXX */ 649 650 if (bootverbose) 651 printf(", EPP1.9"); 652 653 /* enable automatic direction turnover */ 654 if (ppc->ppc_model == NS_PC87332) { 655 outb(idport, PC873_PTR); 656 ptr = inb(idport + 1); 657 ptr &= ~PC873_EPPRDIR; 658 outb(idport + 1, ptr); 659 outb(idport + 1, ptr); 660 661 if (bootverbose) 662 printf(", Automatic mode"); 663 } 664 } else { 665 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 666 outb(idport + 1, pcr); 667 outb(idport + 1, pcr); 668 669 /* configure extended bit in PTR */ 670 outb(idport, PC873_PTR); 671 ptr = inb(idport + 1); 672 673 if (chipset_mode & PPB_PS2) { 674 ptr |= PC873_EXTENDED; 675 676 if (bootverbose) 677 printf(", PS/2"); 678 679 } else { 680 /* default to NIBBLE mode */ 681 ptr &= ~PC873_EXTENDED; 682 683 if (bootverbose) 684 printf(", NIBBLE"); 685 } 686 outb(idport + 1, ptr); 687 outb(idport + 1, ptr); 688 } 689 690 ppc->ppc_avm = chipset_mode; 691 } 692 693 if (bootverbose) 694 printf("\n"); 695 696 ppc->ppc_type = PPC_TYPE_GENERIC; 697 ppc_generic_setmode(ppc, chipset_mode); 698 699 return(chipset_mode); 700 } 701 return(-1); 702} 703 704/* 705 * ppc_smc37c66xgt_detect 706 * 707 * SMC FDC37C66xGT configuration. 708 */ 709static int 710ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 711{ 712 int s, i; 713 u_char r; 714 int type = -1; 715 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 716 717 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 718 719 720#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 721 722 /* 723 * Detection: enter configuration mode and read CRD register. 724 */ 725 726 s = splhigh(); 727 outb(csr, SMC665_iCODE); 728 outb(csr, SMC665_iCODE); 729 splx(s); 730 731 outb(csr, 0xd); 732 if (inb(cio) == 0x65) { 733 type = SMC_37C665GT; 734 goto config; 735 } 736 737 for (i = 0; i < 2; i++) { 738 s = splhigh(); 739 outb(csr, SMC666_iCODE); 740 outb(csr, SMC666_iCODE); 741 splx(s); 742 743 outb(csr, 0xd); 744 if (inb(cio) == 0x66) { 745 type = SMC_37C666GT; 746 break; 747 } 748 749 /* Another chance, CSR may be hard-configured to be at 0x370 */ 750 csr = SMC666_CSR; 751 } 752 753config: 754 /* 755 * If chipset not found, do not continue. 756 */ 757 if (type == -1) 758 return (-1); 759 760 /* select CR1 */ 761 outb(csr, 0x1); 762 763 /* read the port's address: bits 0 and 1 of CR1 */ 764 r = inb(cio) & SMC_CR1_ADDR; 765 if (port_address[(int)r] != ppc->ppc_base) 766 return (-1); 767 768 ppc->ppc_model = type; 769 770 /* 771 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 772 * If SPP mode is detected, try to set ECP+EPP mode 773 */ 774 775 if (bootverbose) { 776 outb(csr, 0x1); 777 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 778 inb(cio) & 0xff); 779 780 outb(csr, 0x4); 781 printf(" CR4=0x%x", inb(cio) & 0xff); 782 } 783 784 /* select CR1 */ 785 outb(csr, 0x1); 786 787 if (!chipset_mode) { 788 /* autodetect mode */ 789 790 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 791 if (type == SMC_37C666GT) { 792 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 793 if (bootverbose) 794 printf(" configuration hardwired, supposing " \ 795 "ECP+EPP SPP"); 796 797 } else 798 if ((inb(cio) & SMC_CR1_MODE) == 0) { 799 /* already in extended parallel port mode, read CR4 */ 800 outb(csr, 0x4); 801 r = (inb(cio) & SMC_CR4_EMODE); 802 803 switch (r) { 804 case SMC_SPP: 805 ppc->ppc_avm |= PPB_SPP; 806 if (bootverbose) 807 printf(" SPP"); 808 break; 809 810 case SMC_EPPSPP: 811 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 812 if (bootverbose) 813 printf(" EPP SPP"); 814 break; 815 816 case SMC_ECP: 817 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 818 if (bootverbose) 819 printf(" ECP SPP"); 820 break; 821 822 case SMC_ECPEPP: 823 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 824 if (bootverbose) 825 printf(" ECP+EPP SPP"); 826 break; 827 } 828 } else { 829 /* not an extended port mode */ 830 ppc->ppc_avm |= PPB_SPP; 831 if (bootverbose) 832 printf(" SPP"); 833 } 834 835 } else { 836 /* mode forced */ 837 ppc->ppc_avm = chipset_mode; 838 839 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 840 if (type == SMC_37C666GT) 841 goto end_detect; 842 843 r = inb(cio); 844 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 845 /* do not use ECP when the mode is not forced to */ 846 outb(cio, r | SMC_CR1_MODE); 847 if (bootverbose) 848 printf(" SPP"); 849 } else { 850 /* an extended mode is selected */ 851 outb(cio, r & ~SMC_CR1_MODE); 852 853 /* read CR4 register and reset mode field */ 854 outb(csr, 0x4); 855 r = inb(cio) & ~SMC_CR4_EMODE; 856 857 if (chipset_mode & PPB_ECP) { 858 if (chipset_mode & PPB_EPP) { 859 outb(cio, r | SMC_ECPEPP); 860 if (bootverbose) 861 printf(" ECP+EPP"); 862 } else { 863 outb(cio, r | SMC_ECP); 864 if (bootverbose) 865 printf(" ECP"); 866 } 867 } else { 868 /* PPB_EPP is set */ 869 outb(cio, r | SMC_EPPSPP); 870 if (bootverbose) 871 printf(" EPP SPP"); 872 } 873 } 874 ppc->ppc_avm = chipset_mode; 875 } 876 877 /* set FIFO threshold to 16 */ 878 if (ppc->ppc_avm & PPB_ECP) { 879 /* select CRA */ 880 outb(csr, 0xa); 881 outb(cio, 16); 882 } 883 884end_detect: 885 886 if (bootverbose) 887 printf ("\n"); 888 889 if (ppc->ppc_avm & PPB_EPP) { 890 /* select CR4 */ 891 outb(csr, 0x4); 892 r = inb(cio); 893 894 /* 895 * Set the EPP protocol... 896 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 897 */ 898 if (ppc->ppc_epp == EPP_1_9) 899 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 900 else 901 outb(cio, (r | SMC_CR4_EPPTYPE)); 902 } 903 904 /* end config mode */ 905 outb(csr, 0xaa); 906 907 ppc->ppc_type = PPC_TYPE_SMCLIKE; 908 ppc_smclike_setmode(ppc, chipset_mode); 909 910 return (chipset_mode); 911} 912 913/* 914 * SMC FDC37C935 configuration 915 * Found on many Alpha machines 916 */ 917static int 918ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 919{ 920 int s; 921 int type = -1; 922 923 s = splhigh(); 924 outb(SMC935_CFG, 0x55); /* enter config mode */ 925 outb(SMC935_CFG, 0x55); 926 splx(s); 927 928 outb(SMC935_IND, SMC935_ID); /* check device id */ 929 if (inb(SMC935_DAT) == 0x2) 930 type = SMC_37C935; 931 932 if (type == -1) { 933 outb(SMC935_CFG, 0xaa); /* exit config mode */ 934 return (-1); 935 } 936 937 ppc->ppc_model = type; 938 939 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 940 outb(SMC935_DAT, 3); /* which is logical device 3 */ 941 942 /* set io port base */ 943 outb(SMC935_IND, SMC935_PORTHI); 944 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 945 outb(SMC935_IND, SMC935_PORTLO); 946 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 947 948 if (!chipset_mode) 949 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 950 else { 951 ppc->ppc_avm = chipset_mode; 952 outb(SMC935_IND, SMC935_PPMODE); 953 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 954 955 /* SPP + EPP or just plain SPP */ 956 if (chipset_mode & (PPB_SPP)) { 957 if (chipset_mode & PPB_EPP) { 958 if (ppc->ppc_epp == EPP_1_9) { 959 outb(SMC935_IND, SMC935_PPMODE); 960 outb(SMC935_DAT, SMC935_EPP19SPP); 961 } 962 if (ppc->ppc_epp == EPP_1_7) { 963 outb(SMC935_IND, SMC935_PPMODE); 964 outb(SMC935_DAT, SMC935_EPP17SPP); 965 } 966 } else { 967 outb(SMC935_IND, SMC935_PPMODE); 968 outb(SMC935_DAT, SMC935_SPP); 969 } 970 } 971 972 /* ECP + EPP or just plain ECP */ 973 if (chipset_mode & PPB_ECP) { 974 if (chipset_mode & PPB_EPP) { 975 if (ppc->ppc_epp == EPP_1_9) { 976 outb(SMC935_IND, SMC935_PPMODE); 977 outb(SMC935_DAT, SMC935_ECPEPP19); 978 } 979 if (ppc->ppc_epp == EPP_1_7) { 980 outb(SMC935_IND, SMC935_PPMODE); 981 outb(SMC935_DAT, SMC935_ECPEPP17); 982 } 983 } else { 984 outb(SMC935_IND, SMC935_PPMODE); 985 outb(SMC935_DAT, SMC935_ECP); 986 } 987 } 988 } 989 990 outb(SMC935_CFG, 0xaa); /* exit config mode */ 991 992 ppc->ppc_type = PPC_TYPE_SMCLIKE; 993 ppc_smclike_setmode(ppc, chipset_mode); 994 995 return (chipset_mode); 996} 997 998/* 999 * Winbond W83877F stuff 1000 * 1001 * EFER: extended function enable register 1002 * EFIR: extended function index register 1003 * EFDR: extended function data register 1004 */ 1005#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 1006#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 1007 1008static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 1009static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 1010static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 1011static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 1012 1013static int 1014ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 1015{ 1016 int i, j, efer; 1017 unsigned char r, hefere, hefras; 1018 1019 for (i = 0; i < 4; i ++) { 1020 /* first try to enable configuration registers */ 1021 efer = w83877f_efers[i]; 1022 1023 /* write the key to the EFER */ 1024 for (j = 0; j < w83877f_keyiter[i]; j ++) 1025 outb (efer, w83877f_keys[i]); 1026 1027 /* then check HEFERE and HEFRAS bits */ 1028 outb (efir, 0x0c); 1029 hefere = inb(efdr) & WINB_HEFERE; 1030 1031 outb (efir, 0x16); 1032 hefras = inb(efdr) & WINB_HEFRAS; 1033 1034 /* 1035 * HEFRAS HEFERE 1036 * 0 1 write 89h to 250h (power-on default) 1037 * 1 0 write 86h twice to 3f0h 1038 * 1 1 write 87h twice to 3f0h 1039 * 0 0 write 88h to 250h 1040 */ 1041 if ((hefere | hefras) == w83877f_hefs[i]) 1042 goto found; 1043 } 1044 1045 return (-1); /* failed */ 1046 1047found: 1048 /* check base port address - read from CR23 */ 1049 outb(efir, 0x23); 1050 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1051 return (-1); 1052 1053 /* read CHIP ID from CR9/bits0-3 */ 1054 outb(efir, 0x9); 1055 1056 switch (inb(efdr) & WINB_CHIPID) { 1057 case WINB_W83877F_ID: 1058 ppc->ppc_model = WINB_W83877F; 1059 break; 1060 1061 case WINB_W83877AF_ID: 1062 ppc->ppc_model = WINB_W83877AF; 1063 break; 1064 1065 default: 1066 ppc->ppc_model = WINB_UNKNOWN; 1067 } 1068 1069 if (bootverbose) { 1070 /* dump of registers */ 1071 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 1072 for (i = 0; i <= 0xd; i ++) { 1073 outb(efir, i); 1074 printf("0x%x ", inb(efdr)); 1075 } 1076 for (i = 0x10; i <= 0x17; i ++) { 1077 outb(efir, i); 1078 printf("0x%x ", inb(efdr)); 1079 } 1080 outb(efir, 0x1e); 1081 printf("0x%x ", inb(efdr)); 1082 for (i = 0x20; i <= 0x29; i ++) { 1083 outb(efir, i); 1084 printf("0x%x ", inb(efdr)); 1085 } 1086 printf("\n"); 1087 printf("ppc%d:", ppc->ppc_unit); 1088 } 1089 1090 ppc->ppc_type = PPC_TYPE_GENERIC; 1091 1092 if (!chipset_mode) { 1093 /* autodetect mode */ 1094 1095 /* select CR0 */ 1096 outb(efir, 0x0); 1097 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1098 1099 /* select CR9 */ 1100 outb(efir, 0x9); 1101 r |= (inb(efdr) & WINB_PRTMODS2); 1102 1103 switch (r) { 1104 case WINB_W83757: 1105 if (bootverbose) 1106 printf("ppc%d: W83757 compatible mode\n", 1107 ppc->ppc_unit); 1108 return (-1); /* generic or SMC-like */ 1109 1110 case WINB_EXTFDC: 1111 case WINB_EXTADP: 1112 case WINB_EXT2FDD: 1113 case WINB_JOYSTICK: 1114 if (bootverbose) 1115 printf(" not in parallel port mode\n"); 1116 return (-1); 1117 1118 case (WINB_PARALLEL | WINB_EPP_SPP): 1119 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1120 if (bootverbose) 1121 printf(" EPP SPP"); 1122 break; 1123 1124 case (WINB_PARALLEL | WINB_ECP): 1125 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1126 if (bootverbose) 1127 printf(" ECP SPP"); 1128 break; 1129 1130 case (WINB_PARALLEL | WINB_ECP_EPP): 1131 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1132 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1133 1134 if (bootverbose) 1135 printf(" ECP+EPP SPP"); 1136 break; 1137 default: 1138 printf("%s: unknown case (0x%x)!\n", __func__, r); 1139 } 1140 1141 } else { 1142 /* mode forced */ 1143 1144 /* select CR9 and set PRTMODS2 bit */ 1145 outb(efir, 0x9); 1146 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1147 1148 /* select CR0 and reset PRTMODSx bits */ 1149 outb(efir, 0x0); 1150 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1151 1152 if (chipset_mode & PPB_ECP) { 1153 if (chipset_mode & PPB_EPP) { 1154 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1155 if (bootverbose) 1156 printf(" ECP+EPP"); 1157 1158 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1159 1160 } else { 1161 outb(efdr, inb(efdr) | WINB_ECP); 1162 if (bootverbose) 1163 printf(" ECP"); 1164 } 1165 } else { 1166 /* select EPP_SPP otherwise */ 1167 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1168 if (bootverbose) 1169 printf(" EPP SPP"); 1170 } 1171 ppc->ppc_avm = chipset_mode; 1172 } 1173 1174 if (bootverbose) 1175 printf("\n"); 1176 1177 /* exit configuration mode */ 1178 outb(efer, 0xaa); 1179 1180 switch (ppc->ppc_type) { 1181 case PPC_TYPE_SMCLIKE: 1182 ppc_smclike_setmode(ppc, chipset_mode); 1183 break; 1184 default: 1185 ppc_generic_setmode(ppc, chipset_mode); 1186 break; 1187 } 1188 1189 return (chipset_mode); 1190} 1191#endif 1192 1193/* 1194 * ppc_generic_detect 1195 */ 1196static int 1197ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1198{ 1199 /* default to generic */ 1200 ppc->ppc_type = PPC_TYPE_GENERIC; 1201 1202 if (bootverbose) 1203 printf("ppc%d:", ppc->ppc_unit); 1204 1205 /* first, check for ECP */ 1206 w_ecr(ppc, PPC_ECR_PS2); 1207 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1208 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1209 if (bootverbose) 1210 printf(" ECP SPP"); 1211 1212 /* search for SMC style ECP+EPP mode */ 1213 w_ecr(ppc, PPC_ECR_EPP); 1214 } 1215 1216 /* try to reset EPP timeout bit */ 1217 if (ppc_check_epp_timeout(ppc)) { 1218 ppc->ppc_dtm |= PPB_EPP; 1219 1220 if (ppc->ppc_dtm & PPB_ECP) { 1221 /* SMC like chipset found */ 1222 ppc->ppc_model = SMC_LIKE; 1223 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1224 1225 if (bootverbose) 1226 printf(" ECP+EPP"); 1227 } else { 1228 if (bootverbose) 1229 printf(" EPP"); 1230 } 1231 } else { 1232 /* restore to standard mode */ 1233 w_ecr(ppc, PPC_ECR_STD); 1234 } 1235 1236 /* XXX try to detect NIBBLE and PS2 modes */ 1237 ppc->ppc_dtm |= PPB_NIBBLE; 1238 1239 if (bootverbose) 1240 printf(" SPP"); 1241 1242 if (chipset_mode) 1243 ppc->ppc_avm = chipset_mode; 1244 else 1245 ppc->ppc_avm = ppc->ppc_dtm; 1246 1247 if (bootverbose) 1248 printf("\n"); 1249 1250 switch (ppc->ppc_type) { 1251 case PPC_TYPE_SMCLIKE: 1252 ppc_smclike_setmode(ppc, chipset_mode); 1253 break; 1254 default: 1255 ppc_generic_setmode(ppc, chipset_mode); 1256 break; 1257 } 1258 1259 return (chipset_mode); 1260} 1261 1262/* 1263 * ppc_detect() 1264 * 1265 * mode is the mode suggested at boot 1266 */ 1267static int 1268ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1269 1270#ifdef PPC_PROBE_CHIPSET 1271 int i, mode; 1272 1273 /* list of supported chipsets */ 1274 int (*chipset_detect[])(struct ppc_data *, int) = { 1275 ppc_pc873xx_detect, 1276 ppc_smc37c66xgt_detect, 1277 ppc_w83877f_detect, 1278 ppc_smc37c935_detect, 1279 ppc_generic_detect, 1280 NULL 1281 }; 1282#endif 1283 1284 /* if can't find the port and mode not forced return error */ 1285 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1286 return (EIO); /* failed, port not present */ 1287 1288 /* assume centronics compatible mode is supported */ 1289 ppc->ppc_avm = PPB_COMPATIBLE; 1290 1291#ifdef PPC_PROBE_CHIPSET 1292 /* we have to differenciate available chipset modes, 1293 * chipset running modes and IEEE-1284 operating modes 1294 * 1295 * after detection, the port must support running in compatible mode 1296 */ 1297 if (ppc->ppc_flags & 0x40) { 1298 if (bootverbose) 1299 printf("ppc: chipset forced to generic\n"); 1300#endif 1301 1302 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1303 1304#ifdef PPC_PROBE_CHIPSET 1305 } else { 1306 for (i=0; chipset_detect[i] != NULL; i++) { 1307 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1308 ppc->ppc_mode = mode; 1309 break; 1310 } 1311 } 1312 } 1313#endif 1314 1315 /* configure/detect ECP FIFO */ 1316 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1317 ppc_detect_fifo(ppc); 1318 1319 return (0); 1320} 1321 1322/* 1323 * ppc_exec_microseq() 1324 * 1325 * Execute a microsequence. 1326 * Microsequence mechanism is supposed to handle fast I/O operations. 1327 */ 1328int 1329ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1330{ 1331 struct ppc_data *ppc = DEVTOSOFTC(dev); 1332 struct ppb_microseq *mi; 1333 char cc, *p; 1334 int i, iter, len; 1335 int error; 1336 1337 register int reg; 1338 register char mask; 1339 register int accum = 0; 1340 register char *ptr = 0; 1341 1342 struct ppb_microseq *stack = 0; 1343 1344/* microsequence registers are equivalent to PC-like port registers */ 1345 1346#define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register)) 1347#define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte)) 1348 1349#define INCR_PC (mi ++) /* increment program counter */ 1350 1351 mi = *p_msq; 1352 for (;;) { 1353 switch (mi->opcode) { 1354 case MS_OP_RSET: 1355 cc = r_reg(mi->arg[0].i, ppc); 1356 cc &= (char)mi->arg[2].i; /* clear mask */ 1357 cc |= (char)mi->arg[1].i; /* assert mask */ 1358 w_reg(mi->arg[0].i, ppc, cc); 1359 INCR_PC; 1360 break; 1361 1362 case MS_OP_RASSERT_P: 1363 reg = mi->arg[1].i; 1364 ptr = ppc->ppc_ptr; 1365 1366 if ((len = mi->arg[0].i) == MS_ACCUM) { 1367 accum = ppc->ppc_accum; 1368 for (; accum; accum--) 1369 w_reg(reg, ppc, *ptr++); 1370 ppc->ppc_accum = accum; 1371 } else 1372 for (i=0; i<len; i++) 1373 w_reg(reg, ppc, *ptr++); 1374 ppc->ppc_ptr = ptr; 1375 1376 INCR_PC; 1377 break; 1378 1379 case MS_OP_RFETCH_P: 1380 reg = mi->arg[1].i; 1381 mask = (char)mi->arg[2].i; 1382 ptr = ppc->ppc_ptr; 1383 1384 if ((len = mi->arg[0].i) == MS_ACCUM) { 1385 accum = ppc->ppc_accum; 1386 for (; accum; accum--) 1387 *ptr++ = r_reg(reg, ppc) & mask; 1388 ppc->ppc_accum = accum; 1389 } else 1390 for (i=0; i<len; i++) 1391 *ptr++ = r_reg(reg, ppc) & mask; 1392 ppc->ppc_ptr = ptr; 1393 1394 INCR_PC; 1395 break; 1396 1397 case MS_OP_RFETCH: 1398 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1399 (char)mi->arg[1].i; 1400 INCR_PC; 1401 break; 1402 1403 case MS_OP_RASSERT: 1404 case MS_OP_DELAY: 1405 1406 /* let's suppose the next instr. is the same */ 1407 prefetch: 1408 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1409 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1410 1411 if (mi->opcode == MS_OP_DELAY) { 1412 DELAY(mi->arg[0].i); 1413 INCR_PC; 1414 goto prefetch; 1415 } 1416 break; 1417 1418 case MS_OP_ADELAY: 1419 if (mi->arg[0].i) 1420 tsleep(NULL, PPBPRI, "ppbdelay", 1421 mi->arg[0].i * (hz/1000)); 1422 INCR_PC; 1423 break; 1424 1425 case MS_OP_TRIG: 1426 reg = mi->arg[0].i; 1427 iter = mi->arg[1].i; 1428 p = (char *)mi->arg[2].p; 1429 1430 /* XXX delay limited to 255 us */ 1431 for (i=0; i<iter; i++) { 1432 w_reg(reg, ppc, *p++); 1433 DELAY((unsigned char)*p++); 1434 } 1435 INCR_PC; 1436 break; 1437 1438 case MS_OP_SET: 1439 ppc->ppc_accum = mi->arg[0].i; 1440 INCR_PC; 1441 break; 1442 1443 case MS_OP_DBRA: 1444 if (--ppc->ppc_accum > 0) 1445 mi += mi->arg[0].i; 1446 INCR_PC; 1447 break; 1448 1449 case MS_OP_BRSET: 1450 cc = r_str(ppc); 1451 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1452 mi += mi->arg[1].i; 1453 INCR_PC; 1454 break; 1455 1456 case MS_OP_BRCLEAR: 1457 cc = r_str(ppc); 1458 if ((cc & (char)mi->arg[0].i) == 0) 1459 mi += mi->arg[1].i; 1460 INCR_PC; 1461 break; 1462 1463 case MS_OP_BRSTAT: 1464 cc = r_str(ppc); 1465 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1466 (char)mi->arg[0].i) 1467 mi += mi->arg[2].i; 1468 INCR_PC; 1469 break; 1470 1471 case MS_OP_C_CALL: 1472 /* 1473 * If the C call returns !0 then end the microseq. 1474 * The current state of ptr is passed to the C function 1475 */ 1476 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1477 return (error); 1478 1479 INCR_PC; 1480 break; 1481 1482 case MS_OP_PTR: 1483 ppc->ppc_ptr = (char *)mi->arg[0].p; 1484 INCR_PC; 1485 break; 1486 1487 case MS_OP_CALL: 1488 if (stack) 1489 panic("%s: too much calls", __func__); 1490 1491 if (mi->arg[0].p) { 1492 /* store the state of the actual 1493 * microsequence 1494 */ 1495 stack = mi; 1496 1497 /* jump to the new microsequence */ 1498 mi = (struct ppb_microseq *)mi->arg[0].p; 1499 } else 1500 INCR_PC; 1501 1502 break; 1503 1504 case MS_OP_SUBRET: 1505 /* retrieve microseq and pc state before the call */ 1506 mi = stack; 1507 1508 /* reset the stack */ 1509 stack = 0; 1510 1511 /* XXX return code */ 1512 1513 INCR_PC; 1514 break; 1515 1516 case MS_OP_PUT: 1517 case MS_OP_GET: 1518 case MS_OP_RET: 1519 /* can't return to ppb level during the execution 1520 * of a submicrosequence */ 1521 if (stack) 1522 panic("%s: can't return to ppb level", 1523 __func__); 1524 1525 /* update pc for ppb level of execution */ 1526 *p_msq = mi; 1527 1528 /* return to ppb level of execution */ 1529 return (0); 1530 1531 default: 1532 panic("%s: unknown microsequence opcode 0x%x", 1533 __func__, mi->opcode); 1534 } 1535 } 1536 1537 /* unreached */ 1538} 1539 1540static void 1541ppcintr(void *arg) 1542{ 1543 device_t dev = (device_t)arg; 1544 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1545 u_char ctr, ecr, str; 1546 1547 str = r_str(ppc); 1548 ctr = r_ctr(ppc); 1549 ecr = r_ecr(ppc); 1550 1551#if PPC_DEBUG > 1 1552 printf("![%x/%x/%x]", ctr, ecr, str); 1553#endif 1554 1555 /* don't use ecp mode with IRQENABLE set */ 1556 if (ctr & IRQENABLE) { 1557 return; 1558 } 1559 1560 /* interrupts are generated by nFault signal 1561 * only in ECP mode */ 1562 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1563 /* check if ppc driver has programmed the 1564 * nFault interrupt */ 1565 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1566 1567 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1568 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1569 } else { 1570 /* shall be handled by underlying layers XXX */ 1571 return; 1572 } 1573 } 1574 1575 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1576 /* disable interrupts (should be done by hardware though) */ 1577 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1578 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1579 ecr = r_ecr(ppc); 1580 1581 /* check if DMA completed */ 1582 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1583#ifdef PPC_DEBUG 1584 printf("a"); 1585#endif 1586 /* stop DMA */ 1587 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1588 ecr = r_ecr(ppc); 1589 1590 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1591#ifdef PPC_DEBUG 1592 printf("d"); 1593#endif 1594 isa_dmadone( 1595 ppc->ppc_dmaflags, 1596 ppc->ppc_dmaddr, 1597 ppc->ppc_dmacnt, 1598 ppc->ppc_dmachan); 1599 1600 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1601 1602 /* wakeup the waiting process */ 1603 wakeup(ppc); 1604 } 1605 } 1606 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1607 1608 /* classic interrupt I/O */ 1609 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1610 } 1611 1612 return; 1613} 1614 1615int 1616ppc_read(device_t dev, char *buf, int len, int mode) 1617{ 1618 return (EINVAL); 1619} 1620 1621/* 1622 * Call this function if you want to send data in any advanced mode 1623 * of your parallel port: FIFO, DMA 1624 * 1625 * If what you want is not possible (no ECP, no DMA...), 1626 * EINVAL is returned 1627 */ 1628int 1629ppc_write(device_t dev, char *buf, int len, int how) 1630{ 1631 struct ppc_data *ppc = DEVTOSOFTC(dev); 1632 char ecr, ecr_sav, ctr, ctr_sav; 1633 int s, error = 0; 1634 int spin; 1635 1636#ifdef PPC_DEBUG 1637 printf("w"); 1638#endif 1639 1640 ecr_sav = r_ecr(ppc); 1641 ctr_sav = r_ctr(ppc); 1642 1643 /* 1644 * Send buffer with DMA, FIFO and interrupts 1645 */ 1646 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { 1647 1648 if (ppc->ppc_dmachan > 0) { 1649 1650 /* byte mode, no intr, no DMA, dir=0, flush fifo 1651 */ 1652 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1653 w_ecr(ppc, ecr); 1654 1655 /* disable nAck interrupts */ 1656 ctr = r_ctr(ppc); 1657 ctr &= ~IRQENABLE; 1658 w_ctr(ppc, ctr); 1659 1660 ppc->ppc_dmaflags = 0; 1661 ppc->ppc_dmaddr = (caddr_t)buf; 1662 ppc->ppc_dmacnt = (u_int)len; 1663 1664 switch (ppc->ppc_mode) { 1665 case PPB_COMPATIBLE: 1666 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1667 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1668 break; 1669 case PPB_ECP: 1670 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1671 break; 1672 default: 1673 error = EINVAL; 1674 goto error; 1675 } 1676 1677 w_ecr(ppc, ecr); 1678 ecr = r_ecr(ppc); 1679 1680 /* enter splhigh() not to be preempted 1681 * by the dma interrupt, we may miss 1682 * the wakeup otherwise 1683 */ 1684 s = splhigh(); 1685 1686 ppc->ppc_dmastat = PPC_DMA_INIT; 1687 1688 /* enable interrupts */ 1689 ecr &= ~PPC_SERVICE_INTR; 1690 ppc->ppc_irqstat = PPC_IRQ_DMA; 1691 w_ecr(ppc, ecr); 1692 1693 isa_dmastart( 1694 ppc->ppc_dmaflags, 1695 ppc->ppc_dmaddr, 1696 ppc->ppc_dmacnt, 1697 ppc->ppc_dmachan); 1698#ifdef PPC_DEBUG 1699 printf("s%d", ppc->ppc_dmacnt); 1700#endif 1701 ppc->ppc_dmastat = PPC_DMA_STARTED; 1702 1703 /* Wait for the DMA completed interrupt. We hope we won't 1704 * miss it, otherwise a signal will be necessary to unlock the 1705 * process. 1706 */ 1707 do { 1708 /* release CPU */ 1709 error = tsleep(ppc, 1710 PPBPRI | PCATCH, "ppcdma", 0); 1711 1712 } while (error == EWOULDBLOCK); 1713 1714 splx(s); 1715 1716 if (error) { 1717#ifdef PPC_DEBUG 1718 printf("i"); 1719#endif 1720 /* stop DMA */ 1721 isa_dmadone( 1722 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1723 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1724 1725 /* no dma, no interrupt, flush the fifo */ 1726 w_ecr(ppc, PPC_ECR_RESET); 1727 1728 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1729 goto error; 1730 } 1731 1732 /* wait for an empty fifo */ 1733 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1734 1735 for (spin=100; spin; spin--) 1736 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1737 goto fifo_empty; 1738#ifdef PPC_DEBUG 1739 printf("Z"); 1740#endif 1741 error = tsleep(ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1742 if (error != EWOULDBLOCK) { 1743#ifdef PPC_DEBUG 1744 printf("I"); 1745#endif 1746 /* no dma, no interrupt, flush the fifo */ 1747 w_ecr(ppc, PPC_ECR_RESET); 1748 1749 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1750 error = EINTR; 1751 goto error; 1752 } 1753 } 1754 1755fifo_empty: 1756 /* no dma, no interrupt, flush the fifo */ 1757 w_ecr(ppc, PPC_ECR_RESET); 1758 1759 } else 1760 error = EINVAL; /* XXX we should FIFO and 1761 * interrupts */ 1762 } else 1763 error = EINVAL; 1764 1765error: 1766 1767 /* PDRQ must be kept unasserted until nPDACK is 1768 * deasserted for a minimum of 350ns (SMC datasheet) 1769 * 1770 * Consequence may be a FIFO that never empty 1771 */ 1772 DELAY(1); 1773 1774 w_ecr(ppc, ecr_sav); 1775 w_ctr(ppc, ctr_sav); 1776 1777 return (error); 1778} 1779 1780void 1781ppc_reset_epp(device_t dev) 1782{ 1783 struct ppc_data *ppc = DEVTOSOFTC(dev); 1784 1785 ppc_reset_epp_timeout(ppc); 1786 1787 return; 1788} 1789 1790int 1791ppc_setmode(device_t dev, int mode) 1792{ 1793 struct ppc_data *ppc = DEVTOSOFTC(dev); 1794 1795 switch (ppc->ppc_type) { 1796 case PPC_TYPE_SMCLIKE: 1797 return (ppc_smclike_setmode(ppc, mode)); 1798 break; 1799 1800 case PPC_TYPE_GENERIC: 1801 default: 1802 return (ppc_generic_setmode(ppc, mode)); 1803 break; 1804 } 1805 1806 /* not reached */ 1807 return (ENXIO); 1808} 1809 1810static struct isa_pnp_id lpc_ids[] = { 1811 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */ 1812 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */ 1813 { 0 } 1814}; 1815 1816static int 1817ppc_isa_probe(device_t dev) 1818{ 1819 device_t parent; 1820 int error; 1821 1822 parent = device_get_parent(dev); 1823 1824 error = ISA_PNP_PROBE(parent, dev, lpc_ids); 1825 if (error == ENXIO) 1826 return (ENXIO); 1827 else if (error != 0) /* XXX shall be set after detection */ 1828 device_set_desc(dev, "Parallel port"); 1829 1830 return(ppc_probe(dev)); 1831} 1832 1833int 1834ppc_probe(device_t dev) 1835{ 1836#ifdef __i386__ 1837 static short next_bios_ppc = 0; 1838#endif 1839 struct ppc_data *ppc; 1840 int error; 1841 u_long port; 1842 1843 /* 1844 * Allocate the ppc_data structure. 1845 */ 1846 ppc = DEVTOSOFTC(dev); 1847 bzero(ppc, sizeof(struct ppc_data)); 1848 1849 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; 1850 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; 1851 1852 /* retrieve ISA parameters */ 1853 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); 1854 1855#ifdef __i386__ 1856 /* 1857 * If port not specified, use bios list. 1858 */ 1859 if (error) { 1860 if((next_bios_ppc < BIOS_MAX_PPC) && 1861 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1862 port = *(BIOS_PORTS+next_bios_ppc++); 1863 if (bootverbose) 1864 device_printf(dev, "parallel port found at 0x%x\n", 1865 (int) port); 1866 } else { 1867 device_printf(dev, "parallel port not found.\n"); 1868 return ENXIO; 1869 } 1870 bus_set_resource(dev, SYS_RES_IOPORT, 0, port, 1871 IO_LPTSIZE_EXTENDED); 1872 } 1873#endif 1874#ifdef __alpha__ 1875 /* 1876 * There isn't a bios list on alpha. Put it in the usual place. 1877 */ 1878 if (error) { 1879 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, 1880 IO_LPTSIZE_NORMAL); 1881 } 1882#endif 1883 1884 /* IO port is mandatory */ 1885 1886 /* Try "extended" IO port range...*/ 1887 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1888 &ppc->rid_ioport, 0, ~0, 1889 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1890 1891 if (ppc->res_ioport != 0) { 1892 if (bootverbose) 1893 device_printf(dev, "using extended I/O port range\n"); 1894 } else { 1895 /* Failed? If so, then try the "normal" IO port range... */ 1896 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1897 &ppc->rid_ioport, 0, ~0, 1898 IO_LPTSIZE_NORMAL, 1899 RF_ACTIVE); 1900 if (ppc->res_ioport != 0) { 1901 if (bootverbose) 1902 device_printf(dev, "using normal I/O port range\n"); 1903 } else { 1904 device_printf(dev, "cannot reserve I/O port range\n"); 1905 goto error; 1906 } 1907 } 1908 1909 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1910 1911 ppc->bsh = rman_get_bushandle(ppc->res_ioport); 1912 ppc->bst = rman_get_bustag(ppc->res_ioport); 1913 1914 ppc->ppc_flags = device_get_flags(dev); 1915 1916 if (!(ppc->ppc_flags & 0x20)) { 1917 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1918 &ppc->rid_irq, 1919 RF_SHAREABLE); 1920 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1921 &ppc->rid_drq, 1922 RF_ACTIVE); 1923 } 1924 1925 if (ppc->res_irq) 1926 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1927 if (ppc->res_drq) 1928 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1929 1930 ppc->ppc_unit = device_get_unit(dev); 1931 ppc->ppc_model = GENERIC; 1932 1933 ppc->ppc_mode = PPB_COMPATIBLE; 1934 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1935 1936 ppc->ppc_type = PPC_TYPE_GENERIC; 1937 1938 /* 1939 * Try to detect the chipset and its mode. 1940 */ 1941 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1942 goto error; 1943 1944 return (0); 1945 1946error: 1947 if (ppc->res_irq != 0) { 1948 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1949 ppc->res_irq); 1950 } 1951 if (ppc->res_ioport != 0) { 1952 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1953 ppc->res_ioport); 1954 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1955 ppc->res_ioport); 1956 } 1957 if (ppc->res_drq != 0) { 1958 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1959 ppc->res_drq); 1960 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1961 ppc->res_drq); 1962 } 1963 return (ENXIO); 1964} 1965 1966int 1967ppc_attach(device_t dev) 1968{ 1969 struct ppc_data *ppc = DEVTOSOFTC(dev); 1970 1971 device_t ppbus; 1972 device_t parent = device_get_parent(dev); 1973 1974 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1975 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1976 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1977 ppc_epp_protocol[ppc->ppc_epp] : ""); 1978 1979 if (ppc->ppc_fifo) 1980 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1981 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1982 1983 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1984 /* acquire the DMA channel forever */ /* XXX */ 1985 isa_dma_acquire(ppc->ppc_dmachan); 1986 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1987 } 1988 1989 /* add ppbus as a child of this isa to parallel bridge */ 1990 ppbus = device_add_child(dev, "ppbus", -1); 1991 1992 /* 1993 * Probe the ppbus and attach devices found. 1994 */ 1995 device_probe_and_attach(ppbus); 1996 1997 /* register the ppc interrupt handler as default */ 1998 if (ppc->res_irq) { 1999 /* default to the tty mask for registration */ /* XXX */ 2000 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, 2001 ppcintr, dev, &ppc->intr_cookie) == 0) { 2002 2003 /* remember the ppcintr is registered */ 2004 ppc->ppc_registered = 1; 2005 } 2006 } 2007 2008 return (0); 2009} 2010 2011u_char 2012ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 2013{ 2014 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 2015 switch (iop) { 2016 case PPB_OUTSB_EPP: 2017 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 2018 break; 2019 case PPB_OUTSW_EPP: 2020 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 2021 break; 2022 case PPB_OUTSL_EPP: 2023 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 2024 break; 2025 case PPB_INSB_EPP: 2026 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 2027 break; 2028 case PPB_INSW_EPP: 2029 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 2030 break; 2031 case PPB_INSL_EPP: 2032 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 2033 break; 2034 case PPB_RDTR: 2035 return (r_dtr(ppc)); 2036 case PPB_RSTR: 2037 return (r_str(ppc)); 2038 case PPB_RCTR: 2039 return (r_ctr(ppc)); 2040 case PPB_REPP_A: 2041 return (r_epp_A(ppc)); 2042 case PPB_REPP_D: 2043 return (r_epp_D(ppc)); 2044 case PPB_RECR: 2045 return (r_ecr(ppc)); 2046 case PPB_RFIFO: 2047 return (r_fifo(ppc)); 2048 case PPB_WDTR: 2049 w_dtr(ppc, byte); 2050 break; 2051 case PPB_WSTR: 2052 w_str(ppc, byte); 2053 break; 2054 case PPB_WCTR: 2055 w_ctr(ppc, byte); 2056 break; 2057 case PPB_WEPP_A: 2058 w_epp_A(ppc, byte); 2059 break; 2060 case PPB_WEPP_D: 2061 w_epp_D(ppc, byte); 2062 break; 2063 case PPB_WECR: 2064 w_ecr(ppc, byte); 2065 break; 2066 case PPB_WFIFO: 2067 w_fifo(ppc, byte); 2068 break; 2069 default: 2070 panic("%s: unknown I/O operation", __func__); 2071 break; 2072 } 2073 2074 return (0); /* not significative */ 2075} 2076 2077int 2078ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 2079{ 2080 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 2081 2082 switch (index) { 2083 case PPC_IVAR_EPP_PROTO: 2084 *val = (u_long)ppc->ppc_epp; 2085 break; 2086 case PPC_IVAR_IRQ: 2087 *val = (u_long)ppc->ppc_irq; 2088 break; 2089 default: 2090 return (ENOENT); 2091 } 2092 2093 return (0); 2094} 2095 2096/* 2097 * Resource is useless here since ppbus devices' interrupt handlers are 2098 * multiplexed to the same resource initially allocated by ppc 2099 */ 2100int 2101ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 2102 void (*ihand)(void *), void *arg, void **cookiep) 2103{ 2104 int error; 2105 struct ppc_data *ppc = DEVTOSOFTC(bus); 2106 2107 if (ppc->ppc_registered) { 2108 /* XXX refuse registration if DMA is in progress */ 2109 2110 /* first, unregister the default interrupt handler */ 2111 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 2112 bus, ppc->res_irq, ppc->intr_cookie))) 2113 return (error); 2114 2115/* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 2116/* ppc->res_irq); */ 2117 2118 /* DMA/FIFO operation won't be possible anymore */ 2119 ppc->ppc_registered = 0; 2120 } 2121 2122 /* pass registration to the upper layer, ignore the incoming resource */ 2123 return (BUS_SETUP_INTR(device_get_parent(bus), child, 2124 r, flags, ihand, arg, cookiep)); 2125} 2126 2127/* 2128 * When no underlying device has a registered interrupt, register the ppc 2129 * layer one 2130 */ 2131int 2132ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 2133{ 2134 int error; 2135 struct ppc_data *ppc = DEVTOSOFTC(bus); 2136 device_t parent = device_get_parent(bus); 2137 2138 /* pass unregistration to the upper layer */ 2139 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 2140 return (error); 2141 2142 /* default to the tty mask for registration */ /* XXX */ 2143 if (ppc->ppc_irq && 2144 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 2145 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { 2146 2147 /* remember the ppcintr is registered */ 2148 ppc->ppc_registered = 1; 2149 } 2150 2151 return (error); 2152} 2153 2154DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); 2155DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, 0, 0); 2156