ppc.c revision 127135
1/*- 2 * Copyright (c) 1997-2000 Nicolas Souchu 3 * Copyright (c) 2001 Alcove - Nicolas Souchu 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/ppc/ppc.c 127135 2004-03-17 17:50:55Z njl $"); 30 31#include "opt_ppc.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/malloc.h> 38 39#include <vm/vm.h> 40#include <vm/pmap.h> 41#include <machine/clock.h> 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <machine/vmparam.h> 45#include <sys/rman.h> 46 47#include <isa/isareg.h> 48#include <isa/isavar.h> 49 50#include <dev/ppbus/ppbconf.h> 51#include <dev/ppbus/ppb_msq.h> 52 53#include <dev/ppc/ppcvar.h> 54#include <dev/ppc/ppcreg.h> 55 56#include "ppbus_if.h" 57 58static int ppc_isa_probe(device_t dev); 59 60static void ppcintr(void *arg); 61 62#define LOG_PPC(function, ppc, string) \ 63 if (bootverbose) printf("%s: %s\n", function, string) 64 65 66#define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev)) 67 68devclass_t ppc_devclass; 69 70static device_method_t ppc_methods[] = { 71 /* device interface */ 72 DEVMETHOD(device_probe, ppc_isa_probe), 73 DEVMETHOD(device_attach, ppc_attach), 74 75 /* bus interface */ 76 DEVMETHOD(bus_read_ivar, ppc_read_ivar), 77 DEVMETHOD(bus_setup_intr, ppc_setup_intr), 78 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr), 79 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 80 81 /* ppbus interface */ 82 DEVMETHOD(ppbus_io, ppc_io), 83 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq), 84 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp), 85 DEVMETHOD(ppbus_setmode, ppc_setmode), 86 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync), 87 DEVMETHOD(ppbus_read, ppc_read), 88 DEVMETHOD(ppbus_write, ppc_write), 89 90 { 0, 0 } 91 }; 92 93static driver_t ppc_driver = { 94 "ppc", 95 ppc_methods, 96 sizeof(struct ppc_data), 97}; 98 99static char *ppc_models[] = { 100 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306", 101 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334", 102 "SMC FDC37C935", "PC87303", 0 103}; 104 105/* list of available modes */ 106static char *ppc_avms[] = { 107 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only", 108 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only", 109 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP", 110 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0 111}; 112 113/* list of current executing modes 114 * Note that few modes do not actually exist. 115 */ 116static char *ppc_modes[] = { 117 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP", 118 "EPP", "EPP", "EPP", "ECP", 119 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP", 120 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0 121}; 122 123static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 }; 124 125#ifdef __i386__ 126/* 127 * BIOS printer list - used by BIOS probe. 128 */ 129#define BIOS_PPC_PORTS 0x408 130#define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS) 131#define BIOS_MAX_PPC 4 132#endif 133 134/* 135 * ppc_ecp_sync() XXX 136 */ 137void 138ppc_ecp_sync(device_t dev) { 139 140 int i, r; 141 struct ppc_data *ppc = DEVTOSOFTC(dev); 142 143 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP)) 144 return; 145 146 r = r_ecr(ppc); 147 if ((r & 0xe0) != PPC_ECR_EPP) 148 return; 149 150 for (i = 0; i < 100; i++) { 151 r = r_ecr(ppc); 152 if (r & 0x1) 153 return; 154 DELAY(100); 155 } 156 157 printf("ppc%d: ECP sync failed as data still " \ 158 "present in FIFO.\n", ppc->ppc_unit); 159 160 return; 161} 162 163/* 164 * ppc_detect_fifo() 165 * 166 * Detect parallel port FIFO 167 */ 168static int 169ppc_detect_fifo(struct ppc_data *ppc) 170{ 171 char ecr_sav; 172 char ctr_sav, ctr, cc; 173 short i; 174 175 /* save registers */ 176 ecr_sav = r_ecr(ppc); 177 ctr_sav = r_ctr(ppc); 178 179 /* enter ECP configuration mode, no interrupt, no DMA */ 180 w_ecr(ppc, 0xf4); 181 182 /* read PWord size - transfers in FIFO mode must be PWord aligned */ 183 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK); 184 185 /* XXX 16 and 32 bits implementations not supported */ 186 if (ppc->ppc_pword != PPC_PWORD_8) { 187 LOG_PPC(__func__, ppc, "PWord not supported"); 188 goto error; 189 } 190 191 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */ 192 ctr = r_ctr(ppc); 193 w_ctr(ppc, ctr | PCD); /* set direction to 1 */ 194 195 /* enter ECP test mode, no interrupt, no DMA */ 196 w_ecr(ppc, 0xd4); 197 198 /* flush the FIFO */ 199 for (i=0; i<1024; i++) { 200 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 201 break; 202 cc = r_fifo(ppc); 203 } 204 205 if (i >= 1024) { 206 LOG_PPC(__func__, ppc, "can't flush FIFO"); 207 goto error; 208 } 209 210 /* enable interrupts, no DMA */ 211 w_ecr(ppc, 0xd0); 212 213 /* determine readIntrThreshold 214 * fill the FIFO until serviceIntr is set 215 */ 216 for (i=0; i<1024; i++) { 217 w_fifo(ppc, (char)i); 218 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) { 219 /* readThreshold reached */ 220 ppc->ppc_rthr = i+1; 221 } 222 if (r_ecr(ppc) & PPC_FIFO_FULL) { 223 ppc->ppc_fifo = i+1; 224 break; 225 } 226 } 227 228 if (i >= 1024) { 229 LOG_PPC(__func__, ppc, "can't fill FIFO"); 230 goto error; 231 } 232 233 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */ 234 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */ 235 w_ecr(ppc, 0xd0); /* enable interrupts */ 236 237 /* determine writeIntrThreshold 238 * empty the FIFO until serviceIntr is set 239 */ 240 for (i=ppc->ppc_fifo; i>0; i--) { 241 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) { 242 LOG_PPC(__func__, ppc, "invalid data in FIFO"); 243 goto error; 244 } 245 if (r_ecr(ppc) & PPC_SERVICE_INTR) { 246 /* writeIntrThreshold reached */ 247 ppc->ppc_wthr = ppc->ppc_fifo - i+1; 248 } 249 /* if FIFO empty before the last byte, error */ 250 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) { 251 LOG_PPC(__func__, ppc, "data lost in FIFO"); 252 goto error; 253 } 254 } 255 256 /* FIFO must be empty after the last byte */ 257 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 258 LOG_PPC(__func__, ppc, "can't empty the FIFO"); 259 goto error; 260 } 261 262 w_ctr(ppc, ctr_sav); 263 w_ecr(ppc, ecr_sav); 264 265 return (0); 266 267error: 268 w_ctr(ppc, ctr_sav); 269 w_ecr(ppc, ecr_sav); 270 271 return (EINVAL); 272} 273 274static int 275ppc_detect_port(struct ppc_data *ppc) 276{ 277 278 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */ 279 w_dtr(ppc, 0xaa); 280 if (r_dtr(ppc) != 0xaa) 281 return (0); 282 283 return (1); 284} 285 286/* 287 * EPP timeout, according to the PC87332 manual 288 * Semantics of clearing EPP timeout bit. 289 * PC87332 - reading SPP_STR does it... 290 * SMC - write 1 to EPP timeout bit XXX 291 * Others - (?) write 0 to EPP timeout bit 292 */ 293static void 294ppc_reset_epp_timeout(struct ppc_data *ppc) 295{ 296 register char r; 297 298 r = r_str(ppc); 299 w_str(ppc, r | 0x1); 300 w_str(ppc, r & 0xfe); 301 302 return; 303} 304 305static int 306ppc_check_epp_timeout(struct ppc_data *ppc) 307{ 308 ppc_reset_epp_timeout(ppc); 309 310 return (!(r_str(ppc) & TIMEOUT)); 311} 312 313/* 314 * Configure current operating mode 315 */ 316static int 317ppc_generic_setmode(struct ppc_data *ppc, int mode) 318{ 319 u_char ecr = 0; 320 321 /* check if mode is available */ 322 if (mode && !(ppc->ppc_avm & mode)) 323 return (EINVAL); 324 325 /* if ECP mode, configure ecr register */ 326 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 327 /* return to byte mode (keeping direction bit), 328 * no interrupt, no DMA to be able to change to 329 * ECP 330 */ 331 w_ecr(ppc, PPC_ECR_RESET); 332 ecr = PPC_DISABLE_INTR; 333 334 if (mode & PPB_EPP) 335 return (EINVAL); 336 else if (mode & PPB_ECP) 337 /* select ECP mode */ 338 ecr |= PPC_ECR_ECP; 339 else if (mode & PPB_PS2) 340 /* select PS2 mode with ECP */ 341 ecr |= PPC_ECR_PS2; 342 else 343 /* select COMPATIBLE/NIBBLE mode */ 344 ecr |= PPC_ECR_STD; 345 346 w_ecr(ppc, ecr); 347 } 348 349 ppc->ppc_mode = mode; 350 351 return (0); 352} 353 354/* 355 * The ppc driver is free to choose options like FIFO or DMA 356 * if ECP mode is available. 357 * 358 * The 'RAW' option allows the upper drivers to force the ppc mode 359 * even with FIFO, DMA available. 360 */ 361static int 362ppc_smclike_setmode(struct ppc_data *ppc, int mode) 363{ 364 u_char ecr = 0; 365 366 /* check if mode is available */ 367 if (mode && !(ppc->ppc_avm & mode)) 368 return (EINVAL); 369 370 /* if ECP mode, configure ecr register */ 371 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) { 372 /* return to byte mode (keeping direction bit), 373 * no interrupt, no DMA to be able to change to 374 * ECP or EPP mode 375 */ 376 w_ecr(ppc, PPC_ECR_RESET); 377 ecr = PPC_DISABLE_INTR; 378 379 if (mode & PPB_EPP) 380 /* select EPP mode */ 381 ecr |= PPC_ECR_EPP; 382 else if (mode & PPB_ECP) 383 /* select ECP mode */ 384 ecr |= PPC_ECR_ECP; 385 else if (mode & PPB_PS2) 386 /* select PS2 mode with ECP */ 387 ecr |= PPC_ECR_PS2; 388 else 389 /* select COMPATIBLE/NIBBLE mode */ 390 ecr |= PPC_ECR_STD; 391 392 w_ecr(ppc, ecr); 393 } 394 395 ppc->ppc_mode = mode; 396 397 return (0); 398} 399 400#ifdef PPC_PROBE_CHIPSET 401/* 402 * ppc_pc873xx_detect 403 * 404 * Probe for a Natsemi PC873xx-family part. 405 * 406 * References in this function are to the National Semiconductor 407 * PC87332 datasheet TL/C/11930, May 1995 revision. 408 */ 409static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0}; 410static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0}; 411static int pc873xx_irqtab[] = {5, 7, 5, 0}; 412 413static int pc873xx_regstab[] = { 414 PC873_FER, PC873_FAR, PC873_PTR, 415 PC873_FCR, PC873_PCR, PC873_PMC, 416 PC873_TUP, PC873_SID, PC873_PNP0, 417 PC873_PNP1, PC873_LPTBA, -1 418}; 419 420static char *pc873xx_rnametab[] = { 421 "FER", "FAR", "PTR", "FCR", "PCR", 422 "PMC", "TUP", "SID", "PNP0", "PNP1", 423 "LPTBA", NULL 424}; 425 426static int 427ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */ 428{ 429 static int index = 0; 430 int idport, irq; 431 int ptr, pcr, val, i; 432 433 while ((idport = pc873xx_basetab[index++])) { 434 435 /* XXX should check first to see if this location is already claimed */ 436 437 /* 438 * Pull the 873xx through the power-on ID cycle (2.2,1.). 439 * We can't use this to locate the chip as it may already have 440 * been used by the BIOS. 441 */ 442 (void)inb(idport); (void)inb(idport); 443 (void)inb(idport); (void)inb(idport); 444 445 /* 446 * Read the SID byte. Possible values are : 447 * 448 * 01010xxx PC87334 449 * 0001xxxx PC87332 450 * 01110xxx PC87306 451 * 00110xxx PC87303 452 */ 453 outb(idport, PC873_SID); 454 val = inb(idport + 1); 455 if ((val & 0xf0) == 0x10) { 456 ppc->ppc_model = NS_PC87332; 457 } else if ((val & 0xf8) == 0x70) { 458 ppc->ppc_model = NS_PC87306; 459 } else if ((val & 0xf8) == 0x50) { 460 ppc->ppc_model = NS_PC87334; 461 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the 462 documentation, but probing 463 yielded 0x40... */ 464 ppc->ppc_model = NS_PC87303; 465 } else { 466 if (bootverbose && (val != 0xff)) 467 printf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val); 468 continue ; /* not recognised */ 469 } 470 471 /* print registers */ 472 if (bootverbose) { 473 printf("PC873xx"); 474 for (i=0; pc873xx_regstab[i] != -1; i++) { 475 outb(idport, pc873xx_regstab[i]); 476 printf(" %s=0x%x", pc873xx_rnametab[i], 477 inb(idport + 1) & 0xff); 478 } 479 printf("\n"); 480 } 481 482 /* 483 * We think we have one. Is it enabled and where we want it to be? 484 */ 485 outb(idport, PC873_FER); 486 val = inb(idport + 1); 487 if (!(val & PC873_PPENABLE)) { 488 if (bootverbose) 489 printf("PC873xx parallel port disabled\n"); 490 continue; 491 } 492 outb(idport, PC873_FAR); 493 val = inb(idport + 1); 494 /* XXX we should create a driver instance for every port found */ 495 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) { 496 497 /* First try to change the port address to that requested... */ 498 499 switch(ppc->ppc_base) { 500 case 0x378: 501 val &= 0xfc; 502 break; 503 504 case 0x3bc: 505 val &= 0xfd; 506 break; 507 508 case 0x278: 509 val &= 0xfe; 510 break; 511 512 default: 513 val &= 0xfd; 514 break; 515 } 516 517 outb(idport, PC873_FAR); 518 outb(idport + 1, val); 519 outb(idport + 1, val); 520 521 /* Check for success by reading back the value we supposedly 522 wrote and comparing...*/ 523 524 outb(idport, PC873_FAR); 525 val = inb(idport + 1) & 0x3; 526 527 /* If we fail, report the failure... */ 528 529 if (pc873xx_porttab[val] != ppc->ppc_base) { 530 if (bootverbose) 531 printf("PC873xx at 0x%x not for driver at port 0x%x\n", 532 pc873xx_porttab[val], ppc->ppc_base); 533 } 534 continue; 535 } 536 537 outb(idport, PC873_PTR); 538 ptr = inb(idport + 1); 539 540 /* get irq settings */ 541 if (ppc->ppc_base == 0x378) 542 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5; 543 else 544 irq = pc873xx_irqtab[val]; 545 546 if (bootverbose) 547 printf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base); 548 549 /* 550 * Check if irq settings are correct 551 */ 552 if (irq != ppc->ppc_irq) { 553 /* 554 * If the chipset is not locked and base address is 0x378, 555 * we have another chance 556 */ 557 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) { 558 if (ppc->ppc_irq == 7) { 559 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 560 outb(idport + 1, (ptr | PC873_LPTBIRQ7)); 561 } else { 562 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 563 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7)); 564 } 565 if (bootverbose) 566 printf("PC873xx irq set to %d\n", ppc->ppc_irq); 567 } else { 568 if (bootverbose) 569 printf("PC873xx sorry, can't change irq setting\n"); 570 } 571 } else { 572 if (bootverbose) 573 printf("PC873xx irq settings are correct\n"); 574 } 575 576 outb(idport, PC873_PCR); 577 pcr = inb(idport + 1); 578 579 if ((ptr & PC873_CFGLOCK) || !chipset_mode) { 580 if (bootverbose) 581 printf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked"); 582 583 ppc->ppc_avm |= PPB_NIBBLE; 584 if (bootverbose) 585 printf(", NIBBLE"); 586 587 if (pcr & PC873_EPPEN) { 588 ppc->ppc_avm |= PPB_EPP; 589 590 if (bootverbose) 591 printf(", EPP"); 592 593 if (pcr & PC873_EPP19) 594 ppc->ppc_epp = EPP_1_9; 595 else 596 ppc->ppc_epp = EPP_1_7; 597 598 if ((ppc->ppc_model == NS_PC87332) && bootverbose) { 599 outb(idport, PC873_PTR); 600 ptr = inb(idport + 1); 601 if (ptr & PC873_EPPRDIR) 602 printf(", Regular mode"); 603 else 604 printf(", Automatic mode"); 605 } 606 } else if (pcr & PC873_ECPEN) { 607 ppc->ppc_avm |= PPB_ECP; 608 if (bootverbose) 609 printf(", ECP"); 610 611 if (pcr & PC873_ECPCLK) { /* XXX */ 612 ppc->ppc_avm |= PPB_PS2; 613 if (bootverbose) 614 printf(", PS/2"); 615 } 616 } else { 617 outb(idport, PC873_PTR); 618 ptr = inb(idport + 1); 619 if (ptr & PC873_EXTENDED) { 620 ppc->ppc_avm |= PPB_SPP; 621 if (bootverbose) 622 printf(", SPP"); 623 } 624 } 625 } else { 626 if (bootverbose) 627 printf("PC873xx unlocked"); 628 629 if (chipset_mode & PPB_ECP) { 630 if ((chipset_mode & PPB_EPP) && bootverbose) 631 printf(", ECP+EPP not supported"); 632 633 pcr &= ~PC873_EPPEN; 634 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */ 635 outb(idport + 1, pcr); 636 outb(idport + 1, pcr); 637 638 if (bootverbose) 639 printf(", ECP"); 640 641 } else if (chipset_mode & PPB_EPP) { 642 pcr &= ~(PC873_ECPEN | PC873_ECPCLK); 643 pcr |= (PC873_EPPEN | PC873_EPP19); 644 outb(idport + 1, pcr); 645 outb(idport + 1, pcr); 646 647 ppc->ppc_epp = EPP_1_9; /* XXX */ 648 649 if (bootverbose) 650 printf(", EPP1.9"); 651 652 /* enable automatic direction turnover */ 653 if (ppc->ppc_model == NS_PC87332) { 654 outb(idport, PC873_PTR); 655 ptr = inb(idport + 1); 656 ptr &= ~PC873_EPPRDIR; 657 outb(idport + 1, ptr); 658 outb(idport + 1, ptr); 659 660 if (bootverbose) 661 printf(", Automatic mode"); 662 } 663 } else { 664 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN); 665 outb(idport + 1, pcr); 666 outb(idport + 1, pcr); 667 668 /* configure extended bit in PTR */ 669 outb(idport, PC873_PTR); 670 ptr = inb(idport + 1); 671 672 if (chipset_mode & PPB_PS2) { 673 ptr |= PC873_EXTENDED; 674 675 if (bootverbose) 676 printf(", PS/2"); 677 678 } else { 679 /* default to NIBBLE mode */ 680 ptr &= ~PC873_EXTENDED; 681 682 if (bootverbose) 683 printf(", NIBBLE"); 684 } 685 outb(idport + 1, ptr); 686 outb(idport + 1, ptr); 687 } 688 689 ppc->ppc_avm = chipset_mode; 690 } 691 692 if (bootverbose) 693 printf("\n"); 694 695 ppc->ppc_type = PPC_TYPE_GENERIC; 696 ppc_generic_setmode(ppc, chipset_mode); 697 698 return(chipset_mode); 699 } 700 return(-1); 701} 702 703/* 704 * ppc_smc37c66xgt_detect 705 * 706 * SMC FDC37C66xGT configuration. 707 */ 708static int 709ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode) 710{ 711 int s, i; 712 u_char r; 713 int type = -1; 714 int csr = SMC66x_CSR; /* initial value is 0x3F0 */ 715 716 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 }; 717 718 719#define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */ 720 721 /* 722 * Detection: enter configuration mode and read CRD register. 723 */ 724 725 s = splhigh(); 726 outb(csr, SMC665_iCODE); 727 outb(csr, SMC665_iCODE); 728 splx(s); 729 730 outb(csr, 0xd); 731 if (inb(cio) == 0x65) { 732 type = SMC_37C665GT; 733 goto config; 734 } 735 736 for (i = 0; i < 2; i++) { 737 s = splhigh(); 738 outb(csr, SMC666_iCODE); 739 outb(csr, SMC666_iCODE); 740 splx(s); 741 742 outb(csr, 0xd); 743 if (inb(cio) == 0x66) { 744 type = SMC_37C666GT; 745 break; 746 } 747 748 /* Another chance, CSR may be hard-configured to be at 0x370 */ 749 csr = SMC666_CSR; 750 } 751 752config: 753 /* 754 * If chipset not found, do not continue. 755 */ 756 if (type == -1) 757 return (-1); 758 759 /* select CR1 */ 760 outb(csr, 0x1); 761 762 /* read the port's address: bits 0 and 1 of CR1 */ 763 r = inb(cio) & SMC_CR1_ADDR; 764 if (port_address[(int)r] != ppc->ppc_base) 765 return (-1); 766 767 ppc->ppc_model = type; 768 769 /* 770 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration 771 * If SPP mode is detected, try to set ECP+EPP mode 772 */ 773 774 if (bootverbose) { 775 outb(csr, 0x1); 776 printf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit, 777 inb(cio) & 0xff); 778 779 outb(csr, 0x4); 780 printf(" CR4=0x%x", inb(cio) & 0xff); 781 } 782 783 /* select CR1 */ 784 outb(csr, 0x1); 785 786 if (!chipset_mode) { 787 /* autodetect mode */ 788 789 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 790 if (type == SMC_37C666GT) { 791 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 792 if (bootverbose) 793 printf(" configuration hardwired, supposing " \ 794 "ECP+EPP SPP"); 795 796 } else 797 if ((inb(cio) & SMC_CR1_MODE) == 0) { 798 /* already in extended parallel port mode, read CR4 */ 799 outb(csr, 0x4); 800 r = (inb(cio) & SMC_CR4_EMODE); 801 802 switch (r) { 803 case SMC_SPP: 804 ppc->ppc_avm |= PPB_SPP; 805 if (bootverbose) 806 printf(" SPP"); 807 break; 808 809 case SMC_EPPSPP: 810 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 811 if (bootverbose) 812 printf(" EPP SPP"); 813 break; 814 815 case SMC_ECP: 816 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 817 if (bootverbose) 818 printf(" ECP SPP"); 819 break; 820 821 case SMC_ECPEPP: 822 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 823 if (bootverbose) 824 printf(" ECP+EPP SPP"); 825 break; 826 } 827 } else { 828 /* not an extended port mode */ 829 ppc->ppc_avm |= PPB_SPP; 830 if (bootverbose) 831 printf(" SPP"); 832 } 833 834 } else { 835 /* mode forced */ 836 ppc->ppc_avm = chipset_mode; 837 838 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */ 839 if (type == SMC_37C666GT) 840 goto end_detect; 841 842 r = inb(cio); 843 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) { 844 /* do not use ECP when the mode is not forced to */ 845 outb(cio, r | SMC_CR1_MODE); 846 if (bootverbose) 847 printf(" SPP"); 848 } else { 849 /* an extended mode is selected */ 850 outb(cio, r & ~SMC_CR1_MODE); 851 852 /* read CR4 register and reset mode field */ 853 outb(csr, 0x4); 854 r = inb(cio) & ~SMC_CR4_EMODE; 855 856 if (chipset_mode & PPB_ECP) { 857 if (chipset_mode & PPB_EPP) { 858 outb(cio, r | SMC_ECPEPP); 859 if (bootverbose) 860 printf(" ECP+EPP"); 861 } else { 862 outb(cio, r | SMC_ECP); 863 if (bootverbose) 864 printf(" ECP"); 865 } 866 } else { 867 /* PPB_EPP is set */ 868 outb(cio, r | SMC_EPPSPP); 869 if (bootverbose) 870 printf(" EPP SPP"); 871 } 872 } 873 ppc->ppc_avm = chipset_mode; 874 } 875 876 /* set FIFO threshold to 16 */ 877 if (ppc->ppc_avm & PPB_ECP) { 878 /* select CRA */ 879 outb(csr, 0xa); 880 outb(cio, 16); 881 } 882 883end_detect: 884 885 if (bootverbose) 886 printf ("\n"); 887 888 if (ppc->ppc_avm & PPB_EPP) { 889 /* select CR4 */ 890 outb(csr, 0x4); 891 r = inb(cio); 892 893 /* 894 * Set the EPP protocol... 895 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7 896 */ 897 if (ppc->ppc_epp == EPP_1_9) 898 outb(cio, (r & ~SMC_CR4_EPPTYPE)); 899 else 900 outb(cio, (r | SMC_CR4_EPPTYPE)); 901 } 902 903 /* end config mode */ 904 outb(csr, 0xaa); 905 906 ppc->ppc_type = PPC_TYPE_SMCLIKE; 907 ppc_smclike_setmode(ppc, chipset_mode); 908 909 return (chipset_mode); 910} 911 912/* 913 * SMC FDC37C935 configuration 914 * Found on many Alpha machines 915 */ 916static int 917ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode) 918{ 919 int s; 920 int type = -1; 921 922 s = splhigh(); 923 outb(SMC935_CFG, 0x55); /* enter config mode */ 924 outb(SMC935_CFG, 0x55); 925 splx(s); 926 927 outb(SMC935_IND, SMC935_ID); /* check device id */ 928 if (inb(SMC935_DAT) == 0x2) 929 type = SMC_37C935; 930 931 if (type == -1) { 932 outb(SMC935_CFG, 0xaa); /* exit config mode */ 933 return (-1); 934 } 935 936 ppc->ppc_model = type; 937 938 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */ 939 outb(SMC935_DAT, 3); /* which is logical device 3 */ 940 941 /* set io port base */ 942 outb(SMC935_IND, SMC935_PORTHI); 943 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8)); 944 outb(SMC935_IND, SMC935_PORTLO); 945 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff)); 946 947 if (!chipset_mode) 948 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */ 949 else { 950 ppc->ppc_avm = chipset_mode; 951 outb(SMC935_IND, SMC935_PPMODE); 952 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */ 953 954 /* SPP + EPP or just plain SPP */ 955 if (chipset_mode & (PPB_SPP)) { 956 if (chipset_mode & PPB_EPP) { 957 if (ppc->ppc_epp == EPP_1_9) { 958 outb(SMC935_IND, SMC935_PPMODE); 959 outb(SMC935_DAT, SMC935_EPP19SPP); 960 } 961 if (ppc->ppc_epp == EPP_1_7) { 962 outb(SMC935_IND, SMC935_PPMODE); 963 outb(SMC935_DAT, SMC935_EPP17SPP); 964 } 965 } else { 966 outb(SMC935_IND, SMC935_PPMODE); 967 outb(SMC935_DAT, SMC935_SPP); 968 } 969 } 970 971 /* ECP + EPP or just plain ECP */ 972 if (chipset_mode & PPB_ECP) { 973 if (chipset_mode & PPB_EPP) { 974 if (ppc->ppc_epp == EPP_1_9) { 975 outb(SMC935_IND, SMC935_PPMODE); 976 outb(SMC935_DAT, SMC935_ECPEPP19); 977 } 978 if (ppc->ppc_epp == EPP_1_7) { 979 outb(SMC935_IND, SMC935_PPMODE); 980 outb(SMC935_DAT, SMC935_ECPEPP17); 981 } 982 } else { 983 outb(SMC935_IND, SMC935_PPMODE); 984 outb(SMC935_DAT, SMC935_ECP); 985 } 986 } 987 } 988 989 outb(SMC935_CFG, 0xaa); /* exit config mode */ 990 991 ppc->ppc_type = PPC_TYPE_SMCLIKE; 992 ppc_smclike_setmode(ppc, chipset_mode); 993 994 return (chipset_mode); 995} 996 997/* 998 * Winbond W83877F stuff 999 * 1000 * EFER: extended function enable register 1001 * EFIR: extended function index register 1002 * EFDR: extended function data register 1003 */ 1004#define efir ((efer == 0x250) ? 0x251 : 0x3f0) 1005#define efdr ((efer == 0x250) ? 0x252 : 0x3f1) 1006 1007static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 }; 1008static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 }; 1009static int w83877f_keyiter[] = { 1, 2, 2, 1 }; 1010static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 }; 1011 1012static int 1013ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode) 1014{ 1015 int i, j, efer; 1016 unsigned char r, hefere, hefras; 1017 1018 for (i = 0; i < 4; i ++) { 1019 /* first try to enable configuration registers */ 1020 efer = w83877f_efers[i]; 1021 1022 /* write the key to the EFER */ 1023 for (j = 0; j < w83877f_keyiter[i]; j ++) 1024 outb (efer, w83877f_keys[i]); 1025 1026 /* then check HEFERE and HEFRAS bits */ 1027 outb (efir, 0x0c); 1028 hefere = inb(efdr) & WINB_HEFERE; 1029 1030 outb (efir, 0x16); 1031 hefras = inb(efdr) & WINB_HEFRAS; 1032 1033 /* 1034 * HEFRAS HEFERE 1035 * 0 1 write 89h to 250h (power-on default) 1036 * 1 0 write 86h twice to 3f0h 1037 * 1 1 write 87h twice to 3f0h 1038 * 0 0 write 88h to 250h 1039 */ 1040 if ((hefere | hefras) == w83877f_hefs[i]) 1041 goto found; 1042 } 1043 1044 return (-1); /* failed */ 1045 1046found: 1047 /* check base port address - read from CR23 */ 1048 outb(efir, 0x23); 1049 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */ 1050 return (-1); 1051 1052 /* read CHIP ID from CR9/bits0-3 */ 1053 outb(efir, 0x9); 1054 1055 switch (inb(efdr) & WINB_CHIPID) { 1056 case WINB_W83877F_ID: 1057 ppc->ppc_model = WINB_W83877F; 1058 break; 1059 1060 case WINB_W83877AF_ID: 1061 ppc->ppc_model = WINB_W83877AF; 1062 break; 1063 1064 default: 1065 ppc->ppc_model = WINB_UNKNOWN; 1066 } 1067 1068 if (bootverbose) { 1069 /* dump of registers */ 1070 printf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]); 1071 for (i = 0; i <= 0xd; i ++) { 1072 outb(efir, i); 1073 printf("0x%x ", inb(efdr)); 1074 } 1075 for (i = 0x10; i <= 0x17; i ++) { 1076 outb(efir, i); 1077 printf("0x%x ", inb(efdr)); 1078 } 1079 outb(efir, 0x1e); 1080 printf("0x%x ", inb(efdr)); 1081 for (i = 0x20; i <= 0x29; i ++) { 1082 outb(efir, i); 1083 printf("0x%x ", inb(efdr)); 1084 } 1085 printf("\n"); 1086 printf("ppc%d:", ppc->ppc_unit); 1087 } 1088 1089 ppc->ppc_type = PPC_TYPE_GENERIC; 1090 1091 if (!chipset_mode) { 1092 /* autodetect mode */ 1093 1094 /* select CR0 */ 1095 outb(efir, 0x0); 1096 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1); 1097 1098 /* select CR9 */ 1099 outb(efir, 0x9); 1100 r |= (inb(efdr) & WINB_PRTMODS2); 1101 1102 switch (r) { 1103 case WINB_W83757: 1104 if (bootverbose) 1105 printf("ppc%d: W83757 compatible mode\n", 1106 ppc->ppc_unit); 1107 return (-1); /* generic or SMC-like */ 1108 1109 case WINB_EXTFDC: 1110 case WINB_EXTADP: 1111 case WINB_EXT2FDD: 1112 case WINB_JOYSTICK: 1113 if (bootverbose) 1114 printf(" not in parallel port mode\n"); 1115 return (-1); 1116 1117 case (WINB_PARALLEL | WINB_EPP_SPP): 1118 ppc->ppc_avm |= PPB_EPP | PPB_SPP; 1119 if (bootverbose) 1120 printf(" EPP SPP"); 1121 break; 1122 1123 case (WINB_PARALLEL | WINB_ECP): 1124 ppc->ppc_avm |= PPB_ECP | PPB_SPP; 1125 if (bootverbose) 1126 printf(" ECP SPP"); 1127 break; 1128 1129 case (WINB_PARALLEL | WINB_ECP_EPP): 1130 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP; 1131 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1132 1133 if (bootverbose) 1134 printf(" ECP+EPP SPP"); 1135 break; 1136 default: 1137 printf("%s: unknown case (0x%x)!\n", __func__, r); 1138 } 1139 1140 } else { 1141 /* mode forced */ 1142 1143 /* select CR9 and set PRTMODS2 bit */ 1144 outb(efir, 0x9); 1145 outb(efdr, inb(efdr) & ~WINB_PRTMODS2); 1146 1147 /* select CR0 and reset PRTMODSx bits */ 1148 outb(efir, 0x0); 1149 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1)); 1150 1151 if (chipset_mode & PPB_ECP) { 1152 if (chipset_mode & PPB_EPP) { 1153 outb(efdr, inb(efdr) | WINB_ECP_EPP); 1154 if (bootverbose) 1155 printf(" ECP+EPP"); 1156 1157 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1158 1159 } else { 1160 outb(efdr, inb(efdr) | WINB_ECP); 1161 if (bootverbose) 1162 printf(" ECP"); 1163 } 1164 } else { 1165 /* select EPP_SPP otherwise */ 1166 outb(efdr, inb(efdr) | WINB_EPP_SPP); 1167 if (bootverbose) 1168 printf(" EPP SPP"); 1169 } 1170 ppc->ppc_avm = chipset_mode; 1171 } 1172 1173 if (bootverbose) 1174 printf("\n"); 1175 1176 /* exit configuration mode */ 1177 outb(efer, 0xaa); 1178 1179 switch (ppc->ppc_type) { 1180 case PPC_TYPE_SMCLIKE: 1181 ppc_smclike_setmode(ppc, chipset_mode); 1182 break; 1183 default: 1184 ppc_generic_setmode(ppc, chipset_mode); 1185 break; 1186 } 1187 1188 return (chipset_mode); 1189} 1190#endif 1191 1192/* 1193 * ppc_generic_detect 1194 */ 1195static int 1196ppc_generic_detect(struct ppc_data *ppc, int chipset_mode) 1197{ 1198 /* default to generic */ 1199 ppc->ppc_type = PPC_TYPE_GENERIC; 1200 1201 if (bootverbose) 1202 printf("ppc%d:", ppc->ppc_unit); 1203 1204 /* first, check for ECP */ 1205 w_ecr(ppc, PPC_ECR_PS2); 1206 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) { 1207 ppc->ppc_dtm |= PPB_ECP | PPB_SPP; 1208 if (bootverbose) 1209 printf(" ECP SPP"); 1210 1211 /* search for SMC style ECP+EPP mode */ 1212 w_ecr(ppc, PPC_ECR_EPP); 1213 } 1214 1215 /* try to reset EPP timeout bit */ 1216 if (ppc_check_epp_timeout(ppc)) { 1217 ppc->ppc_dtm |= PPB_EPP; 1218 1219 if (ppc->ppc_dtm & PPB_ECP) { 1220 /* SMC like chipset found */ 1221 ppc->ppc_model = SMC_LIKE; 1222 ppc->ppc_type = PPC_TYPE_SMCLIKE; 1223 1224 if (bootverbose) 1225 printf(" ECP+EPP"); 1226 } else { 1227 if (bootverbose) 1228 printf(" EPP"); 1229 } 1230 } else { 1231 /* restore to standard mode */ 1232 w_ecr(ppc, PPC_ECR_STD); 1233 } 1234 1235 /* XXX try to detect NIBBLE and PS2 modes */ 1236 ppc->ppc_dtm |= PPB_NIBBLE; 1237 1238 if (bootverbose) 1239 printf(" SPP"); 1240 1241 if (chipset_mode) 1242 ppc->ppc_avm = chipset_mode; 1243 else 1244 ppc->ppc_avm = ppc->ppc_dtm; 1245 1246 if (bootverbose) 1247 printf("\n"); 1248 1249 switch (ppc->ppc_type) { 1250 case PPC_TYPE_SMCLIKE: 1251 ppc_smclike_setmode(ppc, chipset_mode); 1252 break; 1253 default: 1254 ppc_generic_setmode(ppc, chipset_mode); 1255 break; 1256 } 1257 1258 return (chipset_mode); 1259} 1260 1261/* 1262 * ppc_detect() 1263 * 1264 * mode is the mode suggested at boot 1265 */ 1266static int 1267ppc_detect(struct ppc_data *ppc, int chipset_mode) { 1268 1269#ifdef PPC_PROBE_CHIPSET 1270 int i, mode; 1271 1272 /* list of supported chipsets */ 1273 int (*chipset_detect[])(struct ppc_data *, int) = { 1274 ppc_pc873xx_detect, 1275 ppc_smc37c66xgt_detect, 1276 ppc_w83877f_detect, 1277 ppc_smc37c935_detect, 1278 ppc_generic_detect, 1279 NULL 1280 }; 1281#endif 1282 1283 /* if can't find the port and mode not forced return error */ 1284 if (!ppc_detect_port(ppc) && chipset_mode == 0) 1285 return (EIO); /* failed, port not present */ 1286 1287 /* assume centronics compatible mode is supported */ 1288 ppc->ppc_avm = PPB_COMPATIBLE; 1289 1290#ifdef PPC_PROBE_CHIPSET 1291 /* we have to differenciate available chipset modes, 1292 * chipset running modes and IEEE-1284 operating modes 1293 * 1294 * after detection, the port must support running in compatible mode 1295 */ 1296 if (ppc->ppc_flags & 0x40) { 1297 if (bootverbose) 1298 printf("ppc: chipset forced to generic\n"); 1299#endif 1300 1301 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode); 1302 1303#ifdef PPC_PROBE_CHIPSET 1304 } else { 1305 for (i=0; chipset_detect[i] != NULL; i++) { 1306 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) { 1307 ppc->ppc_mode = mode; 1308 break; 1309 } 1310 } 1311 } 1312#endif 1313 1314 /* configure/detect ECP FIFO */ 1315 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80)) 1316 ppc_detect_fifo(ppc); 1317 1318 return (0); 1319} 1320 1321/* 1322 * ppc_exec_microseq() 1323 * 1324 * Execute a microsequence. 1325 * Microsequence mechanism is supposed to handle fast I/O operations. 1326 */ 1327int 1328ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq) 1329{ 1330 struct ppc_data *ppc = DEVTOSOFTC(dev); 1331 struct ppb_microseq *mi; 1332 char cc, *p; 1333 int i, iter, len; 1334 int error; 1335 1336 register int reg; 1337 register char mask; 1338 register int accum = 0; 1339 register char *ptr = 0; 1340 1341 struct ppb_microseq *stack = 0; 1342 1343/* microsequence registers are equivalent to PC-like port registers */ 1344 1345#define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register)) 1346#define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte)) 1347 1348#define INCR_PC (mi ++) /* increment program counter */ 1349 1350 mi = *p_msq; 1351 for (;;) { 1352 switch (mi->opcode) { 1353 case MS_OP_RSET: 1354 cc = r_reg(mi->arg[0].i, ppc); 1355 cc &= (char)mi->arg[2].i; /* clear mask */ 1356 cc |= (char)mi->arg[1].i; /* assert mask */ 1357 w_reg(mi->arg[0].i, ppc, cc); 1358 INCR_PC; 1359 break; 1360 1361 case MS_OP_RASSERT_P: 1362 reg = mi->arg[1].i; 1363 ptr = ppc->ppc_ptr; 1364 1365 if ((len = mi->arg[0].i) == MS_ACCUM) { 1366 accum = ppc->ppc_accum; 1367 for (; accum; accum--) 1368 w_reg(reg, ppc, *ptr++); 1369 ppc->ppc_accum = accum; 1370 } else 1371 for (i=0; i<len; i++) 1372 w_reg(reg, ppc, *ptr++); 1373 ppc->ppc_ptr = ptr; 1374 1375 INCR_PC; 1376 break; 1377 1378 case MS_OP_RFETCH_P: 1379 reg = mi->arg[1].i; 1380 mask = (char)mi->arg[2].i; 1381 ptr = ppc->ppc_ptr; 1382 1383 if ((len = mi->arg[0].i) == MS_ACCUM) { 1384 accum = ppc->ppc_accum; 1385 for (; accum; accum--) 1386 *ptr++ = r_reg(reg, ppc) & mask; 1387 ppc->ppc_accum = accum; 1388 } else 1389 for (i=0; i<len; i++) 1390 *ptr++ = r_reg(reg, ppc) & mask; 1391 ppc->ppc_ptr = ptr; 1392 1393 INCR_PC; 1394 break; 1395 1396 case MS_OP_RFETCH: 1397 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) & 1398 (char)mi->arg[1].i; 1399 INCR_PC; 1400 break; 1401 1402 case MS_OP_RASSERT: 1403 case MS_OP_DELAY: 1404 1405 /* let's suppose the next instr. is the same */ 1406 prefetch: 1407 for (;mi->opcode == MS_OP_RASSERT; INCR_PC) 1408 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i); 1409 1410 if (mi->opcode == MS_OP_DELAY) { 1411 DELAY(mi->arg[0].i); 1412 INCR_PC; 1413 goto prefetch; 1414 } 1415 break; 1416 1417 case MS_OP_ADELAY: 1418 if (mi->arg[0].i) 1419 tsleep(NULL, PPBPRI, "ppbdelay", 1420 mi->arg[0].i * (hz/1000)); 1421 INCR_PC; 1422 break; 1423 1424 case MS_OP_TRIG: 1425 reg = mi->arg[0].i; 1426 iter = mi->arg[1].i; 1427 p = (char *)mi->arg[2].p; 1428 1429 /* XXX delay limited to 255 us */ 1430 for (i=0; i<iter; i++) { 1431 w_reg(reg, ppc, *p++); 1432 DELAY((unsigned char)*p++); 1433 } 1434 INCR_PC; 1435 break; 1436 1437 case MS_OP_SET: 1438 ppc->ppc_accum = mi->arg[0].i; 1439 INCR_PC; 1440 break; 1441 1442 case MS_OP_DBRA: 1443 if (--ppc->ppc_accum > 0) 1444 mi += mi->arg[0].i; 1445 INCR_PC; 1446 break; 1447 1448 case MS_OP_BRSET: 1449 cc = r_str(ppc); 1450 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i) 1451 mi += mi->arg[1].i; 1452 INCR_PC; 1453 break; 1454 1455 case MS_OP_BRCLEAR: 1456 cc = r_str(ppc); 1457 if ((cc & (char)mi->arg[0].i) == 0) 1458 mi += mi->arg[1].i; 1459 INCR_PC; 1460 break; 1461 1462 case MS_OP_BRSTAT: 1463 cc = r_str(ppc); 1464 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) == 1465 (char)mi->arg[0].i) 1466 mi += mi->arg[2].i; 1467 INCR_PC; 1468 break; 1469 1470 case MS_OP_C_CALL: 1471 /* 1472 * If the C call returns !0 then end the microseq. 1473 * The current state of ptr is passed to the C function 1474 */ 1475 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr))) 1476 return (error); 1477 1478 INCR_PC; 1479 break; 1480 1481 case MS_OP_PTR: 1482 ppc->ppc_ptr = (char *)mi->arg[0].p; 1483 INCR_PC; 1484 break; 1485 1486 case MS_OP_CALL: 1487 if (stack) 1488 panic("%s: too much calls", __func__); 1489 1490 if (mi->arg[0].p) { 1491 /* store the state of the actual 1492 * microsequence 1493 */ 1494 stack = mi; 1495 1496 /* jump to the new microsequence */ 1497 mi = (struct ppb_microseq *)mi->arg[0].p; 1498 } else 1499 INCR_PC; 1500 1501 break; 1502 1503 case MS_OP_SUBRET: 1504 /* retrieve microseq and pc state before the call */ 1505 mi = stack; 1506 1507 /* reset the stack */ 1508 stack = 0; 1509 1510 /* XXX return code */ 1511 1512 INCR_PC; 1513 break; 1514 1515 case MS_OP_PUT: 1516 case MS_OP_GET: 1517 case MS_OP_RET: 1518 /* can't return to ppb level during the execution 1519 * of a submicrosequence */ 1520 if (stack) 1521 panic("%s: can't return to ppb level", 1522 __func__); 1523 1524 /* update pc for ppb level of execution */ 1525 *p_msq = mi; 1526 1527 /* return to ppb level of execution */ 1528 return (0); 1529 1530 default: 1531 panic("%s: unknown microsequence opcode 0x%x", 1532 __func__, mi->opcode); 1533 } 1534 } 1535 1536 /* unreached */ 1537} 1538 1539static void 1540ppcintr(void *arg) 1541{ 1542 device_t dev = (device_t)arg; 1543 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev); 1544 u_char ctr, ecr, str; 1545 1546 str = r_str(ppc); 1547 ctr = r_ctr(ppc); 1548 ecr = r_ecr(ppc); 1549 1550#if PPC_DEBUG > 1 1551 printf("![%x/%x/%x]", ctr, ecr, str); 1552#endif 1553 1554 /* don't use ecp mode with IRQENABLE set */ 1555 if (ctr & IRQENABLE) { 1556 return; 1557 } 1558 1559 /* interrupts are generated by nFault signal 1560 * only in ECP mode */ 1561 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) { 1562 /* check if ppc driver has programmed the 1563 * nFault interrupt */ 1564 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) { 1565 1566 w_ecr(ppc, ecr | PPC_nFAULT_INTR); 1567 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT; 1568 } else { 1569 /* shall be handled by underlying layers XXX */ 1570 return; 1571 } 1572 } 1573 1574 if (ppc->ppc_irqstat & PPC_IRQ_DMA) { 1575 /* disable interrupts (should be done by hardware though) */ 1576 w_ecr(ppc, ecr | PPC_SERVICE_INTR); 1577 ppc->ppc_irqstat &= ~PPC_IRQ_DMA; 1578 ecr = r_ecr(ppc); 1579 1580 /* check if DMA completed */ 1581 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) { 1582#ifdef PPC_DEBUG 1583 printf("a"); 1584#endif 1585 /* stop DMA */ 1586 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA); 1587 ecr = r_ecr(ppc); 1588 1589 if (ppc->ppc_dmastat == PPC_DMA_STARTED) { 1590#ifdef PPC_DEBUG 1591 printf("d"); 1592#endif 1593 isa_dmadone( 1594 ppc->ppc_dmaflags, 1595 ppc->ppc_dmaddr, 1596 ppc->ppc_dmacnt, 1597 ppc->ppc_dmachan); 1598 1599 ppc->ppc_dmastat = PPC_DMA_COMPLETE; 1600 1601 /* wakeup the waiting process */ 1602 wakeup(ppc); 1603 } 1604 } 1605 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) { 1606 1607 /* classic interrupt I/O */ 1608 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO; 1609 } 1610 1611 return; 1612} 1613 1614int 1615ppc_read(device_t dev, char *buf, int len, int mode) 1616{ 1617 return (EINVAL); 1618} 1619 1620/* 1621 * Call this function if you want to send data in any advanced mode 1622 * of your parallel port: FIFO, DMA 1623 * 1624 * If what you want is not possible (no ECP, no DMA...), 1625 * EINVAL is returned 1626 */ 1627int 1628ppc_write(device_t dev, char *buf, int len, int how) 1629{ 1630 struct ppc_data *ppc = DEVTOSOFTC(dev); 1631 char ecr, ecr_sav, ctr, ctr_sav; 1632 int s, error = 0; 1633 int spin; 1634 1635#ifdef PPC_DEBUG 1636 printf("w"); 1637#endif 1638 1639 ecr_sav = r_ecr(ppc); 1640 ctr_sav = r_ctr(ppc); 1641 1642 /* 1643 * Send buffer with DMA, FIFO and interrupts 1644 */ 1645 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) { 1646 1647 if (ppc->ppc_dmachan > 0) { 1648 1649 /* byte mode, no intr, no DMA, dir=0, flush fifo 1650 */ 1651 ecr = PPC_ECR_STD | PPC_DISABLE_INTR; 1652 w_ecr(ppc, ecr); 1653 1654 /* disable nAck interrupts */ 1655 ctr = r_ctr(ppc); 1656 ctr &= ~IRQENABLE; 1657 w_ctr(ppc, ctr); 1658 1659 ppc->ppc_dmaflags = 0; 1660 ppc->ppc_dmaddr = (caddr_t)buf; 1661 ppc->ppc_dmacnt = (u_int)len; 1662 1663 switch (ppc->ppc_mode) { 1664 case PPB_COMPATIBLE: 1665 /* compatible mode with FIFO, no intr, DMA, dir=0 */ 1666 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1667 break; 1668 case PPB_ECP: 1669 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA; 1670 break; 1671 default: 1672 error = EINVAL; 1673 goto error; 1674 } 1675 1676 w_ecr(ppc, ecr); 1677 ecr = r_ecr(ppc); 1678 1679 /* enter splhigh() not to be preempted 1680 * by the dma interrupt, we may miss 1681 * the wakeup otherwise 1682 */ 1683 s = splhigh(); 1684 1685 ppc->ppc_dmastat = PPC_DMA_INIT; 1686 1687 /* enable interrupts */ 1688 ecr &= ~PPC_SERVICE_INTR; 1689 ppc->ppc_irqstat = PPC_IRQ_DMA; 1690 w_ecr(ppc, ecr); 1691 1692 isa_dmastart( 1693 ppc->ppc_dmaflags, 1694 ppc->ppc_dmaddr, 1695 ppc->ppc_dmacnt, 1696 ppc->ppc_dmachan); 1697#ifdef PPC_DEBUG 1698 printf("s%d", ppc->ppc_dmacnt); 1699#endif 1700 ppc->ppc_dmastat = PPC_DMA_STARTED; 1701 1702 /* Wait for the DMA completed interrupt. We hope we won't 1703 * miss it, otherwise a signal will be necessary to unlock the 1704 * process. 1705 */ 1706 do { 1707 /* release CPU */ 1708 error = tsleep(ppc, 1709 PPBPRI | PCATCH, "ppcdma", 0); 1710 1711 } while (error == EWOULDBLOCK); 1712 1713 splx(s); 1714 1715 if (error) { 1716#ifdef PPC_DEBUG 1717 printf("i"); 1718#endif 1719 /* stop DMA */ 1720 isa_dmadone( 1721 ppc->ppc_dmaflags, ppc->ppc_dmaddr, 1722 ppc->ppc_dmacnt, ppc->ppc_dmachan); 1723 1724 /* no dma, no interrupt, flush the fifo */ 1725 w_ecr(ppc, PPC_ECR_RESET); 1726 1727 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1728 goto error; 1729 } 1730 1731 /* wait for an empty fifo */ 1732 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) { 1733 1734 for (spin=100; spin; spin--) 1735 if (r_ecr(ppc) & PPC_FIFO_EMPTY) 1736 goto fifo_empty; 1737#ifdef PPC_DEBUG 1738 printf("Z"); 1739#endif 1740 error = tsleep(ppc, PPBPRI | PCATCH, "ppcfifo", hz/100); 1741 if (error != EWOULDBLOCK) { 1742#ifdef PPC_DEBUG 1743 printf("I"); 1744#endif 1745 /* no dma, no interrupt, flush the fifo */ 1746 w_ecr(ppc, PPC_ECR_RESET); 1747 1748 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED; 1749 error = EINTR; 1750 goto error; 1751 } 1752 } 1753 1754fifo_empty: 1755 /* no dma, no interrupt, flush the fifo */ 1756 w_ecr(ppc, PPC_ECR_RESET); 1757 1758 } else 1759 error = EINVAL; /* XXX we should FIFO and 1760 * interrupts */ 1761 } else 1762 error = EINVAL; 1763 1764error: 1765 1766 /* PDRQ must be kept unasserted until nPDACK is 1767 * deasserted for a minimum of 350ns (SMC datasheet) 1768 * 1769 * Consequence may be a FIFO that never empty 1770 */ 1771 DELAY(1); 1772 1773 w_ecr(ppc, ecr_sav); 1774 w_ctr(ppc, ctr_sav); 1775 1776 return (error); 1777} 1778 1779void 1780ppc_reset_epp(device_t dev) 1781{ 1782 struct ppc_data *ppc = DEVTOSOFTC(dev); 1783 1784 ppc_reset_epp_timeout(ppc); 1785 1786 return; 1787} 1788 1789int 1790ppc_setmode(device_t dev, int mode) 1791{ 1792 struct ppc_data *ppc = DEVTOSOFTC(dev); 1793 1794 switch (ppc->ppc_type) { 1795 case PPC_TYPE_SMCLIKE: 1796 return (ppc_smclike_setmode(ppc, mode)); 1797 break; 1798 1799 case PPC_TYPE_GENERIC: 1800 default: 1801 return (ppc_generic_setmode(ppc, mode)); 1802 break; 1803 } 1804 1805 /* not reached */ 1806 return (ENXIO); 1807} 1808 1809static struct isa_pnp_id lpc_ids[] = { 1810 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */ 1811 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */ 1812 { 0 } 1813}; 1814 1815static int 1816ppc_isa_probe(device_t dev) 1817{ 1818 device_t parent; 1819 int error; 1820 1821 parent = device_get_parent(dev); 1822 1823 error = ISA_PNP_PROBE(parent, dev, lpc_ids); 1824 if (error == ENXIO) 1825 return (ENXIO); 1826 else if (error != 0) /* XXX shall be set after detection */ 1827 device_set_desc(dev, "Parallel port"); 1828 1829 return(ppc_probe(dev)); 1830} 1831 1832int 1833ppc_probe(device_t dev) 1834{ 1835#ifdef __i386__ 1836 static short next_bios_ppc = 0; 1837#endif 1838 struct ppc_data *ppc; 1839 int error; 1840 u_long port; 1841 1842 /* 1843 * Allocate the ppc_data structure. 1844 */ 1845 ppc = DEVTOSOFTC(dev); 1846 bzero(ppc, sizeof(struct ppc_data)); 1847 1848 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0; 1849 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0; 1850 1851 /* retrieve ISA parameters */ 1852 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL); 1853 1854#ifdef __i386__ 1855 /* 1856 * If port not specified, use bios list. 1857 */ 1858 if (error) { 1859 if((next_bios_ppc < BIOS_MAX_PPC) && 1860 (*(BIOS_PORTS+next_bios_ppc) != 0) ) { 1861 port = *(BIOS_PORTS+next_bios_ppc++); 1862 if (bootverbose) 1863 device_printf(dev, "parallel port found at 0x%x\n", 1864 (int) port); 1865 } else { 1866 device_printf(dev, "parallel port not found.\n"); 1867 return ENXIO; 1868 } 1869 bus_set_resource(dev, SYS_RES_IOPORT, 0, port, 1870 IO_LPTSIZE_EXTENDED); 1871 } 1872#endif 1873#ifdef __alpha__ 1874 /* 1875 * There isn't a bios list on alpha. Put it in the usual place. 1876 */ 1877 if (error) { 1878 bus_set_resource(dev, SYS_RES_IOPORT, 0, 0x3bc, 1879 IO_LPTSIZE_NORMAL); 1880 } 1881#endif 1882 1883 /* IO port is mandatory */ 1884 1885 /* Try "extended" IO port range...*/ 1886 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1887 &ppc->rid_ioport, 0, ~0, 1888 IO_LPTSIZE_EXTENDED, RF_ACTIVE); 1889 1890 if (ppc->res_ioport != 0) { 1891 if (bootverbose) 1892 device_printf(dev, "using extended I/O port range\n"); 1893 } else { 1894 /* Failed? If so, then try the "normal" IO port range... */ 1895 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT, 1896 &ppc->rid_ioport, 0, ~0, 1897 IO_LPTSIZE_NORMAL, 1898 RF_ACTIVE); 1899 if (ppc->res_ioport != 0) { 1900 if (bootverbose) 1901 device_printf(dev, "using normal I/O port range\n"); 1902 } else { 1903 device_printf(dev, "cannot reserve I/O port range\n"); 1904 goto error; 1905 } 1906 } 1907 1908 ppc->ppc_base = rman_get_start(ppc->res_ioport); 1909 1910 ppc->bsh = rman_get_bushandle(ppc->res_ioport); 1911 ppc->bst = rman_get_bustag(ppc->res_ioport); 1912 1913 ppc->ppc_flags = device_get_flags(dev); 1914 1915 if (!(ppc->ppc_flags & 0x20)) { 1916 ppc->res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1917 &ppc->rid_irq, 1918 RF_SHAREABLE); 1919 ppc->res_drq = bus_alloc_resource_any(dev, SYS_RES_DRQ, 1920 &ppc->rid_drq, 1921 RF_ACTIVE); 1922 } 1923 1924 if (ppc->res_irq) 1925 ppc->ppc_irq = rman_get_start(ppc->res_irq); 1926 if (ppc->res_drq) 1927 ppc->ppc_dmachan = rman_get_start(ppc->res_drq); 1928 1929 ppc->ppc_unit = device_get_unit(dev); 1930 ppc->ppc_model = GENERIC; 1931 1932 ppc->ppc_mode = PPB_COMPATIBLE; 1933 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4; 1934 1935 ppc->ppc_type = PPC_TYPE_GENERIC; 1936 1937 /* 1938 * Try to detect the chipset and its mode. 1939 */ 1940 if (ppc_detect(ppc, ppc->ppc_flags & 0xf)) 1941 goto error; 1942 1943 return (0); 1944 1945error: 1946 if (ppc->res_irq != 0) { 1947 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq, 1948 ppc->res_irq); 1949 } 1950 if (ppc->res_ioport != 0) { 1951 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1952 ppc->res_ioport); 1953 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport, 1954 ppc->res_ioport); 1955 } 1956 if (ppc->res_drq != 0) { 1957 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1958 ppc->res_drq); 1959 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq, 1960 ppc->res_drq); 1961 } 1962 return (ENXIO); 1963} 1964 1965int 1966ppc_attach(device_t dev) 1967{ 1968 struct ppc_data *ppc = DEVTOSOFTC(dev); 1969 1970 device_t ppbus; 1971 device_t parent = device_get_parent(dev); 1972 1973 device_printf(dev, "%s chipset (%s) in %s mode%s\n", 1974 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm], 1975 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ? 1976 ppc_epp_protocol[ppc->ppc_epp] : ""); 1977 1978 if (ppc->ppc_fifo) 1979 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n", 1980 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr); 1981 1982 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) { 1983 /* acquire the DMA channel forever */ /* XXX */ 1984 isa_dma_acquire(ppc->ppc_dmachan); 1985 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */ 1986 } 1987 1988 /* add ppbus as a child of this isa to parallel bridge */ 1989 ppbus = device_add_child(dev, "ppbus", -1); 1990 1991 /* 1992 * Probe the ppbus and attach devices found. 1993 */ 1994 device_probe_and_attach(ppbus); 1995 1996 /* register the ppc interrupt handler as default */ 1997 if (ppc->res_irq) { 1998 /* default to the tty mask for registration */ /* XXX */ 1999 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, INTR_TYPE_TTY, 2000 ppcintr, dev, &ppc->intr_cookie) == 0) { 2001 2002 /* remember the ppcintr is registered */ 2003 ppc->ppc_registered = 1; 2004 } 2005 } 2006 2007 return (0); 2008} 2009 2010u_char 2011ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte) 2012{ 2013 struct ppc_data *ppc = DEVTOSOFTC(ppcdev); 2014 switch (iop) { 2015 case PPB_OUTSB_EPP: 2016 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 2017 break; 2018 case PPB_OUTSW_EPP: 2019 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 2020 break; 2021 case PPB_OUTSL_EPP: 2022 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 2023 break; 2024 case PPB_INSB_EPP: 2025 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt); 2026 break; 2027 case PPB_INSW_EPP: 2028 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt); 2029 break; 2030 case PPB_INSL_EPP: 2031 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt); 2032 break; 2033 case PPB_RDTR: 2034 return (r_dtr(ppc)); 2035 case PPB_RSTR: 2036 return (r_str(ppc)); 2037 case PPB_RCTR: 2038 return (r_ctr(ppc)); 2039 case PPB_REPP_A: 2040 return (r_epp_A(ppc)); 2041 case PPB_REPP_D: 2042 return (r_epp_D(ppc)); 2043 case PPB_RECR: 2044 return (r_ecr(ppc)); 2045 case PPB_RFIFO: 2046 return (r_fifo(ppc)); 2047 case PPB_WDTR: 2048 w_dtr(ppc, byte); 2049 break; 2050 case PPB_WSTR: 2051 w_str(ppc, byte); 2052 break; 2053 case PPB_WCTR: 2054 w_ctr(ppc, byte); 2055 break; 2056 case PPB_WEPP_A: 2057 w_epp_A(ppc, byte); 2058 break; 2059 case PPB_WEPP_D: 2060 w_epp_D(ppc, byte); 2061 break; 2062 case PPB_WECR: 2063 w_ecr(ppc, byte); 2064 break; 2065 case PPB_WFIFO: 2066 w_fifo(ppc, byte); 2067 break; 2068 default: 2069 panic("%s: unknown I/O operation", __func__); 2070 break; 2071 } 2072 2073 return (0); /* not significative */ 2074} 2075 2076int 2077ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val) 2078{ 2079 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus); 2080 2081 switch (index) { 2082 case PPC_IVAR_EPP_PROTO: 2083 *val = (u_long)ppc->ppc_epp; 2084 break; 2085 case PPC_IVAR_IRQ: 2086 *val = (u_long)ppc->ppc_irq; 2087 break; 2088 default: 2089 return (ENOENT); 2090 } 2091 2092 return (0); 2093} 2094 2095/* 2096 * Resource is useless here since ppbus devices' interrupt handlers are 2097 * multiplexed to the same resource initially allocated by ppc 2098 */ 2099int 2100ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags, 2101 void (*ihand)(void *), void *arg, void **cookiep) 2102{ 2103 int error; 2104 struct ppc_data *ppc = DEVTOSOFTC(bus); 2105 2106 if (ppc->ppc_registered) { 2107 /* XXX refuse registration if DMA is in progress */ 2108 2109 /* first, unregister the default interrupt handler */ 2110 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus), 2111 bus, ppc->res_irq, ppc->intr_cookie))) 2112 return (error); 2113 2114/* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */ 2115/* ppc->res_irq); */ 2116 2117 /* DMA/FIFO operation won't be possible anymore */ 2118 ppc->ppc_registered = 0; 2119 } 2120 2121 /* pass registration to the upper layer, ignore the incoming resource */ 2122 return (BUS_SETUP_INTR(device_get_parent(bus), child, 2123 r, flags, ihand, arg, cookiep)); 2124} 2125 2126/* 2127 * When no underlying device has a registered interrupt, register the ppc 2128 * layer one 2129 */ 2130int 2131ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih) 2132{ 2133 int error; 2134 struct ppc_data *ppc = DEVTOSOFTC(bus); 2135 device_t parent = device_get_parent(bus); 2136 2137 /* pass unregistration to the upper layer */ 2138 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih))) 2139 return (error); 2140 2141 /* default to the tty mask for registration */ /* XXX */ 2142 if (ppc->ppc_irq && 2143 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq, 2144 INTR_TYPE_TTY, ppcintr, bus, &ppc->intr_cookie))) { 2145 2146 /* remember the ppcintr is registered */ 2147 ppc->ppc_registered = 1; 2148 } 2149 2150 return (error); 2151} 2152 2153DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0); 2154DRIVER_MODULE(ppc, acpi, ppc_driver, ppc_devclass, 0, 0); 2155