1/*-
2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 *    derived from this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 *
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30/*
31 * DEC PDQ FDDI Controller; code for BSD derived operating systems
32 *
33 *   This module supports the DEC DEFPA PCI FDDI Controller
34 */
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/kernel.h>
39#include <sys/socket.h>
40
41#include <sys/module.h>
42#include <sys/bus.h>
43
44#include <machine/bus.h>
45#include <machine/resource.h>
46#include <sys/rman.h>
47
48#include <net/if.h>
49#include <net/if_media.h>
50#include <net/fddi.h>
51
52#include <dev/pci/pcivar.h>
53#include <dev/pci/pcireg.h>
54
55#include <dev/pdq/pdq_freebsd.h>
56#include <dev/pdq/pdqreg.h>
57
58#define	DEC_VENDORID		0x1011
59#define	DEFPA_CHIPID		0x000F
60
61#define	DEFPA_LATENCY	0x88
62
63#define	PCI_CFLT	0x0C	/* Configuration Latency */
64#define	PCI_CBMA	0x10	/* Configuration Base Memory Address */
65#define	PCI_CBIO	0x14	/* Configuration Base I/O Address */
66
67static int	pdq_pci_probe		(device_t);
68static int	pdq_pci_attach		(device_t);
69static int	pdq_pci_detach		(device_t);
70static int	pdq_pci_shutdown	(device_t);
71static void	pdq_pci_ifintr		(void *);
72
73static void
74pdq_pci_ifintr(void *arg)
75{
76    pdq_softc_t *sc;
77
78    sc = arg;
79
80    PDQ_LOCK(sc);
81    (void) pdq_interrupt(sc->sc_pdq);
82    PDQ_UNLOCK(sc);
83
84    return;
85}
86
87/*
88 * This is the PCI configuration support.
89 */
90static int
91pdq_pci_probe(device_t dev)
92{
93    if (pci_get_vendor(dev) == DEC_VENDORID &&
94	    pci_get_device(dev) == DEFPA_CHIPID) {
95	device_set_desc(dev, "Digital DEFPA PCI FDDI Controller");
96	return (BUS_PROBE_DEFAULT);
97    }
98
99    return (ENXIO);
100}
101
102static int
103pdq_pci_attach(device_t dev)
104{
105    pdq_softc_t *sc;
106    u_int32_t command;
107    int error;
108
109    sc = device_get_softc(dev);
110
111    sc->dev = dev;
112
113    /*
114     * Map control/status registers.
115     */
116    pci_enable_busmaster(dev);
117
118    command = pci_read_config(dev, PCIR_LATTIMER, 1);
119    if (command < DEFPA_LATENCY) {
120	command = DEFPA_LATENCY;
121	pci_write_config(dev, PCIR_LATTIMER, command, 1);
122    }
123
124    sc->mem_rid = PCI_CBMA;
125    sc->mem_type = SYS_RES_MEMORY;
126    sc->mem = bus_alloc_resource_any(dev, sc->mem_type, &sc->mem_rid,
127				     RF_ACTIVE);
128    if (!sc->mem) {
129	device_printf(dev, "Unable to allocate I/O space resource.\n");
130	error = ENXIO;
131	goto bad;
132    }
133    sc->mem_bsh = rman_get_bushandle(sc->mem);
134    sc->mem_bst = rman_get_bustag(sc->mem);
135
136    sc->irq_rid = 0;
137    sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
138				     RF_SHAREABLE | RF_ACTIVE);
139    if (!sc->irq) {
140	device_printf(dev, "Unable to allocate interrupt resource.\n");
141	error = ENXIO;
142	goto bad;
143    }
144
145    error = pdq_ifattach(sc, sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, PDQ_DEFPA);
146    if (error)
147	goto bad;
148
149    error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, NULL,
150			   pdq_pci_ifintr, sc, &sc->irq_ih);
151    if (error) {
152	device_printf(dev, "Failed to setup interrupt handler.\n");
153	pdq_ifdetach(sc);
154	return (error);
155    }
156
157
158    return (0);
159bad:
160    pdq_free(dev);
161    return (error);
162}
163
164static int
165pdq_pci_detach (dev)
166    device_t	dev;
167{
168    pdq_softc_t *sc;
169
170    sc = device_get_softc(dev);
171    pdq_ifdetach(sc);
172
173    return (0);
174}
175
176static int
177pdq_pci_shutdown(device_t dev)
178{
179    pdq_softc_t *sc;
180
181    sc = device_get_softc(dev);
182    PDQ_LOCK(sc);
183    pdq_hwreset(sc->sc_pdq);
184    PDQ_UNLOCK(sc);
185
186    return (0);
187}
188
189static device_method_t pdq_pci_methods[] = {
190    /* Device interface */
191    DEVMETHOD(device_probe,	pdq_pci_probe),
192    DEVMETHOD(device_attach,	pdq_pci_attach),
193    DEVMETHOD(device_detach,	pdq_pci_detach),
194    DEVMETHOD(device_shutdown,	pdq_pci_shutdown),
195
196    { 0, 0 }
197};
198
199static driver_t pdq_pci_driver = {
200    "fpa",
201    pdq_pci_methods,
202    sizeof(pdq_softc_t),
203};
204
205DRIVER_MODULE(fpa, pci, pdq_pci_driver, pdq_devclass, 0, 0);
206MODULE_DEPEND(fpa, pci, 1, 1, 1);
207MODULE_DEPEND(fpa, fddi, 1, 1, 1);
208