pcivar.h revision 88375
198944Sobrien/* 298944Sobrien * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 398944Sobrien * All rights reserved. 498944Sobrien * 598944Sobrien * Redistribution and use in source and binary forms, with or without 698944Sobrien * modification, are permitted provided that the following conditions 798944Sobrien * are met: 898944Sobrien * 1. Redistributions of source code must retain the above copyright 998944Sobrien * notice unmodified, this list of conditions, and the following 1098944Sobrien * disclaimer. 1198944Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1298944Sobrien * notice, this list of conditions and the following disclaimer in the 1398944Sobrien * documentation and/or other materials provided with the distribution. 1498944Sobrien * 1598944Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1698944Sobrien * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1798944Sobrien * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1898944Sobrien * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1998944Sobrien * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2098944Sobrien * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2198944Sobrien * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2298944Sobrien * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2398944Sobrien * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2498944Sobrien * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2598944Sobrien * 2698944Sobrien * $FreeBSD: head/sys/dev/pci/pcivar.h 88375 2001-12-21 21:49:57Z tmm $ 2798944Sobrien * 2898944Sobrien */ 2998944Sobrien 3098944Sobrien#ifndef _PCIVAR_H_ 3198944Sobrien#define _PCIVAR_H_ 3298944Sobrien 3398944Sobrien#include <sys/queue.h> 3498944Sobrien 3598944Sobrien/* some PCI bus constants */ 3698944Sobrien 3798944Sobrien#define PCI_BUSMAX 255 /* highest supported bus number */ 3898944Sobrien#define PCI_SLOTMAX 31 /* highest supported slot number */ 3998944Sobrien#define PCI_FUNCMAX 7 /* highest supported function number */ 4098944Sobrien#define PCI_REGMAX 255 /* highest supported config register addr. */ 4198944Sobrien 4298944Sobrien#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4398944Sobrien#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4498944Sobrien#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 4598944Sobrien 4698944Sobrien/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 4798944Sobrien 4898944Sobrien#ifdef PCI_A64 4998944Sobrientypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5098944Sobrien#else 5198944Sobrientypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5298944Sobrien#endif 5398944Sobrien 5498944Sobrien/* config header information common to all header types */ 5598944Sobrien 5698944Sobrientypedef struct pcicfg { 5798944Sobrien struct device *dev; /* device which owns this */ 5898944Sobrien 5998944Sobrien u_int16_t subvendor; /* card vendor ID */ 6098944Sobrien u_int16_t subdevice; /* card device ID, assigned by card vendor */ 6198944Sobrien u_int16_t vendor; /* chip vendor ID */ 6298944Sobrien u_int16_t device; /* chip device ID, assigned by chip vendor */ 6398944Sobrien 6498944Sobrien u_int16_t cmdreg; /* disable/enable chip and PCI options */ 6598944Sobrien u_int16_t statreg; /* supported PCI features and error state */ 6698944Sobrien 6798944Sobrien u_int8_t baseclass; /* chip PCI class */ 6898944Sobrien u_int8_t subclass; /* chip PCI subclass */ 6998944Sobrien u_int8_t progif; /* chip PCI programming interface */ 7098944Sobrien u_int8_t revid; /* chip revision ID */ 7198944Sobrien 7298944Sobrien u_int8_t hdrtype; /* chip config header type */ 7398944Sobrien u_int8_t cachelnsz; /* cache line size in 4byte units */ 7498944Sobrien u_int8_t intpin; /* PCI interrupt pin */ 7598944Sobrien u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 7698944Sobrien 7798944Sobrien u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 7898944Sobrien u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 7998944Sobrien u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 8098944Sobrien 8198944Sobrien u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 8298944Sobrien u_int8_t nummaps; /* actual number of PCI maps used */ 8398944Sobrien 8498944Sobrien u_int8_t bus; /* config space bus address */ 8598944Sobrien u_int8_t slot; /* config space slot address */ 8698944Sobrien u_int8_t func; /* config space function number */ 8798944Sobrien 8898944Sobrien u_int16_t pp_cap; /* PCI power management capabilities */ 8998944Sobrien u_int8_t pp_status; /* config space address of PCI power status reg */ 9098944Sobrien u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 9198944Sobrien u_int8_t pp_data; /* config space address of PCI power data reg */ 9298944Sobrien 9398944Sobrien} pcicfgregs; 9498944Sobrien 9598944Sobrien/* additional type 1 device config header information (PCI to PCI bridge) */ 9698944Sobrien 9798944Sobrien#ifdef PCI_A64 9898944Sobrien#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 9998944Sobrien#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 10098944Sobrien#else 10198944Sobrien#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 10298944Sobrien#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 10398944Sobrien#endif /* PCI_A64 */ 10498944Sobrien 10598944Sobrien#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 10698944Sobrien#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 10798944Sobrien 10898944Sobrientypedef struct { 10998944Sobrien pci_addr_t pmembase; /* base address of prefetchable memory */ 11098944Sobrien pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 11198944Sobrien u_int32_t membase; /* base address of memory window */ 11298944Sobrien u_int32_t memlimit; /* topmost address of memory window */ 11398944Sobrien u_int32_t iobase; /* base address of port window */ 11498944Sobrien u_int32_t iolimit; /* topmost address of port window */ 11598944Sobrien u_int16_t secstat; /* secondary bus status register */ 11698944Sobrien u_int16_t bridgectl; /* bridge control register */ 11798944Sobrien u_int8_t seclat; /* CardBus latency timer */ 11898944Sobrien} pcih1cfgregs; 11998944Sobrien 12098944Sobrien/* additional type 2 device config header information (CardBus bridge) */ 12198944Sobrien 12298944Sobrientypedef struct { 12398944Sobrien u_int32_t membase0; /* base address of memory window */ 12498944Sobrien u_int32_t memlimit0; /* topmost address of memory window */ 12598944Sobrien u_int32_t membase1; /* base address of memory window */ 12698944Sobrien u_int32_t memlimit1; /* topmost address of memory window */ 12798944Sobrien u_int32_t iobase0; /* base address of port window */ 12898944Sobrien u_int32_t iolimit0; /* topmost address of port window */ 12998944Sobrien u_int32_t iobase1; /* base address of port window */ 13098944Sobrien u_int32_t iolimit1; /* topmost address of port window */ 13198944Sobrien u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 13298944Sobrien u_int16_t secstat; /* secondary bus status register */ 133 u_int16_t bridgectl; /* bridge control register */ 134 u_int8_t seclat; /* CardBus latency timer */ 135} pcih2cfgregs; 136 137extern u_int32_t pci_numdevs; 138 139/* Only if the prerequisites are present */ 140#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 141struct pci_devinfo { 142 STAILQ_ENTRY(pci_devinfo) pci_links; 143 struct resource_list resources; 144 pcicfgregs cfg; 145 struct pci_conf conf; 146}; 147#endif 148 149#ifdef __alpha__ 150vm_offset_t pci_cvt_to_dense (vm_offset_t); 151vm_offset_t pci_cvt_to_bwx (vm_offset_t); 152#endif /* __alpha__ */ 153 154#ifdef _SYS_BUS_H_ 155 156#include "pci_if.h" 157 158/* 159 * Define pci-specific resource flags for accessing memory via dense 160 * or bwx memory spaces. These flags are ignored on i386. 161 */ 162#define PCI_RF_DENSE 0x10000 163#define PCI_RF_BWX 0x20000 164 165enum pci_device_ivars { 166 PCI_IVAR_SUBVENDOR, 167 PCI_IVAR_SUBDEVICE, 168 PCI_IVAR_VENDOR, 169 PCI_IVAR_DEVICE, 170 PCI_IVAR_DEVID, 171 PCI_IVAR_CLASS, 172 PCI_IVAR_SUBCLASS, 173 PCI_IVAR_PROGIF, 174 PCI_IVAR_REVID, 175 PCI_IVAR_INTPIN, 176 PCI_IVAR_IRQ, 177 PCI_IVAR_BUS, 178 PCI_IVAR_SLOT, 179 PCI_IVAR_FUNCTION, 180}; 181 182/* 183 * Simplified accessors for pci devices 184 */ 185#define PCI_ACCESSOR(var, ivar, type) \ 186 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 187 188PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 189PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 190PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 191PCI_ACCESSOR(device, DEVICE, u_int16_t) 192PCI_ACCESSOR(devid, DEVID, u_int32_t) 193PCI_ACCESSOR(class, CLASS, u_int8_t) 194PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 195PCI_ACCESSOR(progif, PROGIF, u_int8_t) 196PCI_ACCESSOR(revid, REVID, u_int8_t) 197PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 198PCI_ACCESSOR(irq, IRQ, u_int8_t) 199PCI_ACCESSOR(bus, BUS, u_int8_t) 200PCI_ACCESSOR(slot, SLOT, u_int8_t) 201PCI_ACCESSOR(function, FUNCTION, u_int8_t) 202 203#undef PCI_ACCESSOR 204 205/* 206 * Operations on configuration space. 207 */ 208static __inline u_int32_t 209pci_read_config(device_t dev, int reg, int width) 210{ 211 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 212} 213 214static __inline void 215pci_write_config(device_t dev, int reg, u_int32_t val, int width) 216{ 217 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 218} 219 220/* 221 * Ivars for pci bridges. 222 */ 223 224/*typedef enum pci_device_ivars pcib_device_ivars;*/ 225enum pcib_device_ivars { 226 PCIB_IVAR_BUS 227}; 228 229#define PCIB_ACCESSOR(A, B, T) \ 230 \ 231static __inline T pcib_get_ ## A(device_t dev) \ 232{ \ 233 uintptr_t v; \ 234 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 235 return (T) v; \ 236} \ 237 \ 238static __inline void pcib_set_ ## A(device_t dev, T t) \ 239{ \ 240 uintptr_t v = (uintptr_t) t; \ 241 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 242} 243 244PCIB_ACCESSOR(bus, BUS, u_int32_t) 245 246#undef PCIB_ACCESSOR 247 248/* 249 * Convenience functions. 250 * 251 * These should be used in preference to manually manipulating 252 * configuration space. 253 */ 254static __inline void 255pci_enable_busmaster(device_t dev) 256{ 257 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 258} 259 260static __inline void 261pci_disable_busmaster(device_t dev) 262{ 263 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 264} 265 266static __inline void 267pci_enable_io(device_t dev, int space) 268{ 269 PCI_ENABLE_IO(device_get_parent(dev), dev, space); 270} 271 272static __inline void 273pci_disable_io(device_t dev, int space) 274{ 275 PCI_DISABLE_IO(device_get_parent(dev), dev, space); 276} 277 278/* 279 * PCI power states are as defined by ACPI: 280 * 281 * D0 State in which device is on and running. It is receiving full 282 * power from the system and delivering full functionality to the user. 283 * D1 Class-specific low-power state in which device context may or may not 284 * be lost. Buses in D1 cannot do anything to the bus that would force 285 * devices on that bus to loose context. 286 * D2 Class-specific low-power state in which device context may or may 287 * not be lost. Attains greater power savings than D1. Buses in D2 288 * can cause devices on that bus to loose some context. Devices in D2 289 * must be prepared for the bus to be in D2 or higher. 290 * D3 State in which the device is off and not running. Device context is 291 * lost. Power can be removed from the device. 292 */ 293#define PCI_POWERSTATE_D0 0 294#define PCI_POWERSTATE_D1 1 295#define PCI_POWERSTATE_D2 2 296#define PCI_POWERSTATE_D3 3 297#define PCI_POWERSTATE_UNKNOWN -1 298 299static __inline int 300pci_set_powerstate(device_t dev, int state) 301{ 302 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 303} 304 305static __inline int 306pci_get_powerstate(device_t dev) 307{ 308 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 309} 310 311#endif /* _SYS_BUS_H_ */ 312 313/* 314 * cdev switch for control device, initialised in generic PCI code 315 */ 316extern struct cdevsw pcicdev; 317 318/* 319 * List of all PCI devices, generation count for the list. 320 */ 321STAILQ_HEAD(devlist, pci_devinfo); 322 323extern struct devlist pci_devq; 324extern u_int32_t pci_generation; 325 326#endif /* _PCIVAR_H_ */ 327