pcivar.h revision 61451
1254721Semaste/* 2254721Semaste * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3254721Semaste * All rights reserved. 4254721Semaste * 5254721Semaste * Redistribution and use in source and binary forms, with or without 6254721Semaste * modification, are permitted provided that the following conditions 7254721Semaste * are met: 8254721Semaste * 1. Redistributions of source code must retain the above copyright 9254721Semaste * notice unmodified, this list of conditions, and the following 10254721Semaste * disclaimer. 11254721Semaste * 2. Redistributions in binary form must reproduce the above copyright 12254721Semaste * notice, this list of conditions and the following disclaimer in the 13254721Semaste * documentation and/or other materials provided with the distribution. 14254721Semaste * 15254721Semaste * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16254721Semaste * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17254721Semaste * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18254721Semaste * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19254721Semaste * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20254721Semaste * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21254721Semaste * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22254721Semaste * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23254721Semaste * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24254721Semaste * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25254721Semaste * 26254721Semaste * $FreeBSD: head/sys/dev/pci/pcivar.h 61451 2000-06-09 16:00:29Z dfr $ 27254721Semaste * 28254721Semaste */ 29254721Semaste 30254721Semaste#ifndef _PCIVAR_H_ 31254721Semaste#define _PCIVAR_H_ 32254721Semaste 33254721Semaste#include <sys/queue.h> 34254721Semaste 35254721Semaste/* some PCI bus constants */ 36254721Semaste 37254721Semaste#define PCI_BUSMAX 255 /* highest supported bus number */ 38254721Semaste#define PCI_SLOTMAX 31 /* highest supported slot number */ 39254721Semaste#define PCI_FUNCMAX 7 /* highest supported function number */ 40254721Semaste#define PCI_REGMAX 255 /* highest supported config register addr. */ 41254721Semaste 42254721Semaste#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43254721Semaste#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44254721Semaste#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45254721Semaste 46254721Semaste/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47254721Semaste 48254721Semaste#ifdef PCI_A64 49254721Semastetypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 50254721Semaste#else 51254721Semastetypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 52254721Semaste#endif 53254721Semaste 54254721Semaste/* config header information common to all header types */ 55254721Semaste 56254721Semastetypedef struct pcicfg { 57254721Semaste struct device *dev; /* device which owns this */ 58254721Semaste void *hdrspec; /* pointer to header type specific data */ 59254721Semaste 60254721Semaste u_int16_t subvendor; /* card vendor ID */ 61254721Semaste u_int16_t subdevice; /* card device ID, assigned by card vendor */ 62254721Semaste u_int16_t vendor; /* chip vendor ID */ 63254721Semaste u_int16_t device; /* chip device ID, assigned by chip vendor */ 64254721Semaste 65254721Semaste u_int16_t cmdreg; /* disable/enable chip and PCI options */ 66254721Semaste u_int16_t statreg; /* supported PCI features and error state */ 67254721Semaste 68254721Semaste u_int8_t baseclass; /* chip PCI class */ 69254721Semaste u_int8_t subclass; /* chip PCI subclass */ 70254721Semaste u_int8_t progif; /* chip PCI programming interface */ 71254721Semaste u_int8_t revid; /* chip revision ID */ 72254721Semaste 73254721Semaste u_int8_t hdrtype; /* chip config header type */ 74254721Semaste u_int8_t cachelnsz; /* cache line size in 4byte units */ 75254721Semaste u_int8_t intpin; /* PCI interrupt pin */ 76254721Semaste u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 77254721Semaste 78254721Semaste u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 79254721Semaste u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 80254721Semaste u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 81254721Semaste 82254721Semaste u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 83254721Semaste u_int8_t nummaps; /* actual number of PCI maps used */ 84254721Semaste 85254721Semaste u_int8_t hose; /* hose which bus is attached to */ 86254721Semaste u_int8_t bus; /* config space bus address */ 87254721Semaste u_int8_t slot; /* config space slot address */ 88254721Semaste u_int8_t func; /* config space function number */ 89254721Semaste 90254721Semaste u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 91254721Semaste u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 92254721Semaste} pcicfgregs; 93254721Semaste 94254721Semaste/* additional type 1 device config header information (PCI to PCI bridge) */ 95254721Semaste 96254721Semaste#ifdef PCI_A64 97254721Semaste#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 98254721Semaste#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 99254721Semaste#else 100254721Semaste#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 101254721Semaste#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 102254721Semaste#endif /* PCI_A64 */ 103254721Semaste 104254721Semaste#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 105254721Semaste#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 106254721Semaste 107254721Semastetypedef struct { 108254721Semaste pci_addr_t pmembase; /* base address of prefetchable memory */ 109254721Semaste pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 110254721Semaste u_int32_t membase; /* base address of memory window */ 111254721Semaste u_int32_t memlimit; /* topmost address of memory window */ 112254721Semaste u_int32_t iobase; /* base address of port window */ 113254721Semaste u_int32_t iolimit; /* topmost address of port window */ 114254721Semaste u_int16_t secstat; /* secondary bus status register */ 115254721Semaste u_int16_t bridgectl; /* bridge control register */ 116254721Semaste u_int8_t seclat; /* CardBus latency timer */ 117254721Semaste} pcih1cfgregs; 118254721Semaste 119254721Semaste/* additional type 2 device config header information (CardBus bridge) */ 120254721Semaste 121254721Semastetypedef struct { 122254721Semaste u_int32_t membase0; /* base address of memory window */ 123254721Semaste u_int32_t memlimit0; /* topmost address of memory window */ 124254721Semaste u_int32_t membase1; /* base address of memory window */ 125254721Semaste u_int32_t memlimit1; /* topmost address of memory window */ 126254721Semaste u_int32_t iobase0; /* base address of port window */ 127254721Semaste u_int32_t iolimit0; /* topmost address of port window */ 128254721Semaste u_int32_t iobase1; /* base address of port window */ 129254721Semaste u_int32_t iolimit1; /* topmost address of port window */ 130254721Semaste u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 131254721Semaste u_int16_t secstat; /* secondary bus status register */ 132254721Semaste u_int16_t bridgectl; /* bridge control register */ 133254721Semaste u_int8_t seclat; /* CardBus latency timer */ 134254721Semaste} pcih2cfgregs; 135254721Semaste 136254721Semasteextern u_int32_t pci_numdevs; 137254721Semaste 138254721Semaste/* Only if the prerequisites are present */ 139254721Semaste#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 140254721Semastestruct pci_devinfo { 141254721Semaste STAILQ_ENTRY(pci_devinfo) pci_links; 142254721Semaste struct resource_list resources; 143254721Semaste pcicfgregs cfg; 144254721Semaste struct pci_conf conf; 145254721Semaste}; 146254721Semaste#endif 147254721Semaste 148254721Semaste/* externally visible functions */ 149254721Semaste 150254721Semasteconst char *pci_ata_match(struct device *dev); 151254721Semasteconst char *pci_usb_match(struct device *dev); 152254721Semasteconst char *pci_vga_match(struct device *dev); 153254721Semasteconst char *pci_chip_match(struct device *dev); 154254721Semaste 155254721Semaste/* low level PCI config register functions provided by pcibus.c */ 156254721Semaste 157254721Semasteint pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 158254721Semastevoid pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 159254721Semaste#ifdef __alpha__ 160254721Semastevm_offset_t pci_cvt_to_dense (vm_offset_t); 161254721Semastevm_offset_t pci_cvt_to_bwx (vm_offset_t); 162254721Semaste#endif /* __alpha__ */ 163254721Semaste 164254721Semaste/* low level devlist operations for the 2.2 compatibility code in pci.c */ 165254721Semastepcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 166254721Semaste 167254721Semaste#ifdef _SYS_BUS_H_ 168254721Semaste 169254721Semaste#include "pci_if.h" 170254721Semaste 171254721Semaste/* 172254721Semaste * Define pci-specific resource flags for accessing memory via dense 173254721Semaste * or bwx memory spaces. These flags are ignored on i386. 174254721Semaste */ 175254721Semaste#define PCI_RF_DENSE 0x10000 176254721Semaste#define PCI_RF_BWX 0x20000 177254721Semaste 178254721Semasteenum pci_device_ivars { 179254721Semaste PCI_IVAR_SUBVENDOR, 180254721Semaste PCI_IVAR_SUBDEVICE, 181254721Semaste PCI_IVAR_VENDOR, 182254721Semaste PCI_IVAR_DEVICE, 183254721Semaste PCI_IVAR_DEVID, 184254721Semaste PCI_IVAR_CLASS, 185254721Semaste PCI_IVAR_SUBCLASS, 186254721Semaste PCI_IVAR_PROGIF, 187254721Semaste PCI_IVAR_REVID, 188254721Semaste PCI_IVAR_INTPIN, 189254721Semaste PCI_IVAR_IRQ, 190254721Semaste PCI_IVAR_BUS, 191254721Semaste PCI_IVAR_SLOT, 192254721Semaste PCI_IVAR_FUNCTION, 193254721Semaste PCI_IVAR_SECONDARYBUS, 194254721Semaste PCI_IVAR_SUBORDINATEBUS, 195254721Semaste PCI_IVAR_HOSE, 196254721Semaste}; 197254721Semaste 198254721Semaste/* 199254721Semaste * Simplified accessors for pci devices 200254721Semaste */ 201254721Semaste#define PCI_ACCESSOR(A, B, T) \ 202254721Semaste \ 203254721Semastestatic __inline T pci_get_ ## A(device_t dev) \ 204254721Semaste{ \ 205254721Semaste uintptr_t v; \ 206254721Semaste BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 207254721Semaste return (T) v; \ 208254721Semaste} \ 209254721Semaste \ 210254721Semastestatic __inline void pci_set_ ## A(device_t dev, T t) \ 211254721Semaste{ \ 212254721Semaste u_long v = (u_long) t; \ 213254721Semaste BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 214254721Semaste} 215254721Semaste 216254721SemastePCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 217254721SemastePCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 218254721SemastePCI_ACCESSOR(vendor, VENDOR, u_int16_t) 219254721SemastePCI_ACCESSOR(device, DEVICE, u_int16_t) 220254721SemastePCI_ACCESSOR(devid, DEVID, u_int32_t) 221254721SemastePCI_ACCESSOR(class, CLASS, u_int8_t) 222254721SemastePCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 223254721SemastePCI_ACCESSOR(progif, PROGIF, u_int8_t) 224254721SemastePCI_ACCESSOR(revid, REVID, u_int8_t) 225254721SemastePCI_ACCESSOR(intpin, INTPIN, u_int8_t) 226254721SemastePCI_ACCESSOR(irq, IRQ, u_int8_t) 227254721SemastePCI_ACCESSOR(bus, BUS, u_int8_t) 228254721SemastePCI_ACCESSOR(slot, SLOT, u_int8_t) 229254721SemastePCI_ACCESSOR(function, FUNCTION, u_int8_t) 230254721SemastePCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 231254721SemastePCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 232254721SemastePCI_ACCESSOR(hose, HOSE, u_int32_t) 233254721Semaste 234254721Semastestatic __inline u_int32_t 235254721Semastepci_read_config(device_t dev, int reg, int width) 236254721Semaste{ 237254721Semaste return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 238254721Semaste} 239254721Semaste 240254721Semastestatic __inline void 241254721Semastepci_write_config(device_t dev, int reg, u_int32_t val, int width) 242254721Semaste{ 243254721Semaste PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 244254721Semaste} 245254721Semaste 246254721Semaste/* 247254721Semaste * Ivars for pci bridges. 248254721Semaste */ 249254721Semaste 250254721Semaste/*typedef enum pci_device_ivars pcib_device_ivars;*/ 251254721Semasteenum pcib_device_ivars { 252254721Semaste PCIB_IVAR_HOSE, 253254721Semaste}; 254254721Semaste 255254721Semaste#define PCIB_ACCESSOR(A, B, T) \ 256254721Semaste \ 257254721Semastestatic __inline T pcib_get_ ## A(device_t dev) \ 258254721Semaste{ \ 259254721Semaste uintptr_t v; \ 260254721Semaste BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 261254721Semaste return (T) v; \ 262254721Semaste} \ 263254721Semaste \ 264254721Semastestatic __inline void pcib_set_ ## A(device_t dev, T t) \ 265254721Semaste{ \ 266254721Semaste u_long v = (u_long) t; \ 267254721Semaste BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 268254721Semaste} 269254721Semaste 270254721SemastePCIB_ACCESSOR(hose, HOSE, u_int32_t) 271254721Semaste 272254721Semaste#endif 273254721Semaste 274254721Semaste/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */ 275254721Semaste 276254721Semaste#if defined(_KERNEL) && !defined(KLD_MODULE) 277254721Semaste#include "opt_compat_oldpci.h" 278254721Semaste#endif 279254721Semaste 280254721Semaste#ifdef COMPAT_OLDPCI 281254721Semaste 282254721Semaste/* all this is going some day */ 283254721Semaste 284254721Semastetypedef pcicfgregs *pcici_t; 285254721Semastetypedef unsigned pcidi_t; 286254721Semastetypedef void pci_inthand_t(void *arg); 287254721Semaste 288254721Semaste#define pci_max_burst_len (3) 289254721Semaste 290254721Semaste/* just copied from old PCI code for now ... */ 291254721Semaste 292254721Semastestruct pci_device { 293254721Semaste char* pd_name; 294254721Semaste const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 295254721Semaste void (*pd_attach) (pcici_t tag, int unit); 296254721Semaste u_long *pd_count; 297254721Semaste int (*pd_shutdown) (int, int); 298254721Semaste}; 299254721Semaste 300254721Semaste#ifdef __i386__ 301254721Semastetypedef u_short pci_port_t; 302254721Semaste#else 303254721Semastetypedef u_int pci_port_t; 304254721Semaste#endif 305254721Semaste 306254721Semasteu_long pci_conf_read (pcici_t tag, u_long reg); 307254721Semastevoid pci_conf_write (pcici_t tag, u_long reg, u_long data); 308254721Semasteint pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 309254721Semasteint pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 310254721Semasteint pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 311254721Semaste intrmask_t *maskptr); 312254721Semasteint pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 313254721Semaste intrmask_t *maskptr, u_int flags); 314254721Semasteint pci_unmap_int (pcici_t tag); 315254721Semaste 316254721Semastepcici_t pci_get_parent_from_tag(pcici_t tag); 317254721Semasteint pci_get_bus_from_tag(pcici_t tag); 318254721Semaste 319254721Semastestruct module; 320254721Semasteint compat_pci_handler (struct module *, int, void *); 321254721Semaste#define COMPAT_PCI_DRIVER(name, pcidata) \ 322254721Semastestatic moduledata_t name##_mod = { \ 323254721Semaste #name, \ 324254721Semaste compat_pci_handler, \ 325254721Semaste &pcidata \ 326254721Semaste}; \ 327254721SemasteDECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 328254721Semaste#endif /* COMPAT_OLDPCI */ 329254721Semaste 330254721Semaste#endif /* _PCIVAR_H_ */ 331254721Semaste