pcivar.h revision 54322
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 54322 1999-12-08 17:44:04Z ken $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#ifndef PCI_COMPAT 34#define PCI_COMPAT 35#endif 36 37#include <sys/queue.h> 38 39/* some PCI bus constants */ 40 41#define PCI_BUSMAX 255 /* highest supported bus number */ 42#define PCI_SLOTMAX 31 /* highest supported slot number */ 43#define PCI_FUNCMAX 7 /* highest supported function number */ 44#define PCI_REGMAX 255 /* highest supported config register addr. */ 45 46#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 47#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 48#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 49 50/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 51 52#ifdef PCI_A64 53typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 54#else 55typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 56#endif 57 58/* config header information common to all header types */ 59 60typedef struct pcicfg { 61 struct device *dev; /* device which owns this */ 62 void *hdrspec; /* pointer to header type specific data */ 63 64 u_int16_t subvendor; /* card vendor ID */ 65 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 66 u_int16_t vendor; /* chip vendor ID */ 67 u_int16_t device; /* chip device ID, assigned by chip vendor */ 68 69 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 70 u_int16_t statreg; /* supported PCI features and error state */ 71 72 u_int8_t baseclass; /* chip PCI class */ 73 u_int8_t subclass; /* chip PCI subclass */ 74 u_int8_t progif; /* chip PCI programming interface */ 75 u_int8_t revid; /* chip revision ID */ 76 77 u_int8_t hdrtype; /* chip config header type */ 78 u_int8_t cachelnsz; /* cache line size in 4byte units */ 79 u_int8_t intpin; /* PCI interrupt pin */ 80 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 81 82 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 83 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 84 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 85 86 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 87 u_int8_t nummaps; /* actual number of PCI maps used */ 88 89 u_int8_t hose; /* hose which bus is attached to */ 90 u_int8_t bus; /* config space bus address */ 91 u_int8_t slot; /* config space slot address */ 92 u_int8_t func; /* config space function number */ 93 94 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 95 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 96} pcicfgregs; 97 98/* additional type 1 device config header information (PCI to PCI bridge) */ 99 100#ifdef PCI_A64 101#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 102#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 103#else 104#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 105#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 106#endif /* PCI_A64 */ 107 108#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 109#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 110 111typedef struct { 112 pci_addr_t pmembase; /* base address of prefetchable memory */ 113 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 114 u_int32_t membase; /* base address of memory window */ 115 u_int32_t memlimit; /* topmost address of memory window */ 116 u_int32_t iobase; /* base address of port window */ 117 u_int32_t iolimit; /* topmost address of port window */ 118 u_int16_t secstat; /* secondary bus status register */ 119 u_int16_t bridgectl; /* bridge control register */ 120 u_int8_t seclat; /* CardBus latency timer */ 121} pcih1cfgregs; 122 123/* additional type 2 device config header information (CardBus bridge) */ 124 125typedef struct { 126 u_int32_t membase0; /* base address of memory window */ 127 u_int32_t memlimit0; /* topmost address of memory window */ 128 u_int32_t membase1; /* base address of memory window */ 129 u_int32_t memlimit1; /* topmost address of memory window */ 130 u_int32_t iobase0; /* base address of port window */ 131 u_int32_t iolimit0; /* topmost address of port window */ 132 u_int32_t iobase1; /* base address of port window */ 133 u_int32_t iolimit1; /* topmost address of port window */ 134 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 135 u_int16_t secstat; /* secondary bus status register */ 136 u_int16_t bridgectl; /* bridge control register */ 137 u_int8_t seclat; /* CardBus latency timer */ 138} pcih2cfgregs; 139 140/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 141 142typedef struct pciattach { 143 int unit; 144 int pcibushigh; 145 struct pciattach *next; 146} pciattach; 147 148extern u_int32_t pci_numdevs; 149 150 151/* externally visible functions */ 152 153const char *ide_pci_match(struct device *dev); 154 155/* low level PCI config register functions provided by pcibus.c */ 156 157int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 158void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 159#ifdef __alpha__ 160vm_offset_t pci_cvt_to_dense (vm_offset_t); 161vm_offset_t pci_cvt_to_bwx (vm_offset_t); 162#endif /* __alpha__ */ 163 164/* low level devlist operations for the 2.2 compatibility code in pci.c */ 165pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 166 167#ifdef _SYS_BUS_H_ 168 169#include "pci_if.h" 170 171/* 172 * Define pci-specific resource flags for accessing memory via dense 173 * or bwx memory spaces. These flags are ignored on i386. 174 */ 175#define PCI_RF_DENSE 0x10000 176#define PCI_RF_BWX 0x20000 177 178enum pci_device_ivars { 179 PCI_IVAR_SUBVENDOR, 180 PCI_IVAR_SUBDEVICE, 181 PCI_IVAR_VENDOR, 182 PCI_IVAR_DEVICE, 183 PCI_IVAR_DEVID, 184 PCI_IVAR_CLASS, 185 PCI_IVAR_SUBCLASS, 186 PCI_IVAR_PROGIF, 187 PCI_IVAR_REVID, 188 PCI_IVAR_INTPIN, 189 PCI_IVAR_IRQ, 190 PCI_IVAR_BUS, 191 PCI_IVAR_SLOT, 192 PCI_IVAR_FUNCTION, 193 PCI_IVAR_SECONDARYBUS, 194 PCI_IVAR_SUBORDINATEBUS, 195 PCI_IVAR_HOSE, 196}; 197 198/* 199 * Simplified accessors for pci devices 200 */ 201#define PCI_ACCESSOR(A, B, T) \ 202 \ 203static __inline T pci_get_ ## A(device_t dev) \ 204{ \ 205 uintptr_t v; \ 206 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 207 return (T) v; \ 208} \ 209 \ 210static __inline void pci_set_ ## A(device_t dev, T t) \ 211{ \ 212 u_long v = (u_long) t; \ 213 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 214} 215 216PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 217PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 218PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 219PCI_ACCESSOR(device, DEVICE, u_int16_t) 220PCI_ACCESSOR(devid, DEVID, u_int32_t) 221PCI_ACCESSOR(class, CLASS, u_int8_t) 222PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 223PCI_ACCESSOR(progif, PROGIF, u_int8_t) 224PCI_ACCESSOR(revid, REVID, u_int8_t) 225PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 226PCI_ACCESSOR(irq, IRQ, u_int8_t) 227PCI_ACCESSOR(bus, BUS, u_int8_t) 228PCI_ACCESSOR(slot, SLOT, u_int8_t) 229PCI_ACCESSOR(function, FUNCTION, u_int8_t) 230PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 231PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 232PCI_ACCESSOR(hose, HOSE, u_int32_t) 233 234static __inline u_int32_t 235pci_read_config(device_t dev, int reg, int width) 236{ 237 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 238} 239 240static __inline void 241pci_write_config(device_t dev, int reg, u_int32_t val, int width) 242{ 243 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 244} 245 246/* 247 * Ivars for pci bridges. 248 */ 249 250/*typedef enum pci_device_ivars pcib_device_ivars;*/ 251enum pcib_device_ivars { 252 PCIB_IVAR_HOSE, 253}; 254 255#define PCIB_ACCESSOR(A, B, T) \ 256 \ 257static __inline T pcib_get_ ## A(device_t dev) \ 258{ \ 259 uintptr_t v; \ 260 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 261 return (T) v; \ 262} \ 263 \ 264static __inline void pcib_set_ ## A(device_t dev, T t) \ 265{ \ 266 u_long v = (u_long) t; \ 267 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 268} 269 270PCIB_ACCESSOR(hose, HOSE, u_int32_t) 271 272#endif 273 274/* for compatibility to FreeBSD-2.2 version of PCI code */ 275 276#ifdef PCI_COMPAT 277 278typedef pcicfgregs *pcici_t; 279typedef unsigned pcidi_t; 280typedef void pci_inthand_t(void *arg); 281 282#define pci_max_burst_len (3) 283 284/* just copied from old PCI code for now ... */ 285 286extern int pci_mechanism; 287 288struct pci_device { 289 char* pd_name; 290 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 291 void (*pd_attach) (pcici_t tag, int unit); 292 u_long *pd_count; 293 int (*pd_shutdown) (int, int); 294}; 295 296#ifdef __i386__ 297typedef u_short pci_port_t; 298#else 299typedef u_int pci_port_t; 300#endif 301 302u_long pci_conf_read (pcici_t tag, u_long reg); 303void pci_conf_write (pcici_t tag, u_long reg, u_long data); 304int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 305int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 306int pci_map_dense (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 307int pci_map_bwx (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 308int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 309 intrmask_t *maskptr); 310int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 311 intrmask_t *maskptr, u_int flags); 312int pci_unmap_int (pcici_t tag); 313 314pcici_t pci_get_parent_from_tag(pcici_t tag); 315int pci_get_bus_from_tag(pcici_t tag); 316 317struct module; 318int compat_pci_handler (struct module *, int, void *); 319#define COMPAT_PCI_DRIVER(name, pcidata) \ 320static moduledata_t name##_mod = { \ 321 #name, \ 322 compat_pci_handler, \ 323 &pcidata \ 324}; \ 325DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 326 327 328#endif /* PCI_COMPAT */ 329#endif /* _PCIVAR_H_ */ 330