pcivar.h revision 46831
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $Id: pcivar.h,v 1.29 1999/05/06 22:05:39 peter Exp $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#ifndef PCI_COMPAT 34#define PCI_COMPAT 35#endif 36 37#include <pci/pci_ioctl.h> /* XXX KDM */ 38#include <sys/queue.h> 39 40/* some PCI bus constants */ 41 42#define PCI_BUSMAX 255 /* highest supported bus number */ 43#define PCI_SLOTMAX 31 /* highest supported slot number */ 44#define PCI_FUNCMAX 7 /* highest supported function number */ 45#define PCI_REGMAX 255 /* highest supported config register addr. */ 46 47#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 48#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 49#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 50 51/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 52 53#ifdef PCI_A64 54typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 55#else 56typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 57#endif 58 59/* map register information */ 60 61typedef struct { 62 u_int32_t base; 63 u_int8_t type; 64#define PCI_MAPMEM 0x01 /* memory map */ 65#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 66#define PCI_MAPPORT 0x04 /* port map */ 67 u_int8_t ln2size; 68 u_int8_t ln2range; 69 u_int8_t reg; /* offset of map register in config space */ 70/* u_int8_t dummy;*/ 71 struct resource *res; /* handle from resource manager */ 72} pcimap; 73 74/* config header information common to all header types */ 75 76typedef struct pcicfg { 77 struct device *dev; /* device which owns this */ 78 pcimap *map; /* pointer to array of PCI maps */ 79 void *hdrspec; /* pointer to header type specific data */ 80 struct resource *irqres; /* resource descriptor for interrupt mapping */ 81 82 u_int16_t subvendor; /* card vendor ID */ 83 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 84 u_int16_t vendor; /* chip vendor ID */ 85 u_int16_t device; /* chip device ID, assigned by chip vendor */ 86 87 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 88 u_int16_t statreg; /* supported PCI features and error state */ 89 90 u_int8_t baseclass; /* chip PCI class */ 91 u_int8_t subclass; /* chip PCI subclass */ 92 u_int8_t progif; /* chip PCI programming interface */ 93 u_int8_t revid; /* chip revision ID */ 94 95 u_int8_t hdrtype; /* chip config header type */ 96 u_int8_t cachelnsz; /* cache line size in 4byte units */ 97 u_int8_t intpin; /* PCI interrupt pin */ 98 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 99 100 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 101 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 102 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 103 104 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 105 u_int8_t nummaps; /* actual number of PCI maps used */ 106 107 u_int8_t bus; /* config space bus address */ 108 u_int8_t slot; /* config space slot address */ 109 u_int8_t func; /* config space function number */ 110 111 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 112 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 113} pcicfgregs; 114 115/* additional type 1 device config header information (PCI to PCI bridge) */ 116 117#ifdef PCI_A64 118#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 119#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 120#else 121#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 122#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 123#endif /* PCI_A64 */ 124 125#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 126#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 127 128typedef struct { 129 pci_addr_t pmembase; /* base address of prefetchable memory */ 130 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 131 u_int32_t membase; /* base address of memory window */ 132 u_int32_t memlimit; /* topmost address of memory window */ 133 u_int32_t iobase; /* base address of port window */ 134 u_int32_t iolimit; /* topmost address of port window */ 135 u_int16_t secstat; /* secondary bus status register */ 136 u_int16_t bridgectl; /* bridge control register */ 137 u_int8_t seclat; /* CardBus latency timer */ 138} pcih1cfgregs; 139 140/* additional type 2 device config header information (CardBus bridge) */ 141 142typedef struct { 143 u_int32_t membase0; /* base address of memory window */ 144 u_int32_t memlimit0; /* topmost address of memory window */ 145 u_int32_t membase1; /* base address of memory window */ 146 u_int32_t memlimit1; /* topmost address of memory window */ 147 u_int32_t iobase0; /* base address of port window */ 148 u_int32_t iolimit0; /* topmost address of port window */ 149 u_int32_t iobase1; /* base address of port window */ 150 u_int32_t iolimit1; /* topmost address of port window */ 151 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 152 u_int16_t secstat; /* secondary bus status register */ 153 u_int16_t bridgectl; /* bridge control register */ 154 u_int8_t seclat; /* CardBus latency timer */ 155} pcih2cfgregs; 156 157/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 158 159typedef struct pciattach { 160 int unit; 161 int pcibushigh; 162 struct pciattach *next; 163} pciattach; 164 165struct pci_devinfo { 166 STAILQ_ENTRY(pci_devinfo) pci_links; 167 pcicfgregs cfg; 168 struct pci_conf conf; 169}; 170 171extern u_int32_t pci_numdevs; 172 173 174/* externally visible functions */ 175 176int pci_probe (pciattach *attach); 177void pci_drvattach(struct pci_devinfo *dinfo); 178 179/* low level PCI config register functions provided by pcibus.c */ 180 181int pci_cfgopen (void); 182int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 183void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 184#ifdef __alpha__ 185vm_offset_t pci_cvt_to_dense (vm_offset_t); 186vm_offset_t pci_cvt_to_bwx (vm_offset_t); 187#endif /* __alpha__ */ 188 189#ifdef _SYS_BUS_H_ 190 191#include "pci_if.h" 192 193enum pci_device_ivars { 194 PCI_IVAR_SUBVENDOR, 195 PCI_IVAR_SUBDEVICE, 196 PCI_IVAR_VENDOR, 197 PCI_IVAR_DEVICE, 198 PCI_IVAR_DEVID, 199 PCI_IVAR_CLASS, 200 PCI_IVAR_SUBCLASS, 201 PCI_IVAR_PROGIF, 202 PCI_IVAR_REVID, 203 PCI_IVAR_INTPIN, 204 PCI_IVAR_IRQ, 205 PCI_IVAR_BUS, 206 PCI_IVAR_SLOT, 207 PCI_IVAR_FUNCTION, 208 PCI_IVAR_SECONDARYBUS, 209 PCI_IVAR_SUBORDINATEBUS, 210}; 211 212/* 213 * Simplified accessors for pci devices 214 */ 215#define PCI_ACCESSOR(A, B, T) \ 216 \ 217static __inline T pci_get_ ## A(device_t dev) \ 218{ \ 219 uintptr_t v; \ 220 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 221 return (T) v; \ 222} \ 223 \ 224static __inline void pci_set_ ## A(device_t dev, T t) \ 225{ \ 226 u_long v = (u_long) t; \ 227 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 228} 229 230PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 231PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 232PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 233PCI_ACCESSOR(device, DEVICE, u_int16_t) 234PCI_ACCESSOR(devid, DEVID, u_int32_t) 235PCI_ACCESSOR(class, CLASS, u_int8_t) 236PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 237PCI_ACCESSOR(progif, PROGIF, u_int8_t) 238PCI_ACCESSOR(revid, REVID, u_int8_t) 239PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 240PCI_ACCESSOR(irq, IRQ, u_int8_t) 241PCI_ACCESSOR(bus, BUS, u_int8_t) 242PCI_ACCESSOR(slot, SLOT, u_int8_t) 243PCI_ACCESSOR(function, FUNCTION, u_int8_t) 244PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 245PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 246 247static __inline u_int32_t 248pci_read_config(device_t dev, int reg, int width) 249{ 250 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 251} 252 253static __inline void 254pci_write_config(device_t dev, int reg, u_int32_t val, int width) 255{ 256 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 257} 258 259#endif 260 261/* for compatibility to FreeBSD-2.2 version of PCI code */ 262 263#ifdef PCI_COMPAT 264 265typedef pcicfgregs *pcici_t; 266typedef unsigned pcidi_t; 267typedef void pci_inthand_t(void *arg); 268 269#define pci_max_burst_len (3) 270 271/* just copied from old PCI code for now ... */ 272 273extern int pci_mechanism; 274 275struct pci_device { 276 char* pd_name; 277 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 278 void (*pd_attach) (pcici_t tag, int unit); 279 u_long *pd_count; 280 int (*pd_shutdown) (int, int); 281}; 282 283#ifdef __i386__ 284typedef u_short pci_port_t; 285#else 286typedef u_int pci_port_t; 287#endif 288 289u_long pci_conf_read (pcici_t tag, u_long reg); 290void pci_conf_write (pcici_t tag, u_long reg, u_long data); 291int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 292int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 293int pci_map_dense (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 294int pci_map_bwx (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 295int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 296 intrmask_t *maskptr); 297int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 298 intrmask_t *maskptr, u_int flags); 299int pci_unmap_int (pcici_t tag); 300 301struct module; 302int compat_pci_handler (struct module *, int, void *); 303#define COMPAT_PCI_DRIVER(name, pcidata) \ 304static moduledata_t name##_mod = { \ 305 #name, \ 306 compat_pci_handler, \ 307 &pcidata \ 308}; \ 309DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 310 311 312#endif /* PCI_COMPAT */ 313#endif /* _PCIVAR_H_ */ 314