pcivar.h revision 38304
1#ifndef PCI_COMPAT 2#define PCI_COMPAT 3#endif 4/* 5 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $Id: pcivar.h,v 1.19 1998/07/22 08:39:08 dfr Exp $ 30 * 31 */ 32 33/* some PCI bus constants */ 34 35#define PCI_BUSMAX 255 /* highest supported bus number */ 36#define PCI_SLOTMAX 31 /* highest supported slot number */ 37#define PCI_FUNCMAX 7 /* highest supported function number */ 38#define PCI_REGMAX 255 /* highest supported config register addr. */ 39 40#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 41#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 42#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 43 44/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 45 46#ifdef PCI_A64 47typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 48#else 49typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 50#endif 51 52/* map register information */ 53 54typedef struct { 55 u_int32_t base; 56 u_int8_t type; 57#define PCI_MAPMEM 0x01 /* memory map */ 58#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 59#define PCI_MAPPORT 0x04 /* port map */ 60 u_int8_t ln2size; 61 u_int8_t ln2range; 62/* u_int8_t dummy;*/ 63} pcimap; 64 65/* config header information common to all header types */ 66 67typedef struct pcicfg { 68 struct pcicfg *parent; 69 struct pcicfg *next; 70 pcimap *map; /* pointer to array of PCI maps */ 71 void *hdrspec; /* pointer to header type specific data */ 72 73 u_int16_t subvendor; /* card vendor ID */ 74 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 75 u_int16_t vendor; /* chip vendor ID */ 76 u_int16_t device; /* chip device ID, assigned by chip vendor */ 77 78 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 79 u_int16_t statreg; /* supported PCI features and error state */ 80 81 u_int8_t baseclass; /* chip PCI class */ 82 u_int8_t subclass; /* chip PCI subclass */ 83 u_int8_t progif; /* chip PCI programming interface */ 84 u_int8_t revid; /* chip revision ID */ 85 86 u_int8_t hdrtype; /* chip config header type */ 87 u_int8_t cachelnsz; /* cache line size in 4byte units */ 88 u_int8_t intpin; /* PCI interrupt pin */ 89 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 90 91 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 92 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 93 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 94 95 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 96 u_int8_t nummaps; /* actual number of PCI maps used */ 97 98 u_int8_t bus; /* config space bus address */ 99 u_int8_t slot; /* config space slot address */ 100 u_int8_t func; /* config space function number */ 101 102 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 103 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 104} pcicfgregs; 105 106/* additional type 1 device config header information (PCI to PCI bridge) */ 107 108#ifdef PCI_A64 109#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 110#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 111#else 112#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 113#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 114#endif /* PCI_A64 */ 115 116#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 117#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 118 119typedef struct { 120 pci_addr_t pmembase; /* base address of prefetchable memory */ 121 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 122 u_int32_t membase; /* base address of memory window */ 123 u_int32_t memlimit; /* topmost address of memory window */ 124 u_int32_t iobase; /* base address of port window */ 125 u_int32_t iolimit; /* topmost address of port window */ 126 u_int16_t secstat; /* secondary bus status register */ 127 u_int16_t bridgectl; /* bridge control register */ 128 u_int8_t seclat; /* CardBus latency timer */ 129} pcih1cfgregs; 130 131/* additional type 2 device config header information (CardBus bridge) */ 132 133typedef struct { 134 u_int32_t membase0; /* base address of memory window */ 135 u_int32_t memlimit0; /* topmost address of memory window */ 136 u_int32_t membase1; /* base address of memory window */ 137 u_int32_t memlimit1; /* topmost address of memory window */ 138 u_int32_t iobase0; /* base address of port window */ 139 u_int32_t iolimit0; /* topmost address of port window */ 140 u_int32_t iobase1; /* base address of port window */ 141 u_int32_t iolimit1; /* topmost address of port window */ 142 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 143 u_int16_t secstat; /* secondary bus status register */ 144 u_int16_t bridgectl; /* bridge control register */ 145 u_int8_t seclat; /* CardBus latency timer */ 146} pcih2cfgregs; 147 148/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 149 150typedef struct pciattach { 151 int unit; 152 int pcibushigh; 153 struct pciattach *next; 154} pciattach; 155 156/* externally visible functions */ 157 158int pci_probe (pciattach *attach); 159void pci_drvattach(pcicfgregs *cfg); 160 161/* low level PCI config register functions provided by pcibus.c */ 162 163int pci_cfgopen (void); 164int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 165void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 166 167/* for compatibility to FreeBSD-2.2 version of PCI code */ 168 169#ifdef PCI_COMPAT 170 171typedef pcicfgregs *pcici_t; 172typedef unsigned pcidi_t; 173typedef void pci_inthand_t(void *arg); 174 175#define pci_max_burst_len (3) 176 177/* just copied from old PCI code for now ... */ 178 179extern struct linker_set pcidevice_set; 180extern int pci_mechanism; 181 182struct pci_device { 183 char* pd_name; 184 char* (*pd_probe ) (pcici_t tag, pcidi_t type); 185 void (*pd_attach) (pcici_t tag, int unit); 186 u_long *pd_count; 187 int (*pd_shutdown) (int, int); 188}; 189 190struct pci_lkm { 191 struct pci_device *dvp; 192 struct pci_lkm *next; 193}; 194 195#ifdef __i386__ 196typedef u_short pci_port_t; 197#else 198typedef u_int pci_port_t; 199#endif 200 201u_long pci_conf_read (pcici_t tag, u_long reg); 202void pci_conf_write (pcici_t tag, u_long reg, u_long data); 203void pci_configure (void); 204int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 205int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 206int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr); 207int pci_unmap_int (pcici_t tag); 208int pci_register_lkm (struct pci_device *dvp, int if_revision); 209 210#endif /* PCI_COMPAT */ 211