pcivar.h revision 28517
11541Srgrimes#ifndef PCI_COMPAT 21541Srgrimes#define PCI_COMPAT 31541Srgrimes#endif 41541Srgrimes/* 51541Srgrimes * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 61541Srgrimes * All rights reserved. 71541Srgrimes * 81541Srgrimes * Redistribution and use in source and binary forms, with or without 91541Srgrimes * modification, are permitted provided that the following conditions 101541Srgrimes * are met: 111541Srgrimes * 1. Redistributions of source code must retain the above copyright 121541Srgrimes * notice unmodified, this list of conditions, and the following 131541Srgrimes * disclaimer. 141541Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 151541Srgrimes * notice, this list of conditions and the following disclaimer in the 161541Srgrimes * documentation and/or other materials provided with the distribution. 171541Srgrimes * 181541Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 191541Srgrimes * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 201541Srgrimes * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 211541Srgrimes * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 221541Srgrimes * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 231541Srgrimes * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241541Srgrimes * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251541Srgrimes * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261541Srgrimes * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 271541Srgrimes * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281541Srgrimes * 291541Srgrimes * $Id: pcivar.h,v 1.17 1997/08/21 07:05:54 fsmp Exp $ 301541Srgrimes * 311541Srgrimes */ 321541Srgrimes 331541Srgrimes/* some PCI bus constants */ 341541Srgrimes 351541Srgrimes#define PCI_BUSMAX 255 /* highest supported bus number */ 361541Srgrimes#define PCI_SLOTMAX 31 /* highest supported slot number */ 371541Srgrimes#define PCI_FUNCMAX 7 /* highest supported function number */ 381541Srgrimes#define PCI_REGMAX 255 /* highest supported config register addr. */ 3950477Speter 401541Srgrimes#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 411541Srgrimes#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 422165Spaul#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 434825Sbde 442165Spaul/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 451541Srgrimes 4659288Sjlemon#ifdef PCI_A64 4770834Swollmantypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 481541Srgrimes#else 491541Srgrimestypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 501541Srgrimes#endif 511541Srgrimes 521541Srgrimes/* map register information */ 531541Srgrimes 541541Srgrimestypedef struct { 554825Sbde u_int32_t base; 564825Sbde u_int8_t type; 574825Sbde#define PCI_MAPMEM 0x01 /* memory map */ 581541Srgrimes#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 591541Srgrimes#define PCI_MAPPORT 0x04 /* port map */ 601541Srgrimes u_int8_t ln2size; 611541Srgrimes u_int8_t ln2range; 621541Srgrimes/* u_int8_t dummy;*/ 631541Srgrimes} pcimap; 641541Srgrimes 651541Srgrimes/* config header information common to all header types */ 661541Srgrimes 671541Srgrimestypedef struct pcicfg { 681541Srgrimes struct pcicfg *parent; 691541Srgrimes struct pcicfg *next; 701541Srgrimes pcimap *map; /* pointer to array of PCI maps */ 711541Srgrimes void *hdrspec; /* pointer to header type specific data */ 721541Srgrimes 731541Srgrimes u_int16_t subvendor; /* card vendor ID */ 741541Srgrimes u_int16_t subdevice; /* card device ID, assigned by card vendor */ 751541Srgrimes u_int16_t vendor; /* chip vendor ID */ 7622877Sbde u_int16_t device; /* chip device ID, assigned by chip vendor */ 771541Srgrimes 781541Srgrimes u_int16_t cmdreg; /* disable/enable chip and PCI options */ 791541Srgrimes u_int16_t statreg; /* supported PCI features and error state */ 805396Sache 811541Srgrimes u_int8_t class; /* chip PCI class */ 821541Srgrimes u_int8_t subclass; /* chip PCI subclass */ 8341087Struckman u_int8_t progif; /* chip PCI programming interface */ 841541Srgrimes u_int8_t revid; /* chip revision ID */ 851541Srgrimes 861541Srgrimes u_int8_t hdrtype; /* chip config header type */ 871541Srgrimes u_int8_t cachelnsz; /* cache line size in 4byte units */ 881541Srgrimes u_int8_t intpin; /* PCI interrupt pin */ 891541Srgrimes u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 901541Srgrimes 911541Srgrimes u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 921541Srgrimes u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 931541Srgrimes u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 941541Srgrimes 959833Sbde u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 969833Sbde u_int8_t nummaps; /* actual number of PCI maps used */ 9734185Sbde 9834185Sbde u_int8_t bus; /* config space bus address */ 9934185Sbde u_int8_t slot; /* config space slot address */ 10034185Sbde u_int8_t func; /* config space function number */ 10134185Sbde 10234185Sbde u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 10334185Sbde u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 1049833Sbde} pcicfgregs; 10560938Sjake 1061541Srgrimes/* additional type 1 device config header information (PCI to PCI bridge) */ 1071541Srgrimes 1081541Srgrimes#ifdef PCI_A64 1091541Srgrimes#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 1101541Srgrimes#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 1111541Srgrimes#else 1121541Srgrimes#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 1131541Srgrimes#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 1141541Srgrimes#endif /* PCI_A64 */ 1151541Srgrimes 1161541Srgrimes#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 1171541Srgrimes#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1181541Srgrimes 1191541Srgrimestypedef struct { 1201541Srgrimes pci_addr_t pmembase; /* base address of prefetchable memory */ 1217850Sbde pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 1227850Sbde u_int32_t membase; /* base address of memory window */ 1237850Sbde u_int32_t memlimit; /* topmost address of memory window */ 1247850Sbde u_int32_t iobase; /* base address of port window */ 1257850Sbde u_int32_t iolimit; /* topmost address of port window */ 1267850Sbde u_int16_t secstat; /* secondary bus status register */ 1271541Srgrimes u_int16_t bridgectl; /* bridge control register */ 1287850Sbde u_int8_t seclat; /* CardBus latency timer */ 1299543Sjoerg} pcih1cfgregs; 1301541Srgrimes 1319543Sjoerg/* additional type 2 device config header information (CardBus bridge) */ 1321541Srgrimes 13355205Spetertypedef struct { 1341541Srgrimes u_int32_t membase0; /* base address of memory window */ 1351541Srgrimes u_int32_t memlimit0; /* topmost address of memory window */ 1361541Srgrimes u_int32_t membase1; /* base address of memory window */ 1371541Srgrimes u_int32_t memlimit1; /* topmost address of memory window */ 1381541Srgrimes u_int32_t iobase0; /* base address of port window */ 1391541Srgrimes u_int32_t iolimit0; /* topmost address of port window */ 1401541Srgrimes u_int32_t iobase1; /* base address of port window */ 1419790Sbde u_int32_t iolimit1; /* topmost address of port window */ 1421541Srgrimes u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 1431541Srgrimes u_int16_t secstat; /* secondary bus status register */ 1441541Srgrimes u_int16_t bridgectl; /* bridge control register */ 1451541Srgrimes u_int8_t seclat; /* CardBus latency timer */ 1461541Srgrimes} pcih2cfgregs; 1471541Srgrimes 1481541Srgrimes/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 1491541Srgrimes 1509823Sbdetypedef struct pciattach { 1511541Srgrimes int unit; 1529623Sbde int pcibushigh; 1531541Srgrimes struct pciattach *next; 1541541Srgrimes} pciattach; 1551541Srgrimes 1561541Srgrimes/* externally visible functions */ 1571541Srgrimes 1581541Srgrimesint pci_probe (pciattach *attach); 1591541Srgrimesvoid pci_drvattach(pcicfgregs *cfg); 1601541Srgrimes 1611541Srgrimes/* low level PCI config register functions provided by pcibus.c */ 1621541Srgrimes 1639790Sbdeint pci_cfgopen (void); 1649823Sbdeint pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 1659824Sbdevoid pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 1669823Sbde 1679790Sbde/* for compatibility to FreeBSD-2.2 version of PCI code */ 1689824Sbde 1696391Sugen#ifdef PCI_COMPAT 1709832Sbde 1719832Sbdetypedef pcicfgregs *pcici_t; 1729832Sbdetypedef unsigned pcidi_t; 1739832Sbdetypedef void pci_inthand_t(void *arg); 1749832Sbde 1759832Sbde#define pci_max_burst_len (3) 1769832Sbde 1771541Srgrimes/* just copied from old PCI code for now ... */ 1781541Srgrimes 1791541Srgrimesextern struct linker_set pcidevice_set; 1801541Srgrimesextern int pci_mechanism; 1811541Srgrimes 1821541Srgrimesstruct pci_device { 1831541Srgrimes char* pd_name; 1841541Srgrimes char* (*pd_probe ) (pcici_t tag, pcidi_t type); 1851541Srgrimes void (*pd_attach) (pcici_t tag, int unit); 1861541Srgrimes u_long *pd_count; 1871541Srgrimes int (*pd_shutdown) (int, int); 1881541Srgrimes}; 1891541Srgrimes 1901541Srgrimesstruct pci_lkm { 1911541Srgrimes struct pci_device *dvp; 1921541Srgrimes struct pci_lkm *next; 1931541Srgrimes}; 1941541Srgrimes 1951541Srgrimesu_long pci_conf_read (pcici_t tag, u_long reg); 1961541Srgrimesvoid pci_conf_write (pcici_t tag, u_long reg, u_long data); 1971541Srgrimesvoid pci_configure (void); 1981541Srgrimesint pci_map_port (pcici_t tag, u_long reg, u_short* pa); 1991541Srgrimesint pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 2001541Srgrimesint pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr); 2017467Sacheint pci_unmap_int (pcici_t tag); 2021541Srgrimesint pci_register_lkm (struct pci_device *dvp, int if_revision); 2037467Sache 2047467Sache#endif /* PCI_COMPAT */ 2051541Srgrimes