pcivar.h revision 233379
1193326Sed/*- 2193326Sed * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3193326Sed * All rights reserved. 4193326Sed * 5193326Sed * Redistribution and use in source and binary forms, with or without 6193326Sed * modification, are permitted provided that the following conditions 7193326Sed * are met: 8193326Sed * 1. Redistributions of source code must retain the above copyright 9193326Sed * notice unmodified, this list of conditions, and the following 10193326Sed * disclaimer. 11193326Sed * 2. Redistributions in binary form must reproduce the above copyright 12193326Sed * notice, this list of conditions and the following disclaimer in the 13193326Sed * documentation and/or other materials provided with the distribution. 14193326Sed * 15198092Srdivacky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16193326Sed * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17193326Sed * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18193326Sed * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19193326Sed * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20193326Sed * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21193326Sed * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22193326Sed * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23193326Sed * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24193326Sed * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25193326Sed * 26193326Sed * $FreeBSD: stable/9/sys/dev/pci/pcivar.h 233379 2012-03-23 18:03:04Z jhb $ 27193326Sed * 28193326Sed */ 29193326Sed 30193326Sed#ifndef _PCIVAR_H_ 31193326Sed#define _PCIVAR_H_ 32193326Sed 33193326Sed#include <sys/queue.h> 34193326Sed 35193326Sed/* some PCI bus constants */ 36193326Sed#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37193326Sed#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38193326Sed#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39193326Sed 40193326Sedtypedef uint64_t pci_addr_t; 41193326Sed 42193326Sed/* Interesting values for PCI power management */ 43193326Sedstruct pcicfg_pp { 44193326Sed uint16_t pp_cap; /* PCI power management capabilities */ 45193326Sed uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46193326Sed uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47199990Srdivacky uint8_t pp_data; /* conf. space addr. of PM data reg */ 48193326Sed}; 49193326Sed 50193326Sedstruct pci_map { 51193326Sed pci_addr_t pm_value; /* Raw BAR value */ 52198092Srdivacky pci_addr_t pm_size; 53193326Sed uint8_t pm_reg; 54193326Sed STAILQ_ENTRY(pci_map) pm_link; 55193326Sed}; 56198092Srdivacky 57198092Srdivackystruct vpd_readonly { 58193326Sed char keyword[2]; 59198092Srdivacky char *value; 60193326Sed}; 61193326Sed 62193326Sedstruct vpd_write { 63193326Sed char keyword[2]; 64193326Sed char *value; 65198092Srdivacky int start; 66198092Srdivacky int len; 67198092Srdivacky}; 68198092Srdivacky 69193326Sedstruct pcicfg_vpd { 70193326Sed uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 71193326Sed char vpd_cached; 72201361Srdivacky char *vpd_ident; /* string identifier */ 73193326Sed int vpd_rocnt; 74193326Sed struct vpd_readonly *vpd_ros; 75193326Sed int vpd_wcnt; 76193326Sed struct vpd_write *vpd_w; 77198092Srdivacky}; 78193326Sed 79193326Sed/* Interesting values for PCI MSI */ 80193326Sedstruct pcicfg_msi { 81193326Sed uint16_t msi_ctrl; /* Message Control */ 82201361Srdivacky uint8_t msi_location; /* Offset of MSI capability registers. */ 83193326Sed uint8_t msi_msgnum; /* Number of messages */ 84198092Srdivacky int msi_alloc; /* Number of allocated messages. */ 85193326Sed uint64_t msi_addr; /* Contents of address register. */ 86193326Sed uint16_t msi_data; /* Contents of data register. */ 87193326Sed u_int msi_handlers; 88198092Srdivacky}; 89193326Sed 90193326Sed/* Interesting values for PCI MSI-X */ 91193326Sedstruct msix_vector { 92193326Sed uint64_t mv_address; /* Contents of address register. */ 93193326Sed uint32_t mv_data; /* Contents of data register. */ 94198092Srdivacky int mv_irq; 95198092Srdivacky}; 96193326Sed 97193326Sedstruct msix_table_entry { 98193326Sed u_int mte_vector; /* 1-based index into msix_vectors array. */ 99193326Sed u_int mte_handlers; 100193326Sed}; 101193326Sed 102193326Sedstruct pcicfg_msix { 103193326Sed uint16_t msix_ctrl; /* Message Control */ 104193326Sed uint16_t msix_msgnum; /* Number of messages */ 105193326Sed uint8_t msix_location; /* Offset of MSI-X capability registers. */ 106193326Sed uint8_t msix_table_bar; /* BAR containing vector table. */ 107193326Sed uint8_t msix_pba_bar; /* BAR containing PBA. */ 108193326Sed uint32_t msix_table_offset; 109198398Srdivacky uint32_t msix_pba_offset; 110193326Sed int msix_alloc; /* Number of allocated vectors. */ 111193326Sed int msix_table_len; /* Length of virtual table. */ 112193326Sed struct msix_table_entry *msix_table; /* Virtual table. */ 113193326Sed struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 114198092Srdivacky struct resource *msix_table_res; /* Resource containing vector table. */ 115193326Sed struct resource *msix_pba_res; /* Resource containing PBA. */ 116193326Sed}; 117198092Srdivacky 118193326Sed/* Interesting values for HyperTransport */ 119193326Sedstruct pcicfg_ht { 120193326Sed uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 121193326Sed uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 122193326Sed uint16_t ht_msictrl; /* MSI mapping control */ 123193326Sed uint64_t ht_msiaddr; /* MSI mapping base address */ 124193326Sed}; 125193326Sed 126193326Sed/* config header information common to all header types */ 127193326Sedtypedef struct pcicfg { 128193326Sed struct device *dev; /* device which owns this */ 129193326Sed 130193326Sed STAILQ_HEAD(, pci_map) maps; /* BARs */ 131193326Sed 132193326Sed uint16_t subvendor; /* card vendor ID */ 133193326Sed uint16_t subdevice; /* card device ID, assigned by card vendor */ 134193326Sed uint16_t vendor; /* chip vendor ID */ 135193326Sed uint16_t device; /* chip device ID, assigned by chip vendor */ 136193326Sed 137193326Sed uint16_t cmdreg; /* disable/enable chip and PCI options */ 138198893Srdivacky uint16_t statreg; /* supported PCI features and error state */ 139198893Srdivacky 140193326Sed uint8_t baseclass; /* chip PCI class */ 141198092Srdivacky uint8_t subclass; /* chip PCI subclass */ 142193326Sed uint8_t progif; /* chip PCI programming interface */ 143193326Sed uint8_t revid; /* chip revision ID */ 144199990Srdivacky 145199990Srdivacky uint8_t hdrtype; /* chip config header type */ 146199990Srdivacky uint8_t cachelnsz; /* cache line size in 4byte units */ 147199990Srdivacky uint8_t intpin; /* PCI interrupt pin */ 148199990Srdivacky uint8_t intline; /* interrupt line (IRQ for PC arch) */ 149193326Sed 150193326Sed uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 151198092Srdivacky uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 152198092Srdivacky uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 153193326Sed 154198092Srdivacky uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 155198092Srdivacky uint8_t nummaps; /* actual number of PCI maps used */ 156193326Sed 157198092Srdivacky uint32_t domain; /* PCI domain */ 158193326Sed uint8_t bus; /* config space bus address */ 159193326Sed uint8_t slot; /* config space slot address */ 160193326Sed uint8_t func; /* config space function number */ 161193326Sed 162193326Sed struct pcicfg_pp pp; /* Power management */ 163198092Srdivacky struct pcicfg_vpd vpd; /* Vital product data */ 164198092Srdivacky struct pcicfg_msi msi; /* PCI MSI */ 165193326Sed struct pcicfg_msix msix; /* PCI MSI-X */ 166193326Sed struct pcicfg_ht ht; /* HyperTransport */ 167193326Sed} pcicfgregs; 168193326Sed 169193326Sed/* additional type 1 device config header information (PCI to PCI bridge) */ 170193326Sed 171200583Srdivacky#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 172200583Srdivacky#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 173200583Srdivacky#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 174200583Srdivacky#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 175200583Srdivacky 176200583Srdivackytypedef struct { 177193326Sed pci_addr_t pmembase; /* base address of prefetchable memory */ 178193326Sed pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 179199990Srdivacky uint32_t membase; /* base address of memory window */ 180193326Sed uint32_t memlimit; /* topmost address of memory window */ 181193326Sed uint32_t iobase; /* base address of port window */ 182193326Sed uint32_t iolimit; /* topmost address of port window */ 183193326Sed uint16_t secstat; /* secondary bus status register */ 184198092Srdivacky uint16_t bridgectl; /* bridge control register */ 185198398Srdivacky uint8_t seclat; /* CardBus latency timer */ 186198092Srdivacky} pcih1cfgregs; 187193326Sed 188193326Sed/* additional type 2 device config header information (CardBus bridge) */ 189193326Sed 190199990Srdivackytypedef struct { 191193326Sed uint32_t membase0; /* base address of memory window */ 192193326Sed uint32_t memlimit0; /* topmost address of memory window */ 193193326Sed uint32_t membase1; /* base address of memory window */ 194193326Sed uint32_t memlimit1; /* topmost address of memory window */ 195198092Srdivacky uint32_t iobase0; /* base address of port window */ 196193326Sed uint32_t iolimit0; /* topmost address of port window */ 197199990Srdivacky uint32_t iobase1; /* base address of port window */ 198193326Sed uint32_t iolimit1; /* topmost address of port window */ 199193326Sed uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 200193326Sed uint16_t secstat; /* secondary bus status register */ 201193326Sed uint16_t bridgectl; /* bridge control register */ 202198092Srdivacky uint8_t seclat; /* CardBus latency timer */ 203193326Sed} pcih2cfgregs; 204193326Sed 205193326Sedextern uint32_t pci_numdevs; 206193326Sed 207193326Sed/* Only if the prerequisites are present */ 208193326Sed#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 209198092Srdivackystruct pci_devinfo { 210193326Sed STAILQ_ENTRY(pci_devinfo) pci_links; 211202379Srdivacky struct resource_list resources; 212202379Srdivacky pcicfgregs cfg; 213202379Srdivacky struct pci_conf conf; 214202379Srdivacky}; 215193326Sed#endif 216193326Sed 217193326Sed#ifdef _SYS_BUS_H_ 218193326Sed 219193326Sed#include "pci_if.h" 220193326Sed 221193326Sedenum pci_device_ivars { 222193326Sed PCI_IVAR_SUBVENDOR, 223193326Sed PCI_IVAR_SUBDEVICE, 224193326Sed PCI_IVAR_VENDOR, 225193326Sed PCI_IVAR_DEVICE, 226193326Sed PCI_IVAR_DEVID, 227193326Sed PCI_IVAR_CLASS, 228193326Sed PCI_IVAR_SUBCLASS, 229193326Sed PCI_IVAR_PROGIF, 230193326Sed PCI_IVAR_REVID, 231193326Sed PCI_IVAR_INTPIN, 232193326Sed PCI_IVAR_IRQ, 233193326Sed PCI_IVAR_DOMAIN, 234193326Sed PCI_IVAR_BUS, 235193326Sed PCI_IVAR_SLOT, 236193326Sed PCI_IVAR_FUNCTION, 237193326Sed PCI_IVAR_ETHADDR, 238193326Sed PCI_IVAR_CMDREG, 239193326Sed PCI_IVAR_CACHELNSZ, 240193326Sed PCI_IVAR_MINGNT, 241193326Sed PCI_IVAR_MAXLAT, 242193326Sed PCI_IVAR_LATTIMER 243193326Sed}; 244193326Sed 245198092Srdivacky/* 246193326Sed * Simplified accessors for pci devices 247193326Sed */ 248193326Sed#define PCI_ACCESSOR(var, ivar, type) \ 249193326Sed __BUS_ACCESSOR(pci, var, PCI, ivar, type) 250193326Sed 251193326SedPCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 252198092SrdivackyPCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 253198092SrdivackyPCI_ACCESSOR(vendor, VENDOR, uint16_t) 254193326SedPCI_ACCESSOR(device, DEVICE, uint16_t) 255193326SedPCI_ACCESSOR(devid, DEVID, uint32_t) 256193326SedPCI_ACCESSOR(class, CLASS, uint8_t) 257193326SedPCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 258193326SedPCI_ACCESSOR(progif, PROGIF, uint8_t) 259193326SedPCI_ACCESSOR(revid, REVID, uint8_t) 260198092SrdivackyPCI_ACCESSOR(intpin, INTPIN, uint8_t) 261198092SrdivackyPCI_ACCESSOR(irq, IRQ, uint8_t) 262198092SrdivackyPCI_ACCESSOR(domain, DOMAIN, uint32_t) 263198092SrdivackyPCI_ACCESSOR(bus, BUS, uint8_t) 264200583SrdivackyPCI_ACCESSOR(slot, SLOT, uint8_t) 265200583SrdivackyPCI_ACCESSOR(function, FUNCTION, uint8_t) 266200583SrdivackyPCI_ACCESSOR(ether, ETHADDR, uint8_t *) 267200583SrdivackyPCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 268198092SrdivackyPCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 269198092SrdivackyPCI_ACCESSOR(mingnt, MINGNT, uint8_t) 270198092SrdivackyPCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 271198092SrdivackyPCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 272198092Srdivacky 273198092Srdivacky#undef PCI_ACCESSOR 274198092Srdivacky 275198092Srdivacky/* 276198092Srdivacky * Operations on configuration space. 277198092Srdivacky */ 278198092Srdivackystatic __inline uint32_t 279198092Srdivackypci_read_config(device_t dev, int reg, int width) 280198092Srdivacky{ 281198092Srdivacky return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 282198893Srdivacky} 283198893Srdivacky 284198893Srdivackystatic __inline void 285198893Srdivackypci_write_config(device_t dev, int reg, uint32_t val, int width) 286198893Srdivacky{ 287198893Srdivacky PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 288193326Sed} 289193326Sed 290193326Sed/* 291193326Sed * Ivars for pci bridges. 292193326Sed */ 293203955Srdivacky 294194613Sed/*typedef enum pci_device_ivars pcib_device_ivars;*/ 295193326Sedenum pcib_device_ivars { 296193326Sed PCIB_IVAR_DOMAIN, 297193326Sed PCIB_IVAR_BUS 298193326Sed}; 299193326Sed 300193326Sed#define PCIB_ACCESSOR(var, ivar, type) \ 301193326Sed __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 302193326Sed 303193326SedPCIB_ACCESSOR(domain, DOMAIN, uint32_t) 304193326SedPCIB_ACCESSOR(bus, BUS, uint32_t) 305193326Sed 306193326Sed#undef PCIB_ACCESSOR 307193326Sed 308193326Sed/* 309193326Sed * PCI interrupt validation. Invalid interrupt values such as 0 or 128 310193326Sed * on i386 or other platforms should be mapped out in the MD pcireadconf 311193326Sed * code and not here, since the only MI invalid IRQ is 255. 312193326Sed */ 313193326Sed#define PCI_INVALID_IRQ 255 314193326Sed#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 315193326Sed 316193326Sed/* 317193326Sed * Convenience functions. 318193326Sed * 319193326Sed * These should be used in preference to manually manipulating 320193326Sed * configuration space. 321193326Sed */ 322193326Sedstatic __inline int 323193326Sedpci_enable_busmaster(device_t dev) 324193326Sed{ 325193326Sed return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 326193326Sed} 327193326Sed 328201361Srdivackystatic __inline int 329201361Srdivackypci_disable_busmaster(device_t dev) 330201361Srdivacky{ 331201361Srdivacky return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 332201361Srdivacky} 333201361Srdivacky 334201361Srdivackystatic __inline int 335201361Srdivackypci_enable_io(device_t dev, int space) 336201361Srdivacky{ 337201361Srdivacky return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 338193326Sed} 339193326Sed 340193326Sedstatic __inline int 341193326Sedpci_disable_io(device_t dev, int space) 342193326Sed{ 343193326Sed return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 344193326Sed} 345193326Sed 346193326Sedstatic __inline int 347201361Srdivackypci_get_vpd_ident(device_t dev, const char **identptr) 348201361Srdivacky{ 349201361Srdivacky return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 350201361Srdivacky} 351201361Srdivacky 352201361Srdivackystatic __inline int 353193326Sedpci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 354198092Srdivacky{ 355193326Sed return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 356193326Sed} 357193326Sed 358193326Sed/* 359193326Sed * Check if the address range falls within the VGA defined address range(s) 360193326Sed */ 361199482Srdivackystatic __inline int 362199482Srdivackypci_is_vga_ioport_range(u_long start, u_long end) 363199482Srdivacky{ 364193326Sed 365193326Sed return (((start >= 0x3b0 && end <= 0x3bb) || 366193326Sed (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 367193326Sed} 368193326Sed 369193326Sedstatic __inline int 370193326Sedpci_is_vga_memory_range(u_long start, u_long end) 371193326Sed{ 372193326Sed 373193326Sed return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 374193326Sed} 375193326Sed 376193326Sed/* 377193326Sed * PCI power states are as defined by ACPI: 378193326Sed * 379193326Sed * D0 State in which device is on and running. It is receiving full 380193326Sed * power from the system and delivering full functionality to the user. 381193326Sed * D1 Class-specific low-power state in which device context may or may not 382198398Srdivacky * be lost. Buses in D1 cannot do anything to the bus that would force 383198092Srdivacky * devices on that bus to lose context. 384193326Sed * D2 Class-specific low-power state in which device context may or may 385193326Sed * not be lost. Attains greater power savings than D1. Buses in D2 386193326Sed * can cause devices on that bus to lose some context. Devices in D2 387193326Sed * must be prepared for the bus to be in D2 or higher. 388193326Sed * D3 State in which the device is off and not running. Device context is 389198092Srdivacky * lost. Power can be removed from the device. 390198092Srdivacky */ 391198092Srdivacky#define PCI_POWERSTATE_D0 0 392198092Srdivacky#define PCI_POWERSTATE_D1 1 393198092Srdivacky#define PCI_POWERSTATE_D2 2 394198092Srdivacky#define PCI_POWERSTATE_D3 3 395198092Srdivacky#define PCI_POWERSTATE_UNKNOWN -1 396193326Sed 397193326Sedstatic __inline int 398198092Srdivackypci_set_powerstate(device_t dev, int state) 399193326Sed{ 400193326Sed return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 401193326Sed} 402193326Sed 403198092Srdivackystatic __inline int 404198092Srdivackypci_get_powerstate(device_t dev) 405193326Sed{ 406193326Sed return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 407193326Sed} 408193326Sed 409193326Sedstatic __inline int 410193326Sedpci_find_cap(device_t dev, int capability, int *capreg) 411193326Sed{ 412193326Sed return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 413193326Sed} 414198092Srdivacky 415193326Sedstatic __inline int 416193326Sedpci_find_extcap(device_t dev, int capability, int *capreg) 417193326Sed{ 418193326Sed return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 419193326Sed} 420193326Sed 421193326Sedstatic __inline int 422193326Sedpci_alloc_msi(device_t dev, int *count) 423193326Sed{ 424193326Sed return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 425193326Sed} 426193326Sed 427198092Srdivackystatic __inline int 428193326Sedpci_alloc_msix(device_t dev, int *count) 429193326Sed{ 430198092Srdivacky return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 431198092Srdivacky} 432193326Sed 433193326Sedstatic __inline int 434193326Sedpci_remap_msix(device_t dev, int count, const u_int *vectors) 435198092Srdivacky{ 436193326Sed return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 437193326Sed} 438193326Sed 439193326Sedstatic __inline int 440193326Sedpci_release_msi(device_t dev) 441193326Sed{ 442198092Srdivacky return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 443198092Srdivacky} 444198092Srdivacky 445193326Sedstatic __inline int 446193326Sedpci_msi_count(device_t dev) 447193326Sed{ 448193326Sed return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 449198092Srdivacky} 450193326Sed 451193326Sedstatic __inline int 452193326Sedpci_msix_count(device_t dev) 453198092Srdivacky{ 454198092Srdivacky return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 455193326Sed} 456193326Sed 457193326Seddevice_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 458193326Seddevice_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 459193326Seddevice_t pci_find_device(uint16_t, uint16_t); 460193326Seddevice_t pci_find_class(uint8_t class, uint8_t subclass); 461198092Srdivacky 462193326Sed/* Can be used by drivers to manage the MSI-X table. */ 463193326Sedint pci_pending_msix(device_t dev, u_int index); 464193326Sed 465193326Sedint pci_msi_device_blacklisted(device_t dev); 466193326Sed 467198092Srdivackyvoid pci_ht_map_msi(device_t dev, uint64_t addr); 468193326Sed 469198092Srdivackyint pci_get_max_read_req(device_t dev); 470193326Sedvoid pci_restore_state(device_t dev); 471198092Srdivackyvoid pci_save_state(device_t dev); 472193326Sedint pci_set_max_read_req(device_t dev, int size); 473193326Sed 474193326Sed#endif /* _SYS_BUS_H_ */ 475193326Sed 476198092Srdivacky/* 477198092Srdivacky * cdev switch for control device, initialised in generic PCI code 478193326Sed */ 479193326Sedextern struct cdevsw pcicdev; 480193326Sed 481193326Sed/* 482193326Sed * List of all PCI devices, generation count for the list. 483193326Sed */ 484198092SrdivackySTAILQ_HEAD(devlist, pci_devinfo); 485198092Srdivacky 486198092Srdivackyextern struct devlist pci_devq; 487193326Sedextern uint32_t pci_generation; 488193326Sed 489193326Sedstruct pci_map *pci_find_bar(device_t dev, int reg); 490193326Sedint pci_bar_enabled(device_t dev, struct pci_map *pm); 491193326Sed 492193326Sed#endif /* _PCIVAR_H_ */ 493193326Sed