pcivar.h revision 225736
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/9/sys/dev/pci/pcivar.h 223885 2011-07-09 14:30:13Z kib $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40typedef uint64_t pci_addr_t; 41 42/* Interesting values for PCI power management */ 43struct pcicfg_pp { 44 uint16_t pp_cap; /* PCI power management capabilities */ 45 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47 uint8_t pp_data; /* conf. space addr. of PM data reg */ 48}; 49 50struct pci_map { 51 pci_addr_t pm_value; /* Raw BAR value */ 52 pci_addr_t pm_size; 53 uint8_t pm_reg; 54 STAILQ_ENTRY(pci_map) pm_link; 55}; 56 57struct vpd_readonly { 58 char keyword[2]; 59 char *value; 60}; 61 62struct vpd_write { 63 char keyword[2]; 64 char *value; 65 int start; 66 int len; 67}; 68 69struct pcicfg_vpd { 70 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 71 char vpd_cached; 72 char *vpd_ident; /* string identifier */ 73 int vpd_rocnt; 74 struct vpd_readonly *vpd_ros; 75 int vpd_wcnt; 76 struct vpd_write *vpd_w; 77}; 78 79/* Interesting values for PCI MSI */ 80struct pcicfg_msi { 81 uint16_t msi_ctrl; /* Message Control */ 82 uint8_t msi_location; /* Offset of MSI capability registers. */ 83 uint8_t msi_msgnum; /* Number of messages */ 84 int msi_alloc; /* Number of allocated messages. */ 85 uint64_t msi_addr; /* Contents of address register. */ 86 uint16_t msi_data; /* Contents of data register. */ 87 u_int msi_handlers; 88}; 89 90/* Interesting values for PCI MSI-X */ 91struct msix_vector { 92 uint64_t mv_address; /* Contents of address register. */ 93 uint32_t mv_data; /* Contents of data register. */ 94 int mv_irq; 95}; 96 97struct msix_table_entry { 98 u_int mte_vector; /* 1-based index into msix_vectors array. */ 99 u_int mte_handlers; 100}; 101 102struct pcicfg_msix { 103 uint16_t msix_ctrl; /* Message Control */ 104 uint16_t msix_msgnum; /* Number of messages */ 105 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 106 uint8_t msix_table_bar; /* BAR containing vector table. */ 107 uint8_t msix_pba_bar; /* BAR containing PBA. */ 108 uint32_t msix_table_offset; 109 uint32_t msix_pba_offset; 110 int msix_alloc; /* Number of allocated vectors. */ 111 int msix_table_len; /* Length of virtual table. */ 112 struct msix_table_entry *msix_table; /* Virtual table. */ 113 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 114 struct resource *msix_table_res; /* Resource containing vector table. */ 115 struct resource *msix_pba_res; /* Resource containing PBA. */ 116}; 117 118/* Interesting values for HyperTransport */ 119struct pcicfg_ht { 120 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 121 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 122 uint16_t ht_msictrl; /* MSI mapping control */ 123 uint64_t ht_msiaddr; /* MSI mapping base address */ 124}; 125 126/* config header information common to all header types */ 127typedef struct pcicfg { 128 struct device *dev; /* device which owns this */ 129 130 STAILQ_HEAD(, pci_map) maps; /* BARs */ 131 132 uint16_t subvendor; /* card vendor ID */ 133 uint16_t subdevice; /* card device ID, assigned by card vendor */ 134 uint16_t vendor; /* chip vendor ID */ 135 uint16_t device; /* chip device ID, assigned by chip vendor */ 136 137 uint16_t cmdreg; /* disable/enable chip and PCI options */ 138 uint16_t statreg; /* supported PCI features and error state */ 139 140 uint8_t baseclass; /* chip PCI class */ 141 uint8_t subclass; /* chip PCI subclass */ 142 uint8_t progif; /* chip PCI programming interface */ 143 uint8_t revid; /* chip revision ID */ 144 145 uint8_t hdrtype; /* chip config header type */ 146 uint8_t cachelnsz; /* cache line size in 4byte units */ 147 uint8_t intpin; /* PCI interrupt pin */ 148 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 149 150 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 151 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 152 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 153 154 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 155 uint8_t nummaps; /* actual number of PCI maps used */ 156 157 uint32_t domain; /* PCI domain */ 158 uint8_t bus; /* config space bus address */ 159 uint8_t slot; /* config space slot address */ 160 uint8_t func; /* config space function number */ 161 162 struct pcicfg_pp pp; /* Power management */ 163 struct pcicfg_vpd vpd; /* Vital product data */ 164 struct pcicfg_msi msi; /* PCI MSI */ 165 struct pcicfg_msix msix; /* PCI MSI-X */ 166 struct pcicfg_ht ht; /* HyperTransport */ 167} pcicfgregs; 168 169/* additional type 1 device config header information (PCI to PCI bridge) */ 170 171#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 172#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 173#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 174#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 175 176typedef struct { 177 pci_addr_t pmembase; /* base address of prefetchable memory */ 178 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 179 uint32_t membase; /* base address of memory window */ 180 uint32_t memlimit; /* topmost address of memory window */ 181 uint32_t iobase; /* base address of port window */ 182 uint32_t iolimit; /* topmost address of port window */ 183 uint16_t secstat; /* secondary bus status register */ 184 uint16_t bridgectl; /* bridge control register */ 185 uint8_t seclat; /* CardBus latency timer */ 186} pcih1cfgregs; 187 188/* additional type 2 device config header information (CardBus bridge) */ 189 190typedef struct { 191 uint32_t membase0; /* base address of memory window */ 192 uint32_t memlimit0; /* topmost address of memory window */ 193 uint32_t membase1; /* base address of memory window */ 194 uint32_t memlimit1; /* topmost address of memory window */ 195 uint32_t iobase0; /* base address of port window */ 196 uint32_t iolimit0; /* topmost address of port window */ 197 uint32_t iobase1; /* base address of port window */ 198 uint32_t iolimit1; /* topmost address of port window */ 199 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 200 uint16_t secstat; /* secondary bus status register */ 201 uint16_t bridgectl; /* bridge control register */ 202 uint8_t seclat; /* CardBus latency timer */ 203} pcih2cfgregs; 204 205extern uint32_t pci_numdevs; 206 207/* Only if the prerequisites are present */ 208#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 209struct pci_devinfo { 210 STAILQ_ENTRY(pci_devinfo) pci_links; 211 struct resource_list resources; 212 pcicfgregs cfg; 213 struct pci_conf conf; 214}; 215#endif 216 217#ifdef _SYS_BUS_H_ 218 219#include "pci_if.h" 220 221enum pci_device_ivars { 222 PCI_IVAR_SUBVENDOR, 223 PCI_IVAR_SUBDEVICE, 224 PCI_IVAR_VENDOR, 225 PCI_IVAR_DEVICE, 226 PCI_IVAR_DEVID, 227 PCI_IVAR_CLASS, 228 PCI_IVAR_SUBCLASS, 229 PCI_IVAR_PROGIF, 230 PCI_IVAR_REVID, 231 PCI_IVAR_INTPIN, 232 PCI_IVAR_IRQ, 233 PCI_IVAR_DOMAIN, 234 PCI_IVAR_BUS, 235 PCI_IVAR_SLOT, 236 PCI_IVAR_FUNCTION, 237 PCI_IVAR_ETHADDR, 238 PCI_IVAR_CMDREG, 239 PCI_IVAR_CACHELNSZ, 240 PCI_IVAR_MINGNT, 241 PCI_IVAR_MAXLAT, 242 PCI_IVAR_LATTIMER 243}; 244 245/* 246 * Simplified accessors for pci devices 247 */ 248#define PCI_ACCESSOR(var, ivar, type) \ 249 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 250 251PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 252PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 253PCI_ACCESSOR(vendor, VENDOR, uint16_t) 254PCI_ACCESSOR(device, DEVICE, uint16_t) 255PCI_ACCESSOR(devid, DEVID, uint32_t) 256PCI_ACCESSOR(class, CLASS, uint8_t) 257PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 258PCI_ACCESSOR(progif, PROGIF, uint8_t) 259PCI_ACCESSOR(revid, REVID, uint8_t) 260PCI_ACCESSOR(intpin, INTPIN, uint8_t) 261PCI_ACCESSOR(irq, IRQ, uint8_t) 262PCI_ACCESSOR(domain, DOMAIN, uint32_t) 263PCI_ACCESSOR(bus, BUS, uint8_t) 264PCI_ACCESSOR(slot, SLOT, uint8_t) 265PCI_ACCESSOR(function, FUNCTION, uint8_t) 266PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 267PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 268PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 269PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 270PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 271PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 272 273#undef PCI_ACCESSOR 274 275/* 276 * Operations on configuration space. 277 */ 278static __inline uint32_t 279pci_read_config(device_t dev, int reg, int width) 280{ 281 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 282} 283 284static __inline void 285pci_write_config(device_t dev, int reg, uint32_t val, int width) 286{ 287 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 288} 289 290/* 291 * Ivars for pci bridges. 292 */ 293 294/*typedef enum pci_device_ivars pcib_device_ivars;*/ 295enum pcib_device_ivars { 296 PCIB_IVAR_DOMAIN, 297 PCIB_IVAR_BUS 298}; 299 300#define PCIB_ACCESSOR(var, ivar, type) \ 301 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 302 303PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 304PCIB_ACCESSOR(bus, BUS, uint32_t) 305 306#undef PCIB_ACCESSOR 307 308/* 309 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 310 * on i386 or other platforms should be mapped out in the MD pcireadconf 311 * code and not here, since the only MI invalid IRQ is 255. 312 */ 313#define PCI_INVALID_IRQ 255 314#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 315 316/* 317 * Convenience functions. 318 * 319 * These should be used in preference to manually manipulating 320 * configuration space. 321 */ 322static __inline int 323pci_enable_busmaster(device_t dev) 324{ 325 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 326} 327 328static __inline int 329pci_disable_busmaster(device_t dev) 330{ 331 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 332} 333 334static __inline int 335pci_enable_io(device_t dev, int space) 336{ 337 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 338} 339 340static __inline int 341pci_disable_io(device_t dev, int space) 342{ 343 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 344} 345 346static __inline int 347pci_get_vpd_ident(device_t dev, const char **identptr) 348{ 349 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 350} 351 352static __inline int 353pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 354{ 355 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 356} 357 358/* 359 * Check if the address range falls within the VGA defined address range(s) 360 */ 361static __inline int 362pci_is_vga_ioport_range(u_long start, u_long end) 363{ 364 365 return (((start >= 0x3b0 && end <= 0x3bb) || 366 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 367} 368 369static __inline int 370pci_is_vga_memory_range(u_long start, u_long end) 371{ 372 373 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 374} 375 376/* 377 * PCI power states are as defined by ACPI: 378 * 379 * D0 State in which device is on and running. It is receiving full 380 * power from the system and delivering full functionality to the user. 381 * D1 Class-specific low-power state in which device context may or may not 382 * be lost. Buses in D1 cannot do anything to the bus that would force 383 * devices on that bus to lose context. 384 * D2 Class-specific low-power state in which device context may or may 385 * not be lost. Attains greater power savings than D1. Buses in D2 386 * can cause devices on that bus to lose some context. Devices in D2 387 * must be prepared for the bus to be in D2 or higher. 388 * D3 State in which the device is off and not running. Device context is 389 * lost. Power can be removed from the device. 390 */ 391#define PCI_POWERSTATE_D0 0 392#define PCI_POWERSTATE_D1 1 393#define PCI_POWERSTATE_D2 2 394#define PCI_POWERSTATE_D3 3 395#define PCI_POWERSTATE_UNKNOWN -1 396 397static __inline int 398pci_set_powerstate(device_t dev, int state) 399{ 400 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 401} 402 403static __inline int 404pci_get_powerstate(device_t dev) 405{ 406 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 407} 408 409static __inline int 410pci_find_cap(device_t dev, int capability, int *capreg) 411{ 412 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 413} 414 415static __inline int 416pci_find_extcap(device_t dev, int capability, int *capreg) 417{ 418 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 419} 420 421static __inline int 422pci_alloc_msi(device_t dev, int *count) 423{ 424 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 425} 426 427static __inline int 428pci_alloc_msix(device_t dev, int *count) 429{ 430 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 431} 432 433static __inline int 434pci_remap_msix(device_t dev, int count, const u_int *vectors) 435{ 436 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 437} 438 439static __inline int 440pci_release_msi(device_t dev) 441{ 442 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 443} 444 445static __inline int 446pci_msi_count(device_t dev) 447{ 448 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 449} 450 451static __inline int 452pci_msix_count(device_t dev) 453{ 454 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 455} 456 457device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 458device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 459device_t pci_find_device(uint16_t, uint16_t); 460device_t pci_find_class(uint8_t class, uint8_t subclass); 461 462/* Can be used by drivers to manage the MSI-X table. */ 463int pci_pending_msix(device_t dev, u_int index); 464 465int pci_msi_device_blacklisted(device_t dev); 466 467void pci_ht_map_msi(device_t dev, uint64_t addr); 468 469int pci_get_max_read_req(device_t dev); 470int pci_set_max_read_req(device_t dev, int size); 471 472#endif /* _SYS_BUS_H_ */ 473 474/* 475 * cdev switch for control device, initialised in generic PCI code 476 */ 477extern struct cdevsw pcicdev; 478 479/* 480 * List of all PCI devices, generation count for the list. 481 */ 482STAILQ_HEAD(devlist, pci_devinfo); 483 484extern struct devlist pci_devq; 485extern uint32_t pci_generation; 486 487struct pci_map *pci_find_bar(device_t dev, int reg); 488int pci_bar_enabled(device_t dev, struct pci_map *pm); 489 490#endif /* _PCIVAR_H_ */ 491