pcivar.h revision 107300
1227569Sphilip/* 2227569Sphilip * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3227569Sphilip * All rights reserved. 4227569Sphilip * 5227569Sphilip * Redistribution and use in source and binary forms, with or without 6227569Sphilip * modification, are permitted provided that the following conditions 7227569Sphilip * are met: 8255608Skib * 1. Redistributions of source code must retain the above copyright 9227569Sphilip * notice unmodified, this list of conditions, and the following 10227569Sphilip * disclaimer. 11227569Sphilip * 2. Redistributions in binary form must reproduce the above copyright 12227569Sphilip * notice, this list of conditions and the following disclaimer in the 13227569Sphilip * documentation and/or other materials provided with the distribution. 14227569Sphilip * 15227569Sphilip * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16227569Sphilip * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17227569Sphilip * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18227569Sphilip * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19227569Sphilip * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20227569Sphilip * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21227569Sphilip * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22227569Sphilip * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23255936Sphilip * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24227569Sphilip * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25227569Sphilip * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 107300 2002-11-27 06:41:28Z imp $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36 37#define PCI_BUSMAX 255 /* highest supported bus number */ 38#define PCI_SLOTMAX 31 /* highest supported slot number */ 39#define PCI_FUNCMAX 7 /* highest supported function number */ 40#define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48#ifdef PCI_A64 49typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 50#else 51typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 52#endif 53 54/* config header information common to all header types */ 55 56typedef struct pcicfg { 57 struct device *dev; /* device which owns this */ 58 59 u_int16_t subvendor; /* card vendor ID */ 60 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 61 u_int16_t vendor; /* chip vendor ID */ 62 u_int16_t device; /* chip device ID, assigned by chip vendor */ 63 64 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 65 u_int16_t statreg; /* supported PCI features and error state */ 66 67 u_int8_t baseclass; /* chip PCI class */ 68 u_int8_t subclass; /* chip PCI subclass */ 69 u_int8_t progif; /* chip PCI programming interface */ 70 u_int8_t revid; /* chip revision ID */ 71 72 u_int8_t hdrtype; /* chip config header type */ 73 u_int8_t cachelnsz; /* cache line size in 4byte units */ 74 u_int8_t intpin; /* PCI interrupt pin */ 75 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 76 77 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 78 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 79 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 80 81 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 82 u_int8_t nummaps; /* actual number of PCI maps used */ 83 84 u_int8_t bus; /* config space bus address */ 85 u_int8_t slot; /* config space slot address */ 86 u_int8_t func; /* config space function number */ 87 88 u_int16_t pp_cap; /* PCI power management capabilities */ 89 u_int8_t pp_status; /* config space address of PCI power status reg */ 90 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 91 u_int8_t pp_data; /* config space address of PCI power data reg */ 92 93} pcicfgregs; 94 95/* additional type 1 device config header information (PCI to PCI bridge) */ 96 97#ifdef PCI_A64 98#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 99#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 100#else 101#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 102#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 103#endif /* PCI_A64 */ 104 105#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 106#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 107 108typedef struct { 109 pci_addr_t pmembase; /* base address of prefetchable memory */ 110 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 111 u_int32_t membase; /* base address of memory window */ 112 u_int32_t memlimit; /* topmost address of memory window */ 113 u_int32_t iobase; /* base address of port window */ 114 u_int32_t iolimit; /* topmost address of port window */ 115 u_int16_t secstat; /* secondary bus status register */ 116 u_int16_t bridgectl; /* bridge control register */ 117 u_int8_t seclat; /* CardBus latency timer */ 118} pcih1cfgregs; 119 120/* additional type 2 device config header information (CardBus bridge) */ 121 122typedef struct { 123 u_int32_t membase0; /* base address of memory window */ 124 u_int32_t memlimit0; /* topmost address of memory window */ 125 u_int32_t membase1; /* base address of memory window */ 126 u_int32_t memlimit1; /* topmost address of memory window */ 127 u_int32_t iobase0; /* base address of port window */ 128 u_int32_t iolimit0; /* topmost address of port window */ 129 u_int32_t iobase1; /* base address of port window */ 130 u_int32_t iolimit1; /* topmost address of port window */ 131 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 132 u_int16_t secstat; /* secondary bus status register */ 133 u_int16_t bridgectl; /* bridge control register */ 134 u_int8_t seclat; /* CardBus latency timer */ 135} pcih2cfgregs; 136 137extern u_int32_t pci_numdevs; 138 139/* Only if the prerequisites are present */ 140#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 141struct pci_devinfo { 142 STAILQ_ENTRY(pci_devinfo) pci_links; 143 struct resource_list resources; 144 pcicfgregs cfg; 145 struct pci_conf conf; 146}; 147#endif 148 149#ifdef __alpha__ 150vm_offset_t pci_cvt_to_dense (vm_offset_t); 151vm_offset_t pci_cvt_to_bwx (vm_offset_t); 152#endif /* __alpha__ */ 153 154#ifdef _SYS_BUS_H_ 155 156#include "pci_if.h" 157 158/* 159 * Define pci-specific resource flags for accessing memory via dense 160 * or bwx memory spaces. These flags are ignored on i386. 161 */ 162#define PCI_RF_DENSE 0x10000 163#define PCI_RF_BWX 0x20000 164 165enum pci_device_ivars { 166 PCI_IVAR_SUBVENDOR, 167 PCI_IVAR_SUBDEVICE, 168 PCI_IVAR_VENDOR, 169 PCI_IVAR_DEVICE, 170 PCI_IVAR_DEVID, 171 PCI_IVAR_CLASS, 172 PCI_IVAR_SUBCLASS, 173 PCI_IVAR_PROGIF, 174 PCI_IVAR_REVID, 175 PCI_IVAR_INTPIN, 176 PCI_IVAR_IRQ, 177 PCI_IVAR_BUS, 178 PCI_IVAR_SLOT, 179 PCI_IVAR_FUNCTION, 180 PCI_IVAR_ETHADDR, 181}; 182 183/* 184 * Simplified accessors for pci devices 185 */ 186#define PCI_ACCESSOR(var, ivar, type) \ 187 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 188 189PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 190PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 191PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 192PCI_ACCESSOR(device, DEVICE, u_int16_t) 193PCI_ACCESSOR(devid, DEVID, u_int32_t) 194PCI_ACCESSOR(class, CLASS, u_int8_t) 195PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 196PCI_ACCESSOR(progif, PROGIF, u_int8_t) 197PCI_ACCESSOR(revid, REVID, u_int8_t) 198PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 199PCI_ACCESSOR(irq, IRQ, u_int8_t) 200PCI_ACCESSOR(bus, BUS, u_int8_t) 201PCI_ACCESSOR(slot, SLOT, u_int8_t) 202PCI_ACCESSOR(function, FUNCTION, u_int8_t) 203PCI_ACCESSOR(ether, ETHADDR, u_int8_t *) 204 205#undef PCI_ACCESSOR 206 207/* 208 * Operations on configuration space. 209 */ 210static __inline u_int32_t 211pci_read_config(device_t dev, int reg, int width) 212{ 213 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 214} 215 216static __inline void 217pci_write_config(device_t dev, int reg, u_int32_t val, int width) 218{ 219 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 220} 221 222/* 223 * Ivars for pci bridges. 224 */ 225 226/*typedef enum pci_device_ivars pcib_device_ivars;*/ 227enum pcib_device_ivars { 228 PCIB_IVAR_BUS 229}; 230 231#define PCIB_ACCESSOR(var, ivar, type) \ 232 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 233 234PCIB_ACCESSOR(bus, BUS, u_int32_t) 235 236#undef PCIB_ACCESSOR 237 238/* 239 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 240 * on i386 or other platforms should be mapped out in the MD pcireadconf 241 * code and not here, since the only MI invalid IRQ is 255. 242 */ 243#define PCI_INVALID_IRQ 255 244#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 245 246/* 247 * Convenience functions. 248 * 249 * These should be used in preference to manually manipulating 250 * configuration space. 251 */ 252static __inline void 253pci_enable_busmaster(device_t dev) 254{ 255 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 256} 257 258static __inline void 259pci_disable_busmaster(device_t dev) 260{ 261 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 262} 263 264static __inline void 265pci_enable_io(device_t dev, int space) 266{ 267 PCI_ENABLE_IO(device_get_parent(dev), dev, space); 268} 269 270static __inline void 271pci_disable_io(device_t dev, int space) 272{ 273 PCI_DISABLE_IO(device_get_parent(dev), dev, space); 274} 275 276/* 277 * PCI power states are as defined by ACPI: 278 * 279 * D0 State in which device is on and running. It is receiving full 280 * power from the system and delivering full functionality to the user. 281 * D1 Class-specific low-power state in which device context may or may not 282 * be lost. Buses in D1 cannot do anything to the bus that would force 283 * devices on that bus to loose context. 284 * D2 Class-specific low-power state in which device context may or may 285 * not be lost. Attains greater power savings than D1. Buses in D2 286 * can cause devices on that bus to loose some context. Devices in D2 287 * must be prepared for the bus to be in D2 or higher. 288 * D3 State in which the device is off and not running. Device context is 289 * lost. Power can be removed from the device. 290 */ 291#define PCI_POWERSTATE_D0 0 292#define PCI_POWERSTATE_D1 1 293#define PCI_POWERSTATE_D2 2 294#define PCI_POWERSTATE_D3 3 295#define PCI_POWERSTATE_UNKNOWN -1 296 297static __inline int 298pci_set_powerstate(device_t dev, int state) 299{ 300 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 301} 302 303static __inline int 304pci_get_powerstate(device_t dev) 305{ 306 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 307} 308 309device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); 310device_t pci_find_device(u_int16_t, u_int16_t); 311#endif /* _SYS_BUS_H_ */ 312 313/* 314 * cdev switch for control device, initialised in generic PCI code 315 */ 316extern struct cdevsw pcicdev; 317 318/* 319 * List of all PCI devices, generation count for the list. 320 */ 321STAILQ_HEAD(devlist, pci_devinfo); 322 323extern struct devlist pci_devq; 324extern u_int32_t pci_generation; 325 326#endif /* _PCIVAR_H_ */ 327