pcivar.h revision 90554
126159Sse/* 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2650477Speter * $FreeBSD: head/sys/dev/pci/pcivar.h 90554 2002-02-12 01:28:49Z msmith $ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 3139231Sgibbs#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#include <sys/queue.h> 3439231Sgibbs 3526159Sse/* some PCI bus constants */ 366767Sse 3726159Sse#define PCI_BUSMAX 255 /* highest supported bus number */ 3826159Sse#define PCI_SLOTMAX 31 /* highest supported slot number */ 3926159Sse#define PCI_FUNCMAX 7 /* highest supported function number */ 4026159Sse#define PCI_REGMAX 255 /* highest supported config register addr. */ 416100Sse 4226159Sse#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4326159Sse#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4426159Sse#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 456100Sse 4626159Sse/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 476100Sse 4826159Sse#ifdef PCI_A64 4926159Ssetypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5026159Sse#else 5126159Ssetypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5226159Sse#endif 536100Sse 5426159Sse/* config header information common to all header types */ 556100Sse 5626159Ssetypedef struct pcicfg { 5745720Speter struct device *dev; /* device which owns this */ 586100Sse 5926159Sse u_int16_t subvendor; /* card vendor ID */ 6026159Sse u_int16_t subdevice; /* card device ID, assigned by card vendor */ 6126159Sse u_int16_t vendor; /* chip vendor ID */ 6226159Sse u_int16_t device; /* chip device ID, assigned by chip vendor */ 636100Sse 6426159Sse u_int16_t cmdreg; /* disable/enable chip and PCI options */ 6526159Sse u_int16_t statreg; /* supported PCI features and error state */ 667233Sse 6738304Sgibbs u_int8_t baseclass; /* chip PCI class */ 6826159Sse u_int8_t subclass; /* chip PCI subclass */ 6926159Sse u_int8_t progif; /* chip PCI programming interface */ 7026159Sse u_int8_t revid; /* chip revision ID */ 716100Sse 7226159Sse u_int8_t hdrtype; /* chip config header type */ 7326159Sse u_int8_t cachelnsz; /* cache line size in 4byte units */ 7426159Sse u_int8_t intpin; /* PCI interrupt pin */ 7526159Sse u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 766100Sse 7726159Sse u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 7826159Sse u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 7926159Sse u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 806100Sse 8126159Sse u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 8226159Sse u_int8_t nummaps; /* actual number of PCI maps used */ 837233Sse 8426159Sse u_int8_t bus; /* config space bus address */ 8526159Sse u_int8_t slot; /* config space slot address */ 8626159Sse u_int8_t func; /* config space function number */ 877233Sse 8869953Smsmith u_int16_t pp_cap; /* PCI power management capabilities */ 8969953Smsmith u_int8_t pp_status; /* config space address of PCI power status reg */ 9069953Smsmith u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 9169953Smsmith u_int8_t pp_data; /* config space address of PCI power data reg */ 9269953Smsmith 9326159Sse} pcicfgregs; 946100Sse 9526159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 966100Sse 9726159Sse#ifdef PCI_A64 9826159Sse#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 9926159Sse#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 10026159Sse#else 10126159Sse#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 10226159Sse#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 10326159Sse#endif /* PCI_A64 */ 1046100Sse 10526159Sse#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 10626159Sse#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1077233Sse 10826159Ssetypedef struct { 10926159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 11026159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 11126159Sse u_int32_t membase; /* base address of memory window */ 11226159Sse u_int32_t memlimit; /* topmost address of memory window */ 11326159Sse u_int32_t iobase; /* base address of port window */ 11426159Sse u_int32_t iolimit; /* topmost address of port window */ 11526159Sse u_int16_t secstat; /* secondary bus status register */ 11626159Sse u_int16_t bridgectl; /* bridge control register */ 11726159Sse u_int8_t seclat; /* CardBus latency timer */ 11826159Sse} pcih1cfgregs; 1196100Sse 12026159Sse/* additional type 2 device config header information (CardBus bridge) */ 12126159Sse 12226159Ssetypedef struct { 12326159Sse u_int32_t membase0; /* base address of memory window */ 12426159Sse u_int32_t memlimit0; /* topmost address of memory window */ 12526159Sse u_int32_t membase1; /* base address of memory window */ 12626159Sse u_int32_t memlimit1; /* topmost address of memory window */ 12726159Sse u_int32_t iobase0; /* base address of port window */ 12826159Sse u_int32_t iolimit0; /* topmost address of port window */ 12926159Sse u_int32_t iobase1; /* base address of port window */ 13026159Sse u_int32_t iolimit1; /* topmost address of port window */ 13126159Sse u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 13226159Sse u_int16_t secstat; /* secondary bus status register */ 13326159Sse u_int16_t bridgectl; /* bridge control register */ 13426159Sse u_int8_t seclat; /* CardBus latency timer */ 13526159Sse} pcih2cfgregs; 13626159Sse 13739231Sgibbsextern u_int32_t pci_numdevs; 13839231Sgibbs 13961047Speter/* Only if the prerequisites are present */ 14061047Speter#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 14161047Speterstruct pci_devinfo { 14261047Speter STAILQ_ENTRY(pci_devinfo) pci_links; 14361047Speter struct resource_list resources; 14461047Speter pcicfgregs cfg; 14561047Speter struct pci_conf conf; 14661047Speter}; 14761047Speter#endif 14839231Sgibbs 14940004Sdfr#ifdef __alpha__ 15040004Sdfrvm_offset_t pci_cvt_to_dense (vm_offset_t); 15140004Sdfrvm_offset_t pci_cvt_to_bwx (vm_offset_t); 15240004Sdfr#endif /* __alpha__ */ 15345720Speter 15445720Speter#ifdef _SYS_BUS_H_ 15545720Speter 15645720Speter#include "pci_if.h" 15745720Speter 15852243Sdfr/* 15952243Sdfr * Define pci-specific resource flags for accessing memory via dense 16052243Sdfr * or bwx memory spaces. These flags are ignored on i386. 16152243Sdfr */ 16252243Sdfr#define PCI_RF_DENSE 0x10000 16352243Sdfr#define PCI_RF_BWX 0x20000 16452243Sdfr 16545720Speterenum pci_device_ivars { 16669953Smsmith PCI_IVAR_SUBVENDOR, 16769953Smsmith PCI_IVAR_SUBDEVICE, 16869953Smsmith PCI_IVAR_VENDOR, 16969953Smsmith PCI_IVAR_DEVICE, 17069953Smsmith PCI_IVAR_DEVID, 17169953Smsmith PCI_IVAR_CLASS, 17269953Smsmith PCI_IVAR_SUBCLASS, 17369953Smsmith PCI_IVAR_PROGIF, 17469953Smsmith PCI_IVAR_REVID, 17569953Smsmith PCI_IVAR_INTPIN, 17669953Smsmith PCI_IVAR_IRQ, 17769953Smsmith PCI_IVAR_BUS, 17869953Smsmith PCI_IVAR_SLOT, 17969953Smsmith PCI_IVAR_FUNCTION, 18045720Speter}; 18145720Speter 18245720Speter/* 18345720Speter * Simplified accessors for pci devices 18445720Speter */ 18588375Stmm#define PCI_ACCESSOR(var, ivar, type) \ 18688375Stmm __BUS_ACCESSOR(pci, var, PCI, ivar, type) 18745720Speter 18845720SpeterPCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 18945720SpeterPCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 19045720SpeterPCI_ACCESSOR(vendor, VENDOR, u_int16_t) 19145720SpeterPCI_ACCESSOR(device, DEVICE, u_int16_t) 19245720SpeterPCI_ACCESSOR(devid, DEVID, u_int32_t) 19345720SpeterPCI_ACCESSOR(class, CLASS, u_int8_t) 19445720SpeterPCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 19545720SpeterPCI_ACCESSOR(progif, PROGIF, u_int8_t) 19645720SpeterPCI_ACCESSOR(revid, REVID, u_int8_t) 19745720SpeterPCI_ACCESSOR(intpin, INTPIN, u_int8_t) 19845720SpeterPCI_ACCESSOR(irq, IRQ, u_int8_t) 19945720SpeterPCI_ACCESSOR(bus, BUS, u_int8_t) 20045720SpeterPCI_ACCESSOR(slot, SLOT, u_int8_t) 20145720SpeterPCI_ACCESSOR(function, FUNCTION, u_int8_t) 20245720Speter 20366416Speter#undef PCI_ACCESSOR 20466416Speter 20569953Smsmith/* 20669953Smsmith * Operations on configuration space. 20769953Smsmith */ 20845720Speterstatic __inline u_int32_t 20945720Speterpci_read_config(device_t dev, int reg, int width) 21045720Speter{ 21145720Speter return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 21245720Speter} 21345720Speter 21445720Speterstatic __inline void 21545720Speterpci_write_config(device_t dev, int reg, u_int32_t val, int width) 21645720Speter{ 21745720Speter PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 21845720Speter} 21945720Speter 22047339Sgallatin/* 22147339Sgallatin * Ivars for pci bridges. 22247339Sgallatin */ 22347339Sgallatin 22447339Sgallatin/*typedef enum pci_device_ivars pcib_device_ivars;*/ 22547339Sgallatinenum pcib_device_ivars { 22665176Sdfr PCIB_IVAR_BUS 22747339Sgallatin}; 22847339Sgallatin 22947339Sgallatin#define PCIB_ACCESSOR(A, B, T) \ 23047339Sgallatin \ 23147339Sgallatinstatic __inline T pcib_get_ ## A(device_t dev) \ 23247339Sgallatin{ \ 23369953Smsmith uintptr_t v; \ 23469953Smsmith BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 23569953Smsmith return (T) v; \ 23647339Sgallatin} \ 23747339Sgallatin \ 23847339Sgallatinstatic __inline void pcib_set_ ## A(device_t dev, T t) \ 23947339Sgallatin{ \ 24069953Smsmith uintptr_t v = (uintptr_t) t; \ 24169953Smsmith BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 24247339Sgallatin} 24347339Sgallatin 24465176SdfrPCIB_ACCESSOR(bus, BUS, u_int32_t) 24547339Sgallatin 24666416Speter#undef PCIB_ACCESSOR 24766416Speter 24869953Smsmith/* 24990554Smsmith * PCI interrupt validation. 25090554Smsmith */ 25190554Smsmith#define PCI_INTERRUPT_VALID(x) (((x) != 0) && ((x) != 255)) 25290554Smsmith 25390554Smsmith/* 25469953Smsmith * Convenience functions. 25569953Smsmith * 25669953Smsmith * These should be used in preference to manually manipulating 25769953Smsmith * configuration space. 25869953Smsmith */ 25973185Speterstatic __inline void 26073185Speterpci_enable_busmaster(device_t dev) 26173185Speter{ 26273185Speter PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 26373185Speter} 26445720Speter 26573185Speterstatic __inline void 26673185Speterpci_disable_busmaster(device_t dev) 26773185Speter{ 26873185Speter PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 26973185Speter} 27073185Speter 27173185Speterstatic __inline void 27273185Speterpci_enable_io(device_t dev, int space) 27373185Speter{ 27473185Speter PCI_ENABLE_IO(device_get_parent(dev), dev, space); 27573185Speter} 27673185Speter 27773185Speterstatic __inline void 27873185Speterpci_disable_io(device_t dev, int space) 27973185Speter{ 28073185Speter PCI_DISABLE_IO(device_get_parent(dev), dev, space); 28173185Speter} 28273185Speter 28369953Smsmith/* 28469953Smsmith * PCI power states are as defined by ACPI: 28569953Smsmith * 28669953Smsmith * D0 State in which device is on and running. It is receiving full 28769953Smsmith * power from the system and delivering full functionality to the user. 28869953Smsmith * D1 Class-specific low-power state in which device context may or may not 28969953Smsmith * be lost. Buses in D1 cannot do anything to the bus that would force 29069953Smsmith * devices on that bus to loose context. 29169953Smsmith * D2 Class-specific low-power state in which device context may or may 29269953Smsmith * not be lost. Attains greater power savings than D1. Buses in D2 29369953Smsmith * can cause devices on that bus to loose some context. Devices in D2 29469953Smsmith * must be prepared for the bus to be in D2 or higher. 29569953Smsmith * D3 State in which the device is off and not running. Device context is 29669953Smsmith * lost. Power can be removed from the device. 29769953Smsmith */ 29869953Smsmith#define PCI_POWERSTATE_D0 0 29969953Smsmith#define PCI_POWERSTATE_D1 1 30069953Smsmith#define PCI_POWERSTATE_D2 2 30169953Smsmith#define PCI_POWERSTATE_D3 3 30269953Smsmith#define PCI_POWERSTATE_UNKNOWN -1 30326159Sse 30473185Speterstatic __inline int 30573185Speterpci_set_powerstate(device_t dev, int state) 30673185Speter{ 30773185Speter return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 30873185Speter} 30958287Speter 31073185Speterstatic __inline int 31173185Speterpci_get_powerstate(device_t dev) 31273185Speter{ 31373185Speter return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 31473185Speter} 31573185Speter 31689171Smdodddevice_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); 31789171Smdodddevice_t pci_find_device(u_int16_t, u_int16_t); 31869953Smsmith#endif /* _SYS_BUS_H_ */ 31961047Speter 32069953Smsmith/* 32169953Smsmith * cdev switch for control device, initialised in generic PCI code 32269953Smsmith */ 32369953Smsmithextern struct cdevsw pcicdev; 32458287Speter 32569953Smsmith/* 32669953Smsmith * List of all PCI devices, generation count for the list. 32769953Smsmith */ 32888184SmdoddSTAILQ_HEAD(devlist, pci_devinfo); 32912453Sbde 33088184Smdoddextern struct devlist pci_devq; 33188184Smdoddextern u_int32_t pci_generation; 33288184Smdodd 33339231Sgibbs#endif /* _PCIVAR_H_ */ 334