pcivar.h revision 50477
10Sduke/* 211884Sykantser * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 30Sduke * All rights reserved. 40Sduke * 50Sduke * Redistribution and use in source and binary forms, with or without 60Sduke * modification, are permitted provided that the following conditions 70Sduke * are met: 80Sduke * 1. Redistributions of source code must retain the above copyright 90Sduke * notice unmodified, this list of conditions, and the following 100Sduke * disclaimer. 110Sduke * 2. Redistributions in binary form must reproduce the above copyright 120Sduke * notice, this list of conditions and the following disclaimer in the 130Sduke * documentation and/or other materials provided with the distribution. 140Sduke * 150Sduke * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 160Sduke * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 170Sduke * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 180Sduke * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 192362Sohair * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 202362Sohair * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 212362Sohair * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 220Sduke * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 230Sduke * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 240Sduke * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 250Sduke * 260Sduke * $FreeBSD: head/sys/dev/pci/pcivar.h 50477 1999-08-28 01:08:13Z peter $ 270Sduke * 280Sduke */ 2916930Siignatyev 300Sduke#ifndef _PCIVAR_H_ 310Sduke#define _PCIVAR_H_ 320Sduke 330Sduke#ifndef PCI_COMPAT 340Sduke#define PCI_COMPAT 350Sduke#endif 360Sduke 370Sduke#include <pci/pci_ioctl.h> /* XXX KDM */ 380Sduke#include <sys/queue.h> 390Sduke 400Sduke/* some PCI bus constants */ 410Sduke 420Sduke#define PCI_BUSMAX 255 /* highest supported bus number */ 430Sduke#define PCI_SLOTMAX 31 /* highest supported slot number */ 440Sduke#define PCI_FUNCMAX 7 /* highest supported function number */ 450Sduke#define PCI_REGMAX 255 /* highest supported config register addr. */ 460Sduke 470Sduke#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 480Sduke#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 490Sduke#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 500Sduke 510Sduke/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 520Sduke 530Sduke#ifdef PCI_A64 540Sduketypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 550Sduke#else 560Sduketypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 570Sduke#endif 580Sduke 590Sduke/* map register information */ 600Sduke 610Sduketypedef struct { 620Sduke u_int32_t base; 630Sduke u_int8_t type; 640Sduke#define PCI_MAPMEM 0x01 /* memory map */ 650Sduke#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 660Sduke#define PCI_MAPPORT 0x04 /* port map */ 670Sduke u_int8_t ln2size; 680Sduke u_int8_t ln2range; 690Sduke u_int8_t reg; /* offset of map register in config space */ 700Sduke/* u_int8_t dummy;*/ 710Sduke struct resource *res; /* handle from resource manager */ 720Sduke} pcimap; 730Sduke 740Sduke/* config header information common to all header types */ 750Sduke 760Sduketypedef struct pcicfg { 770Sduke struct device *dev; /* device which owns this */ 780Sduke pcimap *map; /* pointer to array of PCI maps */ 790Sduke void *hdrspec; /* pointer to header type specific data */ 800Sduke struct resource *irqres; /* resource descriptor for interrupt mapping */ 810Sduke 820Sduke u_int16_t subvendor; /* card vendor ID */ 830Sduke u_int16_t subdevice; /* card device ID, assigned by card vendor */ 840Sduke u_int16_t vendor; /* chip vendor ID */ 850Sduke u_int16_t device; /* chip device ID, assigned by chip vendor */ 860Sduke 870Sduke u_int16_t cmdreg; /* disable/enable chip and PCI options */ 880Sduke u_int16_t statreg; /* supported PCI features and error state */ 890Sduke 900Sduke u_int8_t baseclass; /* chip PCI class */ 910Sduke u_int8_t subclass; /* chip PCI subclass */ 920Sduke u_int8_t progif; /* chip PCI programming interface */ 930Sduke u_int8_t revid; /* chip revision ID */ 940Sduke 950Sduke u_int8_t hdrtype; /* chip config header type */ 960Sduke u_int8_t cachelnsz; /* cache line size in 4byte units */ 970Sduke u_int8_t intpin; /* PCI interrupt pin */ 980Sduke u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 990Sduke 1000Sduke u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 1010Sduke u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 1020Sduke u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 1030Sduke 1040Sduke u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 1050Sduke u_int8_t nummaps; /* actual number of PCI maps used */ 1060Sduke 1070Sduke u_int8_t hose; /* hose which bus is attached to */ 1080Sduke u_int8_t bus; /* config space bus address */ 1090Sduke u_int8_t slot; /* config space slot address */ 1100Sduke u_int8_t func; /* config space function number */ 1110Sduke 1120Sduke u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 1130Sduke u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 1140Sduke} pcicfgregs; 1150Sduke 1160Sduke/* additional type 1 device config header information (PCI to PCI bridge) */ 1170Sduke 1180Sduke#ifdef PCI_A64 1190Sduke#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 1200Sduke#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 1210Sduke#else 1220Sduke#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 1230Sduke#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 1240Sduke#endif /* PCI_A64 */ 1250Sduke 1260Sduke#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 1270Sduke#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1280Sduke 1290Sduketypedef struct { 1300Sduke pci_addr_t pmembase; /* base address of prefetchable memory */ 1310Sduke pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 1320Sduke u_int32_t membase; /* base address of memory window */ 1330Sduke u_int32_t memlimit; /* topmost address of memory window */ 1340Sduke u_int32_t iobase; /* base address of port window */ 1350Sduke u_int32_t iolimit; /* topmost address of port window */ 1360Sduke u_int16_t secstat; /* secondary bus status register */ 1370Sduke u_int16_t bridgectl; /* bridge control register */ 1380Sduke u_int8_t seclat; /* CardBus latency timer */ 1390Sduke} pcih1cfgregs; 1400Sduke 1410Sduke/* additional type 2 device config header information (CardBus bridge) */ 1420Sduke 1430Sduketypedef struct { 1440Sduke u_int32_t membase0; /* base address of memory window */ 1450Sduke u_int32_t memlimit0; /* topmost address of memory window */ 1460Sduke u_int32_t membase1; /* base address of memory window */ 1470Sduke u_int32_t memlimit1; /* topmost address of memory window */ 1480Sduke u_int32_t iobase0; /* base address of port window */ 149 u_int32_t iolimit0; /* topmost address of port window */ 150 u_int32_t iobase1; /* base address of port window */ 151 u_int32_t iolimit1; /* topmost address of port window */ 152 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 153 u_int16_t secstat; /* secondary bus status register */ 154 u_int16_t bridgectl; /* bridge control register */ 155 u_int8_t seclat; /* CardBus latency timer */ 156} pcih2cfgregs; 157 158/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 159 160typedef struct pciattach { 161 int unit; 162 int pcibushigh; 163 struct pciattach *next; 164} pciattach; 165 166struct pci_devinfo { 167 STAILQ_ENTRY(pci_devinfo) pci_links; 168 pcicfgregs cfg; 169 struct pci_conf conf; 170}; 171 172extern u_int32_t pci_numdevs; 173 174 175/* externally visible functions */ 176 177const char *ide_pci_match(struct device *dev); 178 179/* low level PCI config register functions provided by pcibus.c */ 180 181int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 182void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 183#ifdef __alpha__ 184vm_offset_t pci_cvt_to_dense (vm_offset_t); 185vm_offset_t pci_cvt_to_bwx (vm_offset_t); 186#endif /* __alpha__ */ 187 188/* low level devlist operations for the 2.2 compatibility code in pci.c */ 189pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 190 191#ifdef _SYS_BUS_H_ 192 193#include "pci_if.h" 194 195enum pci_device_ivars { 196 PCI_IVAR_SUBVENDOR, 197 PCI_IVAR_SUBDEVICE, 198 PCI_IVAR_VENDOR, 199 PCI_IVAR_DEVICE, 200 PCI_IVAR_DEVID, 201 PCI_IVAR_CLASS, 202 PCI_IVAR_SUBCLASS, 203 PCI_IVAR_PROGIF, 204 PCI_IVAR_REVID, 205 PCI_IVAR_INTPIN, 206 PCI_IVAR_IRQ, 207 PCI_IVAR_BUS, 208 PCI_IVAR_SLOT, 209 PCI_IVAR_FUNCTION, 210 PCI_IVAR_SECONDARYBUS, 211 PCI_IVAR_SUBORDINATEBUS, 212 PCI_IVAR_HOSE, 213}; 214 215/* 216 * Simplified accessors for pci devices 217 */ 218#define PCI_ACCESSOR(A, B, T) \ 219 \ 220static __inline T pci_get_ ## A(device_t dev) \ 221{ \ 222 uintptr_t v; \ 223 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 224 return (T) v; \ 225} \ 226 \ 227static __inline void pci_set_ ## A(device_t dev, T t) \ 228{ \ 229 u_long v = (u_long) t; \ 230 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 231} 232 233PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 234PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 235PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 236PCI_ACCESSOR(device, DEVICE, u_int16_t) 237PCI_ACCESSOR(devid, DEVID, u_int32_t) 238PCI_ACCESSOR(class, CLASS, u_int8_t) 239PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 240PCI_ACCESSOR(progif, PROGIF, u_int8_t) 241PCI_ACCESSOR(revid, REVID, u_int8_t) 242PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 243PCI_ACCESSOR(irq, IRQ, u_int8_t) 244PCI_ACCESSOR(bus, BUS, u_int8_t) 245PCI_ACCESSOR(slot, SLOT, u_int8_t) 246PCI_ACCESSOR(function, FUNCTION, u_int8_t) 247PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 248PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 249PCI_ACCESSOR(hose, HOSE, u_int32_t) 250 251static __inline u_int32_t 252pci_read_config(device_t dev, int reg, int width) 253{ 254 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 255} 256 257static __inline void 258pci_write_config(device_t dev, int reg, u_int32_t val, int width) 259{ 260 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 261} 262 263/* 264 * Ivars for pci bridges. 265 */ 266 267/*typedef enum pci_device_ivars pcib_device_ivars;*/ 268enum pcib_device_ivars { 269 PCIB_IVAR_HOSE, 270}; 271 272#define PCIB_ACCESSOR(A, B, T) \ 273 \ 274static __inline T pcib_get_ ## A(device_t dev) \ 275{ \ 276 uintptr_t v; \ 277 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 278 return (T) v; \ 279} \ 280 \ 281static __inline void pcib_set_ ## A(device_t dev, T t) \ 282{ \ 283 u_long v = (u_long) t; \ 284 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 285} 286 287PCIB_ACCESSOR(hose, HOSE, u_int32_t) 288 289#endif 290 291/* for compatibility to FreeBSD-2.2 version of PCI code */ 292 293#ifdef PCI_COMPAT 294 295typedef pcicfgregs *pcici_t; 296typedef unsigned pcidi_t; 297typedef void pci_inthand_t(void *arg); 298 299#define pci_max_burst_len (3) 300 301/* just copied from old PCI code for now ... */ 302 303extern int pci_mechanism; 304 305struct pci_device { 306 char* pd_name; 307 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 308 void (*pd_attach) (pcici_t tag, int unit); 309 u_long *pd_count; 310 int (*pd_shutdown) (int, int); 311}; 312 313#ifdef __i386__ 314typedef u_short pci_port_t; 315#else 316typedef u_int pci_port_t; 317#endif 318 319u_long pci_conf_read (pcici_t tag, u_long reg); 320void pci_conf_write (pcici_t tag, u_long reg, u_long data); 321int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 322int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 323int pci_map_dense (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 324int pci_map_bwx (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 325int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 326 intrmask_t *maskptr); 327int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 328 intrmask_t *maskptr, u_int flags); 329int pci_unmap_int (pcici_t tag); 330 331pcici_t pci_get_parent_from_tag(pcici_t tag); 332int pci_get_bus_from_tag(pcici_t tag); 333 334struct module; 335int compat_pci_handler (struct module *, int, void *); 336#define COMPAT_PCI_DRIVER(name, pcidata) \ 337static moduledata_t name##_mod = { \ 338 #name, \ 339 compat_pci_handler, \ 340 &pcidata \ 341}; \ 342DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 343 344 345#endif /* PCI_COMPAT */ 346#endif /* _PCIVAR_H_ */ 347