pcivar.h revision 47339
126159Sse/* 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2647339Sgallatin * $Id: pcivar.h,v 1.32 1999/05/18 20:48:38 peter Exp $ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 3139231Sgibbs#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#ifndef PCI_COMPAT 3439231Sgibbs#define PCI_COMPAT 3539231Sgibbs#endif 3639231Sgibbs 3739231Sgibbs#include <pci/pci_ioctl.h> /* XXX KDM */ 3839231Sgibbs#include <sys/queue.h> 3939231Sgibbs 4026159Sse/* some PCI bus constants */ 416767Sse 4226159Sse#define PCI_BUSMAX 255 /* highest supported bus number */ 4326159Sse#define PCI_SLOTMAX 31 /* highest supported slot number */ 4426159Sse#define PCI_FUNCMAX 7 /* highest supported function number */ 4526159Sse#define PCI_REGMAX 255 /* highest supported config register addr. */ 466100Sse 4726159Sse#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4826159Sse#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4926159Sse#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 506100Sse 5126159Sse/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 526100Sse 5326159Sse#ifdef PCI_A64 5426159Ssetypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5526159Sse#else 5626159Ssetypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5726159Sse#endif 586100Sse 5926159Sse/* map register information */ 607233Sse 6126159Ssetypedef struct { 6226159Sse u_int32_t base; 6326159Sse u_int8_t type; 6426159Sse#define PCI_MAPMEM 0x01 /* memory map */ 6526159Sse#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 6626159Sse#define PCI_MAPPORT 0x04 /* port map */ 6726159Sse u_int8_t ln2size; 6826159Sse u_int8_t ln2range; 6942867Sse u_int8_t reg; /* offset of map register in config space */ 7045720Speter/* u_int8_t dummy;*/ 7145720Speter struct resource *res; /* handle from resource manager */ 7226159Sse} pcimap; 736100Sse 7426159Sse/* config header information common to all header types */ 756100Sse 7626159Ssetypedef struct pcicfg { 7745720Speter struct device *dev; /* device which owns this */ 7826159Sse pcimap *map; /* pointer to array of PCI maps */ 7926159Sse void *hdrspec; /* pointer to header type specific data */ 8045720Speter struct resource *irqres; /* resource descriptor for interrupt mapping */ 816100Sse 8226159Sse u_int16_t subvendor; /* card vendor ID */ 8326159Sse u_int16_t subdevice; /* card device ID, assigned by card vendor */ 8426159Sse u_int16_t vendor; /* chip vendor ID */ 8526159Sse u_int16_t device; /* chip device ID, assigned by chip vendor */ 866100Sse 8726159Sse u_int16_t cmdreg; /* disable/enable chip and PCI options */ 8826159Sse u_int16_t statreg; /* supported PCI features and error state */ 897233Sse 9038304Sgibbs u_int8_t baseclass; /* chip PCI class */ 9126159Sse u_int8_t subclass; /* chip PCI subclass */ 9226159Sse u_int8_t progif; /* chip PCI programming interface */ 9326159Sse u_int8_t revid; /* chip revision ID */ 946100Sse 9526159Sse u_int8_t hdrtype; /* chip config header type */ 9626159Sse u_int8_t cachelnsz; /* cache line size in 4byte units */ 9726159Sse u_int8_t intpin; /* PCI interrupt pin */ 9826159Sse u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 996100Sse 10026159Sse u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 10126159Sse u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 10226159Sse u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 1036100Sse 10426159Sse u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 10526159Sse u_int8_t nummaps; /* actual number of PCI maps used */ 1067233Sse 10747339Sgallatin u_int8_t hose; /* hose which bus is attached to */ 10826159Sse u_int8_t bus; /* config space bus address */ 10926159Sse u_int8_t slot; /* config space slot address */ 11026159Sse u_int8_t func; /* config space function number */ 1117233Sse 11226159Sse u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 11326159Sse u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 11426159Sse} pcicfgregs; 1156100Sse 11626159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 1176100Sse 11826159Sse#ifdef PCI_A64 11926159Sse#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 12026159Sse#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 12126159Sse#else 12226159Sse#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 12326159Sse#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 12426159Sse#endif /* PCI_A64 */ 1256100Sse 12626159Sse#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 12726159Sse#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1287233Sse 12926159Ssetypedef struct { 13026159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 13126159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 13226159Sse u_int32_t membase; /* base address of memory window */ 13326159Sse u_int32_t memlimit; /* topmost address of memory window */ 13426159Sse u_int32_t iobase; /* base address of port window */ 13526159Sse u_int32_t iolimit; /* topmost address of port window */ 13626159Sse u_int16_t secstat; /* secondary bus status register */ 13726159Sse u_int16_t bridgectl; /* bridge control register */ 13826159Sse u_int8_t seclat; /* CardBus latency timer */ 13926159Sse} pcih1cfgregs; 1406100Sse 14126159Sse/* additional type 2 device config header information (CardBus bridge) */ 14226159Sse 14326159Ssetypedef struct { 14426159Sse u_int32_t membase0; /* base address of memory window */ 14526159Sse u_int32_t memlimit0; /* topmost address of memory window */ 14626159Sse u_int32_t membase1; /* base address of memory window */ 14726159Sse u_int32_t memlimit1; /* topmost address of memory window */ 14826159Sse u_int32_t iobase0; /* base address of port window */ 14926159Sse u_int32_t iolimit0; /* topmost address of port window */ 15026159Sse u_int32_t iobase1; /* base address of port window */ 15126159Sse u_int32_t iolimit1; /* topmost address of port window */ 15226159Sse u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 15326159Sse u_int16_t secstat; /* secondary bus status register */ 15426159Sse u_int16_t bridgectl; /* bridge control register */ 15526159Sse u_int8_t seclat; /* CardBus latency timer */ 15626159Sse} pcih2cfgregs; 15726159Sse 15826159Sse/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 15926159Sse 16026159Ssetypedef struct pciattach { 16126159Sse int unit; 16226159Sse int pcibushigh; 16326159Sse struct pciattach *next; 16426159Sse} pciattach; 16526159Sse 16639231Sgibbsstruct pci_devinfo { 16739231Sgibbs STAILQ_ENTRY(pci_devinfo) pci_links; 16839231Sgibbs pcicfgregs cfg; 16939231Sgibbs struct pci_conf conf; 17039231Sgibbs}; 17139231Sgibbs 17239231Sgibbsextern u_int32_t pci_numdevs; 17339231Sgibbs 17439231Sgibbs 17526159Sse/* externally visible functions */ 17626159Sse 17746993Speterconst char *ide_pci_match(struct device *dev); 17826159Sse 17926159Sse/* low level PCI config register functions provided by pcibus.c */ 18026159Sse 18126159Sseint pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 18226159Ssevoid pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 18340004Sdfr#ifdef __alpha__ 18440004Sdfrvm_offset_t pci_cvt_to_dense (vm_offset_t); 18540004Sdfrvm_offset_t pci_cvt_to_bwx (vm_offset_t); 18640004Sdfr#endif /* __alpha__ */ 18745720Speter 18845720Speter#ifdef _SYS_BUS_H_ 18945720Speter 19045720Speter#include "pci_if.h" 19145720Speter 19245720Speterenum pci_device_ivars { 19345720Speter PCI_IVAR_SUBVENDOR, 19445720Speter PCI_IVAR_SUBDEVICE, 19545720Speter PCI_IVAR_VENDOR, 19645720Speter PCI_IVAR_DEVICE, 19745720Speter PCI_IVAR_DEVID, 19845720Speter PCI_IVAR_CLASS, 19945720Speter PCI_IVAR_SUBCLASS, 20045720Speter PCI_IVAR_PROGIF, 20145720Speter PCI_IVAR_REVID, 20245720Speter PCI_IVAR_INTPIN, 20345720Speter PCI_IVAR_IRQ, 20445720Speter PCI_IVAR_BUS, 20545720Speter PCI_IVAR_SLOT, 20645720Speter PCI_IVAR_FUNCTION, 20745720Speter PCI_IVAR_SECONDARYBUS, 20845720Speter PCI_IVAR_SUBORDINATEBUS, 20947339Sgallatin PCI_IVAR_HOSE, 21045720Speter}; 21145720Speter 21245720Speter/* 21345720Speter * Simplified accessors for pci devices 21445720Speter */ 21545720Speter#define PCI_ACCESSOR(A, B, T) \ 21645720Speter \ 21745720Speterstatic __inline T pci_get_ ## A(device_t dev) \ 21845720Speter{ \ 21945720Speter uintptr_t v; \ 22045720Speter BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 22145720Speter return (T) v; \ 22245720Speter} \ 22345720Speter \ 22445720Speterstatic __inline void pci_set_ ## A(device_t dev, T t) \ 22545720Speter{ \ 22645720Speter u_long v = (u_long) t; \ 22745720Speter BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 22845720Speter} 22945720Speter 23045720SpeterPCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 23145720SpeterPCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 23245720SpeterPCI_ACCESSOR(vendor, VENDOR, u_int16_t) 23345720SpeterPCI_ACCESSOR(device, DEVICE, u_int16_t) 23445720SpeterPCI_ACCESSOR(devid, DEVID, u_int32_t) 23545720SpeterPCI_ACCESSOR(class, CLASS, u_int8_t) 23645720SpeterPCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 23745720SpeterPCI_ACCESSOR(progif, PROGIF, u_int8_t) 23845720SpeterPCI_ACCESSOR(revid, REVID, u_int8_t) 23945720SpeterPCI_ACCESSOR(intpin, INTPIN, u_int8_t) 24045720SpeterPCI_ACCESSOR(irq, IRQ, u_int8_t) 24145720SpeterPCI_ACCESSOR(bus, BUS, u_int8_t) 24245720SpeterPCI_ACCESSOR(slot, SLOT, u_int8_t) 24345720SpeterPCI_ACCESSOR(function, FUNCTION, u_int8_t) 24445720SpeterPCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 24545720SpeterPCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 24647339SgallatinPCI_ACCESSOR(hose, HOSE, u_int32_t) 24745720Speter 24845720Speterstatic __inline u_int32_t 24945720Speterpci_read_config(device_t dev, int reg, int width) 25045720Speter{ 25145720Speter return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 25245720Speter} 25345720Speter 25445720Speterstatic __inline void 25545720Speterpci_write_config(device_t dev, int reg, u_int32_t val, int width) 25645720Speter{ 25745720Speter PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 25845720Speter} 25945720Speter 26047339Sgallatin/* 26147339Sgallatin * Ivars for pci bridges. 26247339Sgallatin */ 26347339Sgallatin 26447339Sgallatin/*typedef enum pci_device_ivars pcib_device_ivars;*/ 26547339Sgallatinenum pcib_device_ivars { 26647339Sgallatin PCIB_IVAR_HOSE, 26747339Sgallatin}; 26847339Sgallatin 26947339Sgallatin#define PCIB_ACCESSOR(A, B, T) \ 27047339Sgallatin \ 27147339Sgallatinstatic __inline T pcib_get_ ## A(device_t dev) \ 27247339Sgallatin{ \ 27347339Sgallatin uintptr_t v; \ 27447339Sgallatin BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 27547339Sgallatin return (T) v; \ 27647339Sgallatin} \ 27747339Sgallatin \ 27847339Sgallatinstatic __inline void pcib_set_ ## A(device_t dev, T t) \ 27947339Sgallatin{ \ 28047339Sgallatin u_long v = (u_long) t; \ 28147339Sgallatin BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 28247339Sgallatin} 28347339Sgallatin 28447339SgallatinPCIB_ACCESSOR(hose, HOSE, u_int32_t) 28547339Sgallatin 28645720Speter#endif 28745720Speter 28826159Sse/* for compatibility to FreeBSD-2.2 version of PCI code */ 28926159Sse 29026159Sse#ifdef PCI_COMPAT 29126159Sse 29226159Ssetypedef pcicfgregs *pcici_t; 29326159Ssetypedef unsigned pcidi_t; 29413597Ssetypedef void pci_inthand_t(void *arg); 29512453Sbde 29626159Sse#define pci_max_burst_len (3) 29726159Sse 29826159Sse/* just copied from old PCI code for now ... */ 29926159Sse 30026159Sseextern int pci_mechanism; 30126159Sse 30226159Ssestruct pci_device { 30326159Sse char* pd_name; 30441766Sdillon const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 30526159Sse void (*pd_attach) (pcici_t tag, int unit); 30626159Sse u_long *pd_count; 30726159Sse int (*pd_shutdown) (int, int); 3087233Sse}; 3097233Sse 31037841Sdfr#ifdef __i386__ 31137841Sdfrtypedef u_short pci_port_t; 31237841Sdfr#else 31337841Sdfrtypedef u_int pci_port_t; 31437841Sdfr#endif 31537841Sdfr 31626159Sseu_long pci_conf_read (pcici_t tag, u_long reg); 31726159Ssevoid pci_conf_write (pcici_t tag, u_long reg, u_long data); 31837841Sdfrint pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 31926159Sseint pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 32040004Sdfrint pci_map_dense (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 32140004Sdfrint pci_map_bwx (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 32242614Sbdeint pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 32342614Sbde intrmask_t *maskptr); 32442614Sbdeint pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 32542614Sbde intrmask_t *maskptr, u_int flags); 3267233Sseint pci_unmap_int (pcici_t tag); 3277233Sse 32846591Speterstruct module; 32946591Speterint compat_pci_handler (struct module *, int, void *); 33046023Speter#define COMPAT_PCI_DRIVER(name, pcidata) \ 33146023Speterstatic moduledata_t name##_mod = { \ 33246023Speter #name, \ 33346023Speter compat_pci_handler, \ 33446023Speter &pcidata \ 33546023Speter}; \ 33646023SpeterDECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 33746023Speter 33846023Speter 33926159Sse#endif /* PCI_COMPAT */ 34039231Sgibbs#endif /* _PCIVAR_H_ */ 341