pcivar.h revision 39231
126159Sse/* 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2639231Sgibbs * $Id: pcivar.h,v 1.20 1998/08/13 19:12:20 gibbs Exp $ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 3139231Sgibbs#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#ifndef PCI_COMPAT 3439231Sgibbs#define PCI_COMPAT 3539231Sgibbs#endif 3639231Sgibbs 3739231Sgibbs#include <pci/pci_ioctl.h> /* XXX KDM */ 3839231Sgibbs#include <sys/queue.h> 3939231Sgibbs 4026159Sse/* some PCI bus constants */ 416767Sse 4226159Sse#define PCI_BUSMAX 255 /* highest supported bus number */ 4326159Sse#define PCI_SLOTMAX 31 /* highest supported slot number */ 4426159Sse#define PCI_FUNCMAX 7 /* highest supported function number */ 4526159Sse#define PCI_REGMAX 255 /* highest supported config register addr. */ 466100Sse 4726159Sse#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4826159Sse#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4926159Sse#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 506100Sse 5126159Sse/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 526100Sse 5326159Sse#ifdef PCI_A64 5426159Ssetypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5526159Sse#else 5626159Ssetypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5726159Sse#endif 586100Sse 5926159Sse/* map register information */ 607233Sse 6126159Ssetypedef struct { 6226159Sse u_int32_t base; 6326159Sse u_int8_t type; 6426159Sse#define PCI_MAPMEM 0x01 /* memory map */ 6526159Sse#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 6626159Sse#define PCI_MAPPORT 0x04 /* port map */ 6726159Sse u_int8_t ln2size; 6826159Sse u_int8_t ln2range; 6926159Sse/* u_int8_t dummy;*/ 7026159Sse} pcimap; 716100Sse 7226159Sse/* config header information common to all header types */ 736100Sse 7426159Ssetypedef struct pcicfg { 7526159Sse pcimap *map; /* pointer to array of PCI maps */ 7626159Sse void *hdrspec; /* pointer to header type specific data */ 776100Sse 7826159Sse u_int16_t subvendor; /* card vendor ID */ 7926159Sse u_int16_t subdevice; /* card device ID, assigned by card vendor */ 8026159Sse u_int16_t vendor; /* chip vendor ID */ 8126159Sse u_int16_t device; /* chip device ID, assigned by chip vendor */ 826100Sse 8326159Sse u_int16_t cmdreg; /* disable/enable chip and PCI options */ 8426159Sse u_int16_t statreg; /* supported PCI features and error state */ 857233Sse 8638304Sgibbs u_int8_t baseclass; /* chip PCI class */ 8726159Sse u_int8_t subclass; /* chip PCI subclass */ 8826159Sse u_int8_t progif; /* chip PCI programming interface */ 8926159Sse u_int8_t revid; /* chip revision ID */ 906100Sse 9126159Sse u_int8_t hdrtype; /* chip config header type */ 9226159Sse u_int8_t cachelnsz; /* cache line size in 4byte units */ 9326159Sse u_int8_t intpin; /* PCI interrupt pin */ 9426159Sse u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 956100Sse 9626159Sse u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 9726159Sse u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 9826159Sse u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 996100Sse 10026159Sse u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 10126159Sse u_int8_t nummaps; /* actual number of PCI maps used */ 1027233Sse 10326159Sse u_int8_t bus; /* config space bus address */ 10426159Sse u_int8_t slot; /* config space slot address */ 10526159Sse u_int8_t func; /* config space function number */ 1067233Sse 10726159Sse u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 10826159Sse u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 10926159Sse} pcicfgregs; 1106100Sse 11126159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 1126100Sse 11326159Sse#ifdef PCI_A64 11426159Sse#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 11526159Sse#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 11626159Sse#else 11726159Sse#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 11826159Sse#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 11926159Sse#endif /* PCI_A64 */ 1206100Sse 12126159Sse#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 12226159Sse#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1237233Sse 12426159Ssetypedef struct { 12526159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 12626159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 12726159Sse u_int32_t membase; /* base address of memory window */ 12826159Sse u_int32_t memlimit; /* topmost address of memory window */ 12926159Sse u_int32_t iobase; /* base address of port window */ 13026159Sse u_int32_t iolimit; /* topmost address of port window */ 13126159Sse u_int16_t secstat; /* secondary bus status register */ 13226159Sse u_int16_t bridgectl; /* bridge control register */ 13326159Sse u_int8_t seclat; /* CardBus latency timer */ 13426159Sse} pcih1cfgregs; 1356100Sse 13626159Sse/* additional type 2 device config header information (CardBus bridge) */ 13726159Sse 13826159Ssetypedef struct { 13926159Sse u_int32_t membase0; /* base address of memory window */ 14026159Sse u_int32_t memlimit0; /* topmost address of memory window */ 14126159Sse u_int32_t membase1; /* base address of memory window */ 14226159Sse u_int32_t memlimit1; /* topmost address of memory window */ 14326159Sse u_int32_t iobase0; /* base address of port window */ 14426159Sse u_int32_t iolimit0; /* topmost address of port window */ 14526159Sse u_int32_t iobase1; /* base address of port window */ 14626159Sse u_int32_t iolimit1; /* topmost address of port window */ 14726159Sse u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 14826159Sse u_int16_t secstat; /* secondary bus status register */ 14926159Sse u_int16_t bridgectl; /* bridge control register */ 15026159Sse u_int8_t seclat; /* CardBus latency timer */ 15126159Sse} pcih2cfgregs; 15226159Sse 15326159Sse/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 15426159Sse 15526159Ssetypedef struct pciattach { 15626159Sse int unit; 15726159Sse int pcibushigh; 15826159Sse struct pciattach *next; 15926159Sse} pciattach; 16026159Sse 16139231Sgibbsstruct pci_devinfo { 16239231Sgibbs STAILQ_ENTRY(pci_devinfo) pci_links; 16339231Sgibbs struct pci_device *device; /* should this be ifdefed? */ 16439231Sgibbs pcicfgregs cfg; 16539231Sgibbs struct pci_conf conf; 16639231Sgibbs}; 16739231Sgibbs 16839231Sgibbsextern u_int32_t pci_numdevs; 16939231Sgibbs 17039231Sgibbs 17126159Sse/* externally visible functions */ 17226159Sse 17326159Sseint pci_probe (pciattach *attach); 17439231Sgibbsvoid pci_drvattach(struct pci_devinfo *dinfo); 17526159Sse 17626159Sse/* low level PCI config register functions provided by pcibus.c */ 17726159Sse 17826159Sseint pci_cfgopen (void); 17926159Sseint pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 18026159Ssevoid pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 18126159Sse 18226159Sse/* for compatibility to FreeBSD-2.2 version of PCI code */ 18326159Sse 18426159Sse#ifdef PCI_COMPAT 18526159Sse 18626159Ssetypedef pcicfgregs *pcici_t; 18726159Ssetypedef unsigned pcidi_t; 18813597Ssetypedef void pci_inthand_t(void *arg); 18912453Sbde 19026159Sse#define pci_max_burst_len (3) 19126159Sse 19226159Sse/* just copied from old PCI code for now ... */ 19326159Sse 19426159Sseextern struct linker_set pcidevice_set; 19526159Sseextern int pci_mechanism; 19626159Sse 19726159Ssestruct pci_device { 19826159Sse char* pd_name; 19926159Sse char* (*pd_probe ) (pcici_t tag, pcidi_t type); 20026159Sse void (*pd_attach) (pcici_t tag, int unit); 20126159Sse u_long *pd_count; 20226159Sse int (*pd_shutdown) (int, int); 2037233Sse}; 2047233Sse 20526159Ssestruct pci_lkm { 20626159Sse struct pci_device *dvp; 20726159Sse struct pci_lkm *next; 20826159Sse}; 2096100Sse 21037841Sdfr#ifdef __i386__ 21137841Sdfrtypedef u_short pci_port_t; 21237841Sdfr#else 21337841Sdfrtypedef u_int pci_port_t; 21437841Sdfr#endif 21537841Sdfr 21626159Sseu_long pci_conf_read (pcici_t tag, u_long reg); 21726159Ssevoid pci_conf_write (pcici_t tag, u_long reg, u_long data); 21828517Sfsmpvoid pci_configure (void); 21937841Sdfrint pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 22026159Sseint pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 22126159Sseint pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr); 2227233Sseint pci_unmap_int (pcici_t tag); 22326159Sseint pci_register_lkm (struct pci_device *dvp, int if_revision); 2247233Sse 22526159Sse#endif /* PCI_COMPAT */ 22639231Sgibbs#endif /* _PCIVAR_H_ */ 227