pcivar.h revision 26159
126159Sse#ifndef PCI_COMPAT 226159Sse#define PCI_COMPAT 326159Sse#endif 426159Sse/* 526159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 626159Sse * All rights reserved. 726159Sse * 826159Sse * Redistribution and use in source and binary forms, with or without 926159Sse * modification, are permitted provided that the following conditions 1026159Sse * are met: 1126159Sse * 1. Redistributions of source code must retain the above copyright 1226159Sse * notice unmodified, this list of conditions, and the following 1326159Sse * disclaimer. 1426159Sse * 2. Redistributions in binary form must reproduce the above copyright 1526159Sse * notice, this list of conditions and the following disclaimer in the 1626159Sse * documentation and/or other materials provided with the distribution. 1726159Sse * 1826159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1926159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2026159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2126159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2226159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2326159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2426159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2526159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2626159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2726159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2826159Sse * 2926159Sse * $Id$ 3026159Sse * 3126159Sse */ 326100Sse 3326159Sse/* some PCI bus constants */ 346767Sse 3526159Sse#define PCI_BUSMAX 255 /* highest supported bus number */ 3626159Sse#define PCI_SLOTMAX 31 /* highest supported slot number */ 3726159Sse#define PCI_FUNCMAX 7 /* highest supported function number */ 3826159Sse#define PCI_REGMAX 255 /* highest supported config register addr. */ 396100Sse 4026159Sse#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4126159Sse#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4226159Sse#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 436100Sse 4426159Sse/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 456100Sse 4626159Sse#ifdef PCI_A64 4726159Ssetypedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 4826159Sse#else 4926159Ssetypedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 5026159Sse#endif 516100Sse 5226159Sse/* map register information */ 537233Sse 5426159Ssetypedef struct { 5526159Sse u_int32_t base; 5626159Sse u_int8_t type; 5726159Sse#define PCI_MAPMEM 0x01 /* memory map */ 5826159Sse#define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 5926159Sse#define PCI_MAPPORT 0x04 /* port map */ 6026159Sse u_int8_t ln2size; 6126159Sse u_int8_t ln2range; 6226159Sse/* u_int8_t dummy;*/ 6326159Sse} pcimap; 646100Sse 6526159Sse/* config header information common to all header types */ 666100Sse 6726159Ssetypedef struct pcicfg { 6826159Sse struct pcicfg *parent; 6926159Sse struct pcicfg *next; 7026159Sse pcimap *map; /* pointer to array of PCI maps */ 7126159Sse void *hdrspec; /* pointer to header type specific data */ 726100Sse 7326159Sse u_int16_t subvendor; /* card vendor ID */ 7426159Sse u_int16_t subdevice; /* card device ID, assigned by card vendor */ 7526159Sse u_int16_t vendor; /* chip vendor ID */ 7626159Sse u_int16_t device; /* chip device ID, assigned by chip vendor */ 776100Sse 7826159Sse u_int16_t cmdreg; /* disable/enable chip and PCI options */ 7926159Sse u_int16_t statreg; /* supported PCI features and error state */ 807233Sse 8126159Sse u_int8_t class; /* chip PCI class */ 8226159Sse u_int8_t subclass; /* chip PCI subclass */ 8326159Sse u_int8_t progif; /* chip PCI programming interface */ 8426159Sse u_int8_t revid; /* chip revision ID */ 856100Sse 8626159Sse u_int8_t hdrtype; /* chip config header type */ 8726159Sse u_int8_t cachelnsz; /* cache line size in 4byte units */ 8826159Sse u_int8_t intpin; /* PCI interrupt pin */ 8926159Sse u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 906100Sse 9126159Sse u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 9226159Sse u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 9326159Sse u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 946100Sse 9526159Sse u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 9626159Sse u_int8_t nummaps; /* actual number of PCI maps used */ 977233Sse 9826159Sse u_int8_t bus; /* config space bus address */ 9926159Sse u_int8_t slot; /* config space slot address */ 10026159Sse u_int8_t func; /* config space function number */ 1017233Sse 10226159Sse u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 10326159Sse u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 10426159Sse} pcicfgregs; 1056100Sse 10626159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 1076100Sse 10826159Sse#ifdef PCI_A64 10926159Sse#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 11026159Sse#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 11126159Sse#else 11226159Sse#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 11326159Sse#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 11426159Sse#endif /* PCI_A64 */ 1156100Sse 11626159Sse#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 11726159Sse#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1187233Sse 11926159Ssetypedef struct { 12026159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 12126159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 12226159Sse u_int32_t membase; /* base address of memory window */ 12326159Sse u_int32_t memlimit; /* topmost address of memory window */ 12426159Sse u_int32_t iobase; /* base address of port window */ 12526159Sse u_int32_t iolimit; /* topmost address of port window */ 12626159Sse u_int16_t secstat; /* secondary bus status register */ 12726159Sse u_int16_t bridgectl; /* bridge control register */ 12826159Sse u_int8_t seclat; /* CardBus latency timer */ 12926159Sse} pcih1cfgregs; 1306100Sse 13126159Sse/* additional type 2 device config header information (CardBus bridge) */ 13226159Sse 13326159Ssetypedef struct { 13426159Sse u_int32_t membase0; /* base address of memory window */ 13526159Sse u_int32_t memlimit0; /* topmost address of memory window */ 13626159Sse u_int32_t membase1; /* base address of memory window */ 13726159Sse u_int32_t memlimit1; /* topmost address of memory window */ 13826159Sse u_int32_t iobase0; /* base address of port window */ 13926159Sse u_int32_t iolimit0; /* topmost address of port window */ 14026159Sse u_int32_t iobase1; /* base address of port window */ 14126159Sse u_int32_t iolimit1; /* topmost address of port window */ 14226159Sse u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 14326159Sse u_int16_t secstat; /* secondary bus status register */ 14426159Sse u_int16_t bridgectl; /* bridge control register */ 14526159Sse u_int8_t seclat; /* CardBus latency timer */ 14626159Sse} pcih2cfgregs; 14726159Sse 14826159Sse/* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 14926159Sse 15026159Ssetypedef struct pciattach { 15126159Sse int unit; 15226159Sse int pcibushigh; 15326159Sse struct pciattach *next; 15426159Sse} pciattach; 15526159Sse 15626159Sse/* externally visible functions */ 15726159Sse 15826159Sseint pci_probe (pciattach *attach); 15926159Ssevoid pci_drvattach(pcicfgregs *cfg); 16026159Sse 16126159Sse/* low level PCI config register functions provided by pcibus.c */ 16226159Sse 16326159Sseint pci_cfgopen (void); 16426159Sseint pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 16526159Ssevoid pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 16626159Sse 16726159Sse/* for compatibility to FreeBSD-2.2 version of PCI code */ 16826159Sse 16926159Sse#ifdef PCI_COMPAT 17026159Sse 17126159Ssetypedef pcicfgregs *pcici_t; 17226159Ssetypedef unsigned pcidi_t; 17313597Ssetypedef void pci_inthand_t(void *arg); 17412453Sbde 17526159Sse#define pci_max_burst_len (3) 17626159Sse 17726159Sse/* just copied from old PCI code for now ... */ 17826159Sse 17926159Sseextern struct linker_set pcidevice_set; 18026159Sseextern int pci_mechanism; 18126159Sse 18226159Ssestruct pci_device { 18326159Sse char* pd_name; 18426159Sse char* (*pd_probe ) (pcici_t tag, pcidi_t type); 18526159Sse void (*pd_attach) (pcici_t tag, int unit); 18626159Sse u_long *pd_count; 18726159Sse int (*pd_shutdown) (int, int); 1887233Sse}; 1897233Sse 19026159Ssestruct pci_lkm { 19126159Sse struct pci_device *dvp; 19226159Sse struct pci_lkm *next; 19326159Sse}; 1946100Sse 19526159Sseu_long pci_conf_read (pcici_t tag, u_long reg); 19626159Ssevoid pci_conf_write (pcici_t tag, u_long reg, u_long data); 19726159Sseint pci_map_port (pcici_t tag, u_long reg, u_short* pa); 19826159Sseint pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 19926159Sseint pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr); 2007233Sseint pci_unmap_int (pcici_t tag); 20126159Sseint pci_register_lkm (struct pci_device *dvp, int if_revision); 2027233Sse 20326159Sse#endif /* PCI_COMPAT */ 204