pcivar.h revision 253273
1139749Simp/*- 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2650477Speter * $FreeBSD: stable/9/sys/dev/pci/pcivar.h 253273 2013-07-12 16:41:58Z marius $ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 31165217Sjhb#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#include <sys/queue.h> 3439231Sgibbs 3526159Sse/* some PCI bus constants */ 36165217Sjhb#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37165217Sjhb#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38165217Sjhb#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 396100Sse 40163805Simptypedef uint64_t pci_addr_t; 416100Sse 42120063Sscottl/* Interesting values for PCI power management */ 43120063Sscottlstruct pcicfg_pp { 44120063Sscottl uint16_t pp_cap; /* PCI power management capabilities */ 45214122Sjkim uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46214122Sjkim uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47214122Sjkim uint8_t pp_data; /* conf. space addr. of PM data reg */ 48120063Sscottl}; 49220195Sjhb 50220195Sjhbstruct pci_map { 51220195Sjhb pci_addr_t pm_value; /* Raw BAR value */ 52220195Sjhb pci_addr_t pm_size; 53220195Sjhb uint8_t pm_reg; 54220195Sjhb STAILQ_ENTRY(pci_map) pm_link; 55220195Sjhb}; 56220195Sjhb 57163163Sjmgstruct vpd_readonly { 58163163Sjmg char keyword[2]; 59163163Sjmg char *value; 60163163Sjmg}; 61163163Sjmg 62163163Sjmgstruct vpd_write { 63163163Sjmg char keyword[2]; 64163163Sjmg char *value; 65163163Sjmg int start; 66163163Sjmg int len; 67163163Sjmg}; 68163163Sjmg 69163163Sjmgstruct pcicfg_vpd { 70163163Sjmg uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 71167909Sjhb char vpd_cached; 72163163Sjmg char *vpd_ident; /* string identifier */ 73163163Sjmg int vpd_rocnt; 74163163Sjmg struct vpd_readonly *vpd_ros; 75163163Sjmg int vpd_wcnt; 76163163Sjmg struct vpd_write *vpd_w; 77163163Sjmg}; 78163163Sjmg 79120063Sscottl/* Interesting values for PCI MSI */ 80120063Sscottlstruct pcicfg_msi { 81120063Sscottl uint16_t msi_ctrl; /* Message Control */ 82164264Sjhb uint8_t msi_location; /* Offset of MSI capability registers. */ 83120063Sscottl uint8_t msi_msgnum; /* Number of messages */ 84164264Sjhb int msi_alloc; /* Number of allocated messages. */ 85164264Sjhb uint64_t msi_addr; /* Contents of address register. */ 86164264Sjhb uint16_t msi_data; /* Contents of data register. */ 87169221Sjhb u_int msi_handlers; 88120063Sscottl}; 89120063Sscottl 90164282Sjhb/* Interesting values for PCI MSI-X */ 91169221Sjhbstruct msix_vector { 92169221Sjhb uint64_t mv_address; /* Contents of address register. */ 93169221Sjhb uint32_t mv_data; /* Contents of data register. */ 94169221Sjhb int mv_irq; 95169221Sjhb}; 96169221Sjhb 97169221Sjhbstruct msix_table_entry { 98169221Sjhb u_int mte_vector; /* 1-based index into msix_vectors array. */ 99169221Sjhb u_int mte_handlers; 100169221Sjhb}; 101169221Sjhb 102164264Sjhbstruct pcicfg_msix { 103164264Sjhb uint16_t msix_ctrl; /* Message Control */ 104169221Sjhb uint16_t msix_msgnum; /* Number of messages */ 105164282Sjhb uint8_t msix_location; /* Offset of MSI-X capability registers. */ 106164264Sjhb uint8_t msix_table_bar; /* BAR containing vector table. */ 107164264Sjhb uint8_t msix_pba_bar; /* BAR containing PBA. */ 108164264Sjhb uint32_t msix_table_offset; 109164264Sjhb uint32_t msix_pba_offset; 110169221Sjhb int msix_alloc; /* Number of allocated vectors. */ 111169221Sjhb int msix_table_len; /* Length of virtual table. */ 112169221Sjhb struct msix_table_entry *msix_table; /* Virtual table. */ 113169221Sjhb struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 114164264Sjhb struct resource *msix_table_res; /* Resource containing vector table. */ 115164264Sjhb struct resource *msix_pba_res; /* Resource containing PBA. */ 116164264Sjhb}; 117164264Sjhb 118180753Sluoqi/* Interesting values for HyperTransport */ 119180753Sluoqistruct pcicfg_ht { 120219737Sjhb uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 121180753Sluoqi uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 122180753Sluoqi uint16_t ht_msictrl; /* MSI mapping control */ 123180753Sluoqi uint64_t ht_msiaddr; /* MSI mapping base address */ 124180753Sluoqi}; 125180753Sluoqi 12626159Sse/* config header information common to all header types */ 12726159Ssetypedef struct pcicfg { 12845720Speter struct device *dev; /* device which owns this */ 1296100Sse 130220195Sjhb STAILQ_HEAD(, pci_map) maps; /* BARs */ 131128019Simp 132119266Simp uint16_t subvendor; /* card vendor ID */ 133119266Simp uint16_t subdevice; /* card device ID, assigned by card vendor */ 134119266Simp uint16_t vendor; /* chip vendor ID */ 135119266Simp uint16_t device; /* chip device ID, assigned by chip vendor */ 1366100Sse 137119266Simp uint16_t cmdreg; /* disable/enable chip and PCI options */ 138119266Simp uint16_t statreg; /* supported PCI features and error state */ 1397233Sse 140119266Simp uint8_t baseclass; /* chip PCI class */ 141119266Simp uint8_t subclass; /* chip PCI subclass */ 142119266Simp uint8_t progif; /* chip PCI programming interface */ 143119266Simp uint8_t revid; /* chip revision ID */ 1446100Sse 145119266Simp uint8_t hdrtype; /* chip config header type */ 146119266Simp uint8_t cachelnsz; /* cache line size in 4byte units */ 147119266Simp uint8_t intpin; /* PCI interrupt pin */ 148119266Simp uint8_t intline; /* interrupt line (IRQ for PC arch) */ 1496100Sse 150119266Simp uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 151119266Simp uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 152119266Simp uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 1536100Sse 154119266Simp uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 155119266Simp uint8_t nummaps; /* actual number of PCI maps used */ 1567233Sse 157172394Smarius uint32_t domain; /* PCI domain */ 158119266Simp uint8_t bus; /* config space bus address */ 159119266Simp uint8_t slot; /* config space slot address */ 160119266Simp uint8_t func; /* config space function number */ 1617233Sse 162193256Sjhb struct pcicfg_pp pp; /* Power management */ 163193256Sjhb struct pcicfg_vpd vpd; /* Vital product data */ 164193256Sjhb struct pcicfg_msi msi; /* PCI MSI */ 165193256Sjhb struct pcicfg_msix msix; /* PCI MSI-X */ 166180753Sluoqi struct pcicfg_ht ht; /* HyperTransport */ 16726159Sse} pcicfgregs; 1686100Sse 16926159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 1706100Sse 171165217Sjhb#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 172165217Sjhb#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 173165217Sjhb#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 174165217Sjhb#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1757233Sse 17626159Ssetypedef struct { 17726159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 17826159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 179119266Simp uint32_t membase; /* base address of memory window */ 180119266Simp uint32_t memlimit; /* topmost address of memory window */ 181119266Simp uint32_t iobase; /* base address of port window */ 182119266Simp uint32_t iolimit; /* topmost address of port window */ 183119266Simp uint16_t secstat; /* secondary bus status register */ 184119266Simp uint16_t bridgectl; /* bridge control register */ 185119266Simp uint8_t seclat; /* CardBus latency timer */ 18626159Sse} pcih1cfgregs; 1876100Sse 18826159Sse/* additional type 2 device config header information (CardBus bridge) */ 18926159Sse 19026159Ssetypedef struct { 191119266Simp uint32_t membase0; /* base address of memory window */ 192119266Simp uint32_t memlimit0; /* topmost address of memory window */ 193119266Simp uint32_t membase1; /* base address of memory window */ 194119266Simp uint32_t memlimit1; /* topmost address of memory window */ 195119266Simp uint32_t iobase0; /* base address of port window */ 196119266Simp uint32_t iolimit0; /* topmost address of port window */ 197119266Simp uint32_t iobase1; /* base address of port window */ 198119266Simp uint32_t iolimit1; /* topmost address of port window */ 199119266Simp uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 200119266Simp uint16_t secstat; /* secondary bus status register */ 201119266Simp uint16_t bridgectl; /* bridge control register */ 202119266Simp uint8_t seclat; /* CardBus latency timer */ 20326159Sse} pcih2cfgregs; 20426159Sse 205119266Simpextern uint32_t pci_numdevs; 20639231Sgibbs 20761047Speter/* Only if the prerequisites are present */ 20861047Speter#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 20961047Speterstruct pci_devinfo { 21061047Speter STAILQ_ENTRY(pci_devinfo) pci_links; 21161047Speter struct resource_list resources; 21261047Speter pcicfgregs cfg; 21361047Speter struct pci_conf conf; 21461047Speter}; 21561047Speter#endif 21639231Sgibbs 21745720Speter#ifdef _SYS_BUS_H_ 21845720Speter 21945720Speter#include "pci_if.h" 22045720Speter 22145720Speterenum pci_device_ivars { 22269953Smsmith PCI_IVAR_SUBVENDOR, 22369953Smsmith PCI_IVAR_SUBDEVICE, 22469953Smsmith PCI_IVAR_VENDOR, 22569953Smsmith PCI_IVAR_DEVICE, 22669953Smsmith PCI_IVAR_DEVID, 22769953Smsmith PCI_IVAR_CLASS, 22869953Smsmith PCI_IVAR_SUBCLASS, 22969953Smsmith PCI_IVAR_PROGIF, 23069953Smsmith PCI_IVAR_REVID, 23169953Smsmith PCI_IVAR_INTPIN, 23269953Smsmith PCI_IVAR_IRQ, 233172394Smarius PCI_IVAR_DOMAIN, 23469953Smsmith PCI_IVAR_BUS, 23569953Smsmith PCI_IVAR_SLOT, 23669953Smsmith PCI_IVAR_FUNCTION, 237107300Simp PCI_IVAR_ETHADDR, 238149972Simp PCI_IVAR_CMDREG, 239149972Simp PCI_IVAR_CACHELNSZ, 240149972Simp PCI_IVAR_MINGNT, 241149972Simp PCI_IVAR_MAXLAT, 242178161Sphk PCI_IVAR_LATTIMER 24345720Speter}; 24445720Speter 24545720Speter/* 24645720Speter * Simplified accessors for pci devices 24745720Speter */ 248165217Sjhb#define PCI_ACCESSOR(var, ivar, type) \ 24988375Stmm __BUS_ACCESSOR(pci, var, PCI, ivar, type) 25045720Speter 251119266SimpPCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 252119266SimpPCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 253119266SimpPCI_ACCESSOR(vendor, VENDOR, uint16_t) 254119266SimpPCI_ACCESSOR(device, DEVICE, uint16_t) 255119266SimpPCI_ACCESSOR(devid, DEVID, uint32_t) 256119266SimpPCI_ACCESSOR(class, CLASS, uint8_t) 257119266SimpPCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 258119266SimpPCI_ACCESSOR(progif, PROGIF, uint8_t) 259119266SimpPCI_ACCESSOR(revid, REVID, uint8_t) 260119266SimpPCI_ACCESSOR(intpin, INTPIN, uint8_t) 261119266SimpPCI_ACCESSOR(irq, IRQ, uint8_t) 262172394SmariusPCI_ACCESSOR(domain, DOMAIN, uint32_t) 263119266SimpPCI_ACCESSOR(bus, BUS, uint8_t) 264119266SimpPCI_ACCESSOR(slot, SLOT, uint8_t) 265119266SimpPCI_ACCESSOR(function, FUNCTION, uint8_t) 266119266SimpPCI_ACCESSOR(ether, ETHADDR, uint8_t *) 267149972SimpPCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 268149972SimpPCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 269149972SimpPCI_ACCESSOR(mingnt, MINGNT, uint8_t) 270149972SimpPCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 271149972SimpPCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 27245720Speter 27366416Speter#undef PCI_ACCESSOR 27466416Speter 27569953Smsmith/* 27669953Smsmith * Operations on configuration space. 27769953Smsmith */ 278119266Simpstatic __inline uint32_t 27945720Speterpci_read_config(device_t dev, int reg, int width) 28045720Speter{ 28145720Speter return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 28245720Speter} 28345720Speter 28445720Speterstatic __inline void 285119266Simppci_write_config(device_t dev, int reg, uint32_t val, int width) 28645720Speter{ 28745720Speter PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 28845720Speter} 28945720Speter 29047339Sgallatin/* 29147339Sgallatin * Ivars for pci bridges. 29247339Sgallatin */ 29347339Sgallatin 29447339Sgallatin/*typedef enum pci_device_ivars pcib_device_ivars;*/ 29547339Sgallatinenum pcib_device_ivars { 296172394Smarius PCIB_IVAR_DOMAIN, 29765176Sdfr PCIB_IVAR_BUS 29847339Sgallatin}; 29947339Sgallatin 300165217Sjhb#define PCIB_ACCESSOR(var, ivar, type) \ 301102144Smux __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 30247339Sgallatin 303172394SmariusPCIB_ACCESSOR(domain, DOMAIN, uint32_t) 304119266SimpPCIB_ACCESSOR(bus, BUS, uint32_t) 30547339Sgallatin 30666416Speter#undef PCIB_ACCESSOR 30766416Speter 30869953Smsmith/* 30998017Simp * PCI interrupt validation. Invalid interrupt values such as 0 or 128 31098017Simp * on i386 or other platforms should be mapped out in the MD pcireadconf 31198017Simp * code and not here, since the only MI invalid IRQ is 255. 31290554Smsmith */ 313165217Sjhb#define PCI_INVALID_IRQ 255 314165217Sjhb#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 31590554Smsmith 31690554Smsmith/* 31769953Smsmith * Convenience functions. 31869953Smsmith * 31969953Smsmith * These should be used in preference to manually manipulating 32069953Smsmith * configuration space. 32169953Smsmith */ 322113544Smdoddstatic __inline int 32373185Speterpci_enable_busmaster(device_t dev) 32473185Speter{ 325113544Smdodd return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 32673185Speter} 32745720Speter 328113544Smdoddstatic __inline int 32973185Speterpci_disable_busmaster(device_t dev) 33073185Speter{ 331113544Smdodd return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 33273185Speter} 33373185Speter 334113544Smdoddstatic __inline int 33573185Speterpci_enable_io(device_t dev, int space) 33673185Speter{ 337113544Smdodd return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 33873185Speter} 33973185Speter 340113544Smdoddstatic __inline int 34173185Speterpci_disable_io(device_t dev, int space) 34273185Speter{ 343113544Smdodd return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 34473185Speter} 34573185Speter 346163163Sjmgstatic __inline int 347163163Sjmgpci_get_vpd_ident(device_t dev, const char **identptr) 348163163Sjmg{ 349163163Sjmg return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 350163163Sjmg} 351163163Sjmg 352163163Sjmgstatic __inline int 353163163Sjmgpci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 354163163Sjmg{ 355163163Sjmg return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 356163163Sjmg} 357163163Sjmg 35869953Smsmith/* 359145651Smarcel * Check if the address range falls within the VGA defined address range(s) 360145651Smarcel */ 361145651Smarcelstatic __inline int 362145651Smarcelpci_is_vga_ioport_range(u_long start, u_long end) 363145651Smarcel{ 364145651Smarcel 365145651Smarcel return (((start >= 0x3b0 && end <= 0x3bb) || 366145651Smarcel (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 367145651Smarcel} 368145651Smarcel 369145651Smarcelstatic __inline int 370145651Smarcelpci_is_vga_memory_range(u_long start, u_long end) 371145651Smarcel{ 372145651Smarcel 373145651Smarcel return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 374145651Smarcel} 375145651Smarcel 376145651Smarcel/* 37769953Smsmith * PCI power states are as defined by ACPI: 37869953Smsmith * 37969953Smsmith * D0 State in which device is on and running. It is receiving full 38069953Smsmith * power from the system and delivering full functionality to the user. 38169953Smsmith * D1 Class-specific low-power state in which device context may or may not 38269953Smsmith * be lost. Buses in D1 cannot do anything to the bus that would force 383160964Syar * devices on that bus to lose context. 38469953Smsmith * D2 Class-specific low-power state in which device context may or may 38569953Smsmith * not be lost. Attains greater power savings than D1. Buses in D2 386160964Syar * can cause devices on that bus to lose some context. Devices in D2 38769953Smsmith * must be prepared for the bus to be in D2 or higher. 38869953Smsmith * D3 State in which the device is off and not running. Device context is 38969953Smsmith * lost. Power can be removed from the device. 39069953Smsmith */ 391165217Sjhb#define PCI_POWERSTATE_D0 0 392165217Sjhb#define PCI_POWERSTATE_D1 1 393165217Sjhb#define PCI_POWERSTATE_D2 2 394165217Sjhb#define PCI_POWERSTATE_D3 3 395165217Sjhb#define PCI_POWERSTATE_UNKNOWN -1 39626159Sse 39773185Speterstatic __inline int 39873185Speterpci_set_powerstate(device_t dev, int state) 39973185Speter{ 40073185Speter return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 40173185Speter} 40258287Speter 40373185Speterstatic __inline int 40473185Speterpci_get_powerstate(device_t dev) 40573185Speter{ 40673185Speter return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 40773185Speter} 40873185Speter 409153560Sjhbstatic __inline int 410219865Sjhbpci_find_cap(device_t dev, int capability, int *capreg) 411219865Sjhb{ 412219865Sjhb return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 413219865Sjhb} 414219865Sjhb 415219865Sjhbstatic __inline int 416153560Sjhbpci_find_extcap(device_t dev, int capability, int *capreg) 417153560Sjhb{ 418219865Sjhb return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 419153560Sjhb} 420153560Sjhb 421164264Sjhbstatic __inline int 422164264Sjhbpci_alloc_msi(device_t dev, int *count) 423164264Sjhb{ 424164264Sjhb return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 425164264Sjhb} 426164264Sjhb 427164264Sjhbstatic __inline int 428166176Sjhbpci_alloc_msix(device_t dev, int *count) 429166176Sjhb{ 430166176Sjhb return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 431166176Sjhb} 432166176Sjhb 433166176Sjhbstatic __inline int 434169221Sjhbpci_remap_msix(device_t dev, int count, const u_int *vectors) 435166176Sjhb{ 436169221Sjhb return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 437166176Sjhb} 438166176Sjhb 439166176Sjhbstatic __inline int 440164264Sjhbpci_release_msi(device_t dev) 441164264Sjhb{ 442164264Sjhb return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 443164264Sjhb} 444164264Sjhb 445164264Sjhbstatic __inline int 446164264Sjhbpci_msi_count(device_t dev) 447164264Sjhb{ 448164264Sjhb return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 449164264Sjhb} 450164264Sjhb 451166176Sjhbstatic __inline int 452166176Sjhbpci_msix_count(device_t dev) 453166176Sjhb{ 454166176Sjhb return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 455166176Sjhb} 456166176Sjhb 457119266Simpdevice_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 458172394Smariusdevice_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 459119266Simpdevice_t pci_find_device(uint16_t, uint16_t); 460223885Skibdevice_t pci_find_class(uint8_t class, uint8_t subclass); 461164264Sjhb 462169221Sjhb/* Can be used by drivers to manage the MSI-X table. */ 463164264Sjhbint pci_pending_msix(device_t dev, u_int index); 464169221Sjhb 465165228Sjhbint pci_msi_device_blacklisted(device_t dev); 466253273Smariusint pci_msix_device_blacklisted(device_t dev); 467164264Sjhb 468180753Sluoqivoid pci_ht_map_msi(device_t dev, uint64_t addr); 469180753Sluoqi 470203528Smavint pci_get_max_read_req(device_t dev); 471233379Sjhbvoid pci_restore_state(device_t dev); 472233379Sjhbvoid pci_save_state(device_t dev); 473203528Smavint pci_set_max_read_req(device_t dev, int size); 474203528Smav 47569953Smsmith#endif /* _SYS_BUS_H_ */ 47661047Speter 47769953Smsmith/* 47869953Smsmith * cdev switch for control device, initialised in generic PCI code 47969953Smsmith */ 48069953Smsmithextern struct cdevsw pcicdev; 48158287Speter 48269953Smsmith/* 48369953Smsmith * List of all PCI devices, generation count for the list. 48469953Smsmith */ 48588184SmdoddSTAILQ_HEAD(devlist, pci_devinfo); 48612453Sbde 48788184Smdoddextern struct devlist pci_devq; 488119266Simpextern uint32_t pci_generation; 48988184Smdodd 490220195Sjhbstruct pci_map *pci_find_bar(device_t dev, int reg); 491220195Sjhbint pci_bar_enabled(device_t dev, struct pci_map *pm); 492220195Sjhb 49339231Sgibbs#endif /* _PCIVAR_H_ */ 494