pcivar.h revision 219865
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 219865 2011-03-22 12:05:49Z jhb $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40typedef uint64_t pci_addr_t; 41 42/* Interesting values for PCI power management */ 43struct pcicfg_pp { 44 uint16_t pp_cap; /* PCI power management capabilities */ 45 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47 uint8_t pp_data; /* conf. space addr. of PM data reg */ 48}; 49 50struct vpd_readonly { 51 char keyword[2]; 52 char *value; 53}; 54 55struct vpd_write { 56 char keyword[2]; 57 char *value; 58 int start; 59 int len; 60}; 61 62struct pcicfg_vpd { 63 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 64 char vpd_cached; 65 char *vpd_ident; /* string identifier */ 66 int vpd_rocnt; 67 struct vpd_readonly *vpd_ros; 68 int vpd_wcnt; 69 struct vpd_write *vpd_w; 70}; 71 72/* Interesting values for PCI MSI */ 73struct pcicfg_msi { 74 uint16_t msi_ctrl; /* Message Control */ 75 uint8_t msi_location; /* Offset of MSI capability registers. */ 76 uint8_t msi_msgnum; /* Number of messages */ 77 int msi_alloc; /* Number of allocated messages. */ 78 uint64_t msi_addr; /* Contents of address register. */ 79 uint16_t msi_data; /* Contents of data register. */ 80 u_int msi_handlers; 81}; 82 83/* Interesting values for PCI MSI-X */ 84struct msix_vector { 85 uint64_t mv_address; /* Contents of address register. */ 86 uint32_t mv_data; /* Contents of data register. */ 87 int mv_irq; 88}; 89 90struct msix_table_entry { 91 u_int mte_vector; /* 1-based index into msix_vectors array. */ 92 u_int mte_handlers; 93}; 94 95struct pcicfg_msix { 96 uint16_t msix_ctrl; /* Message Control */ 97 uint16_t msix_msgnum; /* Number of messages */ 98 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 99 uint8_t msix_table_bar; /* BAR containing vector table. */ 100 uint8_t msix_pba_bar; /* BAR containing PBA. */ 101 uint32_t msix_table_offset; 102 uint32_t msix_pba_offset; 103 int msix_alloc; /* Number of allocated vectors. */ 104 int msix_table_len; /* Length of virtual table. */ 105 struct msix_table_entry *msix_table; /* Virtual table. */ 106 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 107 struct resource *msix_table_res; /* Resource containing vector table. */ 108 struct resource *msix_pba_res; /* Resource containing PBA. */ 109}; 110 111/* Interesting values for HyperTransport */ 112struct pcicfg_ht { 113 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 114 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 115 uint16_t ht_msictrl; /* MSI mapping control */ 116 uint64_t ht_msiaddr; /* MSI mapping base address */ 117}; 118 119/* config header information common to all header types */ 120typedef struct pcicfg { 121 struct device *dev; /* device which owns this */ 122 123 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 124 uint32_t bios; /* BIOS mapping */ 125 126 uint16_t subvendor; /* card vendor ID */ 127 uint16_t subdevice; /* card device ID, assigned by card vendor */ 128 uint16_t vendor; /* chip vendor ID */ 129 uint16_t device; /* chip device ID, assigned by chip vendor */ 130 131 uint16_t cmdreg; /* disable/enable chip and PCI options */ 132 uint16_t statreg; /* supported PCI features and error state */ 133 134 uint8_t baseclass; /* chip PCI class */ 135 uint8_t subclass; /* chip PCI subclass */ 136 uint8_t progif; /* chip PCI programming interface */ 137 uint8_t revid; /* chip revision ID */ 138 139 uint8_t hdrtype; /* chip config header type */ 140 uint8_t cachelnsz; /* cache line size in 4byte units */ 141 uint8_t intpin; /* PCI interrupt pin */ 142 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 143 144 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 145 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 146 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 147 148 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 149 uint8_t nummaps; /* actual number of PCI maps used */ 150 151 uint32_t domain; /* PCI domain */ 152 uint8_t bus; /* config space bus address */ 153 uint8_t slot; /* config space slot address */ 154 uint8_t func; /* config space function number */ 155 156 struct pcicfg_pp pp; /* Power management */ 157 struct pcicfg_vpd vpd; /* Vital product data */ 158 struct pcicfg_msi msi; /* PCI MSI */ 159 struct pcicfg_msix msix; /* PCI MSI-X */ 160 struct pcicfg_ht ht; /* HyperTransport */ 161} pcicfgregs; 162 163/* additional type 1 device config header information (PCI to PCI bridge) */ 164 165#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 166#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 167#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 168#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 169 170typedef struct { 171 pci_addr_t pmembase; /* base address of prefetchable memory */ 172 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 173 uint32_t membase; /* base address of memory window */ 174 uint32_t memlimit; /* topmost address of memory window */ 175 uint32_t iobase; /* base address of port window */ 176 uint32_t iolimit; /* topmost address of port window */ 177 uint16_t secstat; /* secondary bus status register */ 178 uint16_t bridgectl; /* bridge control register */ 179 uint8_t seclat; /* CardBus latency timer */ 180} pcih1cfgregs; 181 182/* additional type 2 device config header information (CardBus bridge) */ 183 184typedef struct { 185 uint32_t membase0; /* base address of memory window */ 186 uint32_t memlimit0; /* topmost address of memory window */ 187 uint32_t membase1; /* base address of memory window */ 188 uint32_t memlimit1; /* topmost address of memory window */ 189 uint32_t iobase0; /* base address of port window */ 190 uint32_t iolimit0; /* topmost address of port window */ 191 uint32_t iobase1; /* base address of port window */ 192 uint32_t iolimit1; /* topmost address of port window */ 193 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 194 uint16_t secstat; /* secondary bus status register */ 195 uint16_t bridgectl; /* bridge control register */ 196 uint8_t seclat; /* CardBus latency timer */ 197} pcih2cfgregs; 198 199extern uint32_t pci_numdevs; 200 201/* Only if the prerequisites are present */ 202#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 203struct pci_devinfo { 204 STAILQ_ENTRY(pci_devinfo) pci_links; 205 struct resource_list resources; 206 pcicfgregs cfg; 207 struct pci_conf conf; 208}; 209#endif 210 211#ifdef _SYS_BUS_H_ 212 213#include "pci_if.h" 214 215enum pci_device_ivars { 216 PCI_IVAR_SUBVENDOR, 217 PCI_IVAR_SUBDEVICE, 218 PCI_IVAR_VENDOR, 219 PCI_IVAR_DEVICE, 220 PCI_IVAR_DEVID, 221 PCI_IVAR_CLASS, 222 PCI_IVAR_SUBCLASS, 223 PCI_IVAR_PROGIF, 224 PCI_IVAR_REVID, 225 PCI_IVAR_INTPIN, 226 PCI_IVAR_IRQ, 227 PCI_IVAR_DOMAIN, 228 PCI_IVAR_BUS, 229 PCI_IVAR_SLOT, 230 PCI_IVAR_FUNCTION, 231 PCI_IVAR_ETHADDR, 232 PCI_IVAR_CMDREG, 233 PCI_IVAR_CACHELNSZ, 234 PCI_IVAR_MINGNT, 235 PCI_IVAR_MAXLAT, 236 PCI_IVAR_LATTIMER 237}; 238 239/* 240 * Simplified accessors for pci devices 241 */ 242#define PCI_ACCESSOR(var, ivar, type) \ 243 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 244 245PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 246PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 247PCI_ACCESSOR(vendor, VENDOR, uint16_t) 248PCI_ACCESSOR(device, DEVICE, uint16_t) 249PCI_ACCESSOR(devid, DEVID, uint32_t) 250PCI_ACCESSOR(class, CLASS, uint8_t) 251PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 252PCI_ACCESSOR(progif, PROGIF, uint8_t) 253PCI_ACCESSOR(revid, REVID, uint8_t) 254PCI_ACCESSOR(intpin, INTPIN, uint8_t) 255PCI_ACCESSOR(irq, IRQ, uint8_t) 256PCI_ACCESSOR(domain, DOMAIN, uint32_t) 257PCI_ACCESSOR(bus, BUS, uint8_t) 258PCI_ACCESSOR(slot, SLOT, uint8_t) 259PCI_ACCESSOR(function, FUNCTION, uint8_t) 260PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 261PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 262PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 263PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 264PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 265PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 266 267#undef PCI_ACCESSOR 268 269/* 270 * Operations on configuration space. 271 */ 272static __inline uint32_t 273pci_read_config(device_t dev, int reg, int width) 274{ 275 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 276} 277 278static __inline void 279pci_write_config(device_t dev, int reg, uint32_t val, int width) 280{ 281 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 282} 283 284/* 285 * Ivars for pci bridges. 286 */ 287 288/*typedef enum pci_device_ivars pcib_device_ivars;*/ 289enum pcib_device_ivars { 290 PCIB_IVAR_DOMAIN, 291 PCIB_IVAR_BUS 292}; 293 294#define PCIB_ACCESSOR(var, ivar, type) \ 295 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 296 297PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 298PCIB_ACCESSOR(bus, BUS, uint32_t) 299 300#undef PCIB_ACCESSOR 301 302/* 303 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 304 * on i386 or other platforms should be mapped out in the MD pcireadconf 305 * code and not here, since the only MI invalid IRQ is 255. 306 */ 307#define PCI_INVALID_IRQ 255 308#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 309 310/* 311 * Convenience functions. 312 * 313 * These should be used in preference to manually manipulating 314 * configuration space. 315 */ 316static __inline int 317pci_enable_busmaster(device_t dev) 318{ 319 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 320} 321 322static __inline int 323pci_disable_busmaster(device_t dev) 324{ 325 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 326} 327 328static __inline int 329pci_enable_io(device_t dev, int space) 330{ 331 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 332} 333 334static __inline int 335pci_disable_io(device_t dev, int space) 336{ 337 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 338} 339 340static __inline int 341pci_get_vpd_ident(device_t dev, const char **identptr) 342{ 343 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 344} 345 346static __inline int 347pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 348{ 349 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 350} 351 352/* 353 * Check if the address range falls within the VGA defined address range(s) 354 */ 355static __inline int 356pci_is_vga_ioport_range(u_long start, u_long end) 357{ 358 359 return (((start >= 0x3b0 && end <= 0x3bb) || 360 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 361} 362 363static __inline int 364pci_is_vga_memory_range(u_long start, u_long end) 365{ 366 367 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 368} 369 370/* 371 * PCI power states are as defined by ACPI: 372 * 373 * D0 State in which device is on and running. It is receiving full 374 * power from the system and delivering full functionality to the user. 375 * D1 Class-specific low-power state in which device context may or may not 376 * be lost. Buses in D1 cannot do anything to the bus that would force 377 * devices on that bus to lose context. 378 * D2 Class-specific low-power state in which device context may or may 379 * not be lost. Attains greater power savings than D1. Buses in D2 380 * can cause devices on that bus to lose some context. Devices in D2 381 * must be prepared for the bus to be in D2 or higher. 382 * D3 State in which the device is off and not running. Device context is 383 * lost. Power can be removed from the device. 384 */ 385#define PCI_POWERSTATE_D0 0 386#define PCI_POWERSTATE_D1 1 387#define PCI_POWERSTATE_D2 2 388#define PCI_POWERSTATE_D3 3 389#define PCI_POWERSTATE_UNKNOWN -1 390 391static __inline int 392pci_set_powerstate(device_t dev, int state) 393{ 394 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 395} 396 397static __inline int 398pci_get_powerstate(device_t dev) 399{ 400 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 401} 402 403static __inline int 404pci_find_cap(device_t dev, int capability, int *capreg) 405{ 406 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 407} 408 409static __inline int 410pci_find_extcap(device_t dev, int capability, int *capreg) 411{ 412 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 413} 414 415static __inline int 416pci_alloc_msi(device_t dev, int *count) 417{ 418 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 419} 420 421static __inline int 422pci_alloc_msix(device_t dev, int *count) 423{ 424 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 425} 426 427static __inline int 428pci_remap_msix(device_t dev, int count, const u_int *vectors) 429{ 430 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 431} 432 433static __inline int 434pci_release_msi(device_t dev) 435{ 436 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 437} 438 439static __inline int 440pci_msi_count(device_t dev) 441{ 442 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 443} 444 445static __inline int 446pci_msix_count(device_t dev) 447{ 448 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 449} 450 451device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 452device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 453device_t pci_find_device(uint16_t, uint16_t); 454 455/* Can be used by drivers to manage the MSI-X table. */ 456int pci_pending_msix(device_t dev, u_int index); 457 458int pci_msi_device_blacklisted(device_t dev); 459 460void pci_ht_map_msi(device_t dev, uint64_t addr); 461 462int pci_get_max_read_req(device_t dev); 463int pci_set_max_read_req(device_t dev, int size); 464 465#endif /* _SYS_BUS_H_ */ 466 467/* 468 * cdev switch for control device, initialised in generic PCI code 469 */ 470extern struct cdevsw pcicdev; 471 472/* 473 * List of all PCI devices, generation count for the list. 474 */ 475STAILQ_HEAD(devlist, pci_devinfo); 476 477extern struct devlist pci_devq; 478extern uint32_t pci_generation; 479 480#endif /* _PCIVAR_H_ */ 481