pcivar.h revision 167909
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 167909 2007-03-26 20:18:52Z jhb $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36 37#define PCI_BUSMAX 255 /* highest supported bus number */ 38#define PCI_SLOTMAX 31 /* highest supported slot number */ 39#define PCI_FUNCMAX 7 /* highest supported function number */ 40#define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46typedef uint64_t pci_addr_t; 47 48/* Interesting values for PCI power management */ 49struct pcicfg_pp { 50 uint16_t pp_cap; /* PCI power management capabilities */ 51 uint8_t pp_status; /* config space address of PCI power status reg */ 52 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 53 uint8_t pp_data; /* config space address of PCI power data reg */ 54}; 55 56struct vpd_readonly { 57 char keyword[2]; 58 char *value; 59}; 60 61struct vpd_write { 62 char keyword[2]; 63 char *value; 64 int start; 65 int len; 66}; 67 68struct pcicfg_vpd { 69 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 70 char vpd_cached; 71 char *vpd_ident; /* string identifier */ 72 int vpd_rocnt; 73 struct vpd_readonly *vpd_ros; 74 int vpd_wcnt; 75 struct vpd_write *vpd_w; 76}; 77 78/* Interesting values for PCI MSI */ 79struct pcicfg_msi { 80 uint16_t msi_ctrl; /* Message Control */ 81 uint8_t msi_location; /* Offset of MSI capability registers. */ 82 uint8_t msi_msgnum; /* Number of messages */ 83 int msi_alloc; /* Number of allocated messages. */ 84 uint64_t msi_addr; /* Contents of address register. */ 85 uint16_t msi_data; /* Contents of data register. */ 86}; 87 88/* Interesting values for PCI MSI-X */ 89struct pcicfg_msix { 90 uint16_t msix_ctrl; /* Message Control */ 91 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 92 uint16_t msix_msgnum; /* Number of messages */ 93 int msix_alloc; /* Number of allocated messages. */ 94 uint8_t msix_table_bar; /* BAR containing vector table. */ 95 uint8_t msix_pba_bar; /* BAR containing PBA. */ 96 uint32_t msix_table_offset; 97 uint32_t msix_pba_offset; 98 struct resource *msix_table_res; /* Resource containing vector table. */ 99 struct resource *msix_pba_res; /* Resource containing PBA. */ 100}; 101 102/* config header information common to all header types */ 103typedef struct pcicfg { 104 struct device *dev; /* device which owns this */ 105 106 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 107 uint32_t bios; /* BIOS mapping */ 108 109 uint16_t subvendor; /* card vendor ID */ 110 uint16_t subdevice; /* card device ID, assigned by card vendor */ 111 uint16_t vendor; /* chip vendor ID */ 112 uint16_t device; /* chip device ID, assigned by chip vendor */ 113 114 uint16_t cmdreg; /* disable/enable chip and PCI options */ 115 uint16_t statreg; /* supported PCI features and error state */ 116 117 uint8_t baseclass; /* chip PCI class */ 118 uint8_t subclass; /* chip PCI subclass */ 119 uint8_t progif; /* chip PCI programming interface */ 120 uint8_t revid; /* chip revision ID */ 121 122 uint8_t hdrtype; /* chip config header type */ 123 uint8_t cachelnsz; /* cache line size in 4byte units */ 124 uint8_t intpin; /* PCI interrupt pin */ 125 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 126 127 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 128 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 129 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 130 131 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 132 uint8_t nummaps; /* actual number of PCI maps used */ 133 134 uint8_t bus; /* config space bus address */ 135 uint8_t slot; /* config space slot address */ 136 uint8_t func; /* config space function number */ 137 138 struct pcicfg_pp pp; /* pci power management */ 139 struct pcicfg_vpd vpd; /* pci vital product data */ 140 struct pcicfg_msi msi; /* pci msi */ 141 struct pcicfg_msix msix; /* pci msi-x */ 142} pcicfgregs; 143 144/* additional type 1 device config header information (PCI to PCI bridge) */ 145 146#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 147#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 148#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 149#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 150 151typedef struct { 152 pci_addr_t pmembase; /* base address of prefetchable memory */ 153 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 154 uint32_t membase; /* base address of memory window */ 155 uint32_t memlimit; /* topmost address of memory window */ 156 uint32_t iobase; /* base address of port window */ 157 uint32_t iolimit; /* topmost address of port window */ 158 uint16_t secstat; /* secondary bus status register */ 159 uint16_t bridgectl; /* bridge control register */ 160 uint8_t seclat; /* CardBus latency timer */ 161} pcih1cfgregs; 162 163/* additional type 2 device config header information (CardBus bridge) */ 164 165typedef struct { 166 uint32_t membase0; /* base address of memory window */ 167 uint32_t memlimit0; /* topmost address of memory window */ 168 uint32_t membase1; /* base address of memory window */ 169 uint32_t memlimit1; /* topmost address of memory window */ 170 uint32_t iobase0; /* base address of port window */ 171 uint32_t iolimit0; /* topmost address of port window */ 172 uint32_t iobase1; /* base address of port window */ 173 uint32_t iolimit1; /* topmost address of port window */ 174 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 175 uint16_t secstat; /* secondary bus status register */ 176 uint16_t bridgectl; /* bridge control register */ 177 uint8_t seclat; /* CardBus latency timer */ 178} pcih2cfgregs; 179 180extern uint32_t pci_numdevs; 181 182/* Only if the prerequisites are present */ 183#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 184struct pci_devinfo { 185 STAILQ_ENTRY(pci_devinfo) pci_links; 186 struct resource_list resources; 187 pcicfgregs cfg; 188 struct pci_conf conf; 189}; 190#endif 191 192#ifdef _SYS_BUS_H_ 193 194#include "pci_if.h" 195 196/* 197 * Define pci-specific resource flags for accessing memory via dense 198 * or bwx memory spaces. These flags are ignored on i386. 199 */ 200#define PCI_RF_DENSE 0x10000 201#define PCI_RF_BWX 0x20000 202 203enum pci_device_ivars { 204 PCI_IVAR_SUBVENDOR, 205 PCI_IVAR_SUBDEVICE, 206 PCI_IVAR_VENDOR, 207 PCI_IVAR_DEVICE, 208 PCI_IVAR_DEVID, 209 PCI_IVAR_CLASS, 210 PCI_IVAR_SUBCLASS, 211 PCI_IVAR_PROGIF, 212 PCI_IVAR_REVID, 213 PCI_IVAR_INTPIN, 214 PCI_IVAR_IRQ, 215 PCI_IVAR_BUS, 216 PCI_IVAR_SLOT, 217 PCI_IVAR_FUNCTION, 218 PCI_IVAR_ETHADDR, 219 PCI_IVAR_CMDREG, 220 PCI_IVAR_CACHELNSZ, 221 PCI_IVAR_MINGNT, 222 PCI_IVAR_MAXLAT, 223 PCI_IVAR_LATTIMER, 224}; 225 226/* 227 * Simplified accessors for pci devices 228 */ 229#define PCI_ACCESSOR(var, ivar, type) \ 230 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 231 232PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 233PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 234PCI_ACCESSOR(vendor, VENDOR, uint16_t) 235PCI_ACCESSOR(device, DEVICE, uint16_t) 236PCI_ACCESSOR(devid, DEVID, uint32_t) 237PCI_ACCESSOR(class, CLASS, uint8_t) 238PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 239PCI_ACCESSOR(progif, PROGIF, uint8_t) 240PCI_ACCESSOR(revid, REVID, uint8_t) 241PCI_ACCESSOR(intpin, INTPIN, uint8_t) 242PCI_ACCESSOR(irq, IRQ, uint8_t) 243PCI_ACCESSOR(bus, BUS, uint8_t) 244PCI_ACCESSOR(slot, SLOT, uint8_t) 245PCI_ACCESSOR(function, FUNCTION, uint8_t) 246PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 247PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 248PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 249PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 250PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 251PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 252 253#undef PCI_ACCESSOR 254 255/* 256 * Operations on configuration space. 257 */ 258static __inline uint32_t 259pci_read_config(device_t dev, int reg, int width) 260{ 261 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 262} 263 264static __inline void 265pci_write_config(device_t dev, int reg, uint32_t val, int width) 266{ 267 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 268} 269 270/* 271 * Ivars for pci bridges. 272 */ 273 274/*typedef enum pci_device_ivars pcib_device_ivars;*/ 275enum pcib_device_ivars { 276 PCIB_IVAR_BUS 277}; 278 279#define PCIB_ACCESSOR(var, ivar, type) \ 280 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 281 282PCIB_ACCESSOR(bus, BUS, uint32_t) 283 284#undef PCIB_ACCESSOR 285 286/* 287 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 288 * on i386 or other platforms should be mapped out in the MD pcireadconf 289 * code and not here, since the only MI invalid IRQ is 255. 290 */ 291#define PCI_INVALID_IRQ 255 292#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 293 294/* 295 * Convenience functions. 296 * 297 * These should be used in preference to manually manipulating 298 * configuration space. 299 */ 300static __inline int 301pci_enable_busmaster(device_t dev) 302{ 303 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 304} 305 306static __inline int 307pci_disable_busmaster(device_t dev) 308{ 309 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 310} 311 312static __inline int 313pci_enable_io(device_t dev, int space) 314{ 315 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 316} 317 318static __inline int 319pci_disable_io(device_t dev, int space) 320{ 321 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 322} 323 324static __inline int 325pci_get_vpd_ident(device_t dev, const char **identptr) 326{ 327 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 328} 329 330static __inline int 331pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 332{ 333 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 334} 335 336/* 337 * Check if the address range falls within the VGA defined address range(s) 338 */ 339static __inline int 340pci_is_vga_ioport_range(u_long start, u_long end) 341{ 342 343 return (((start >= 0x3b0 && end <= 0x3bb) || 344 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 345} 346 347static __inline int 348pci_is_vga_memory_range(u_long start, u_long end) 349{ 350 351 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 352} 353 354/* 355 * PCI power states are as defined by ACPI: 356 * 357 * D0 State in which device is on and running. It is receiving full 358 * power from the system and delivering full functionality to the user. 359 * D1 Class-specific low-power state in which device context may or may not 360 * be lost. Buses in D1 cannot do anything to the bus that would force 361 * devices on that bus to lose context. 362 * D2 Class-specific low-power state in which device context may or may 363 * not be lost. Attains greater power savings than D1. Buses in D2 364 * can cause devices on that bus to lose some context. Devices in D2 365 * must be prepared for the bus to be in D2 or higher. 366 * D3 State in which the device is off and not running. Device context is 367 * lost. Power can be removed from the device. 368 */ 369#define PCI_POWERSTATE_D0 0 370#define PCI_POWERSTATE_D1 1 371#define PCI_POWERSTATE_D2 2 372#define PCI_POWERSTATE_D3 3 373#define PCI_POWERSTATE_UNKNOWN -1 374 375static __inline int 376pci_set_powerstate(device_t dev, int state) 377{ 378 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 379} 380 381static __inline int 382pci_get_powerstate(device_t dev) 383{ 384 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 385} 386 387static __inline int 388pci_find_extcap(device_t dev, int capability, int *capreg) 389{ 390 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 391} 392 393static __inline int 394pci_alloc_msi(device_t dev, int *count) 395{ 396 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 397} 398 399static __inline int 400pci_alloc_msix(device_t dev, int *count) 401{ 402 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 403} 404 405static __inline int 406pci_remap_msix(device_t dev, u_int *indices) 407{ 408 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, indices)); 409} 410 411static __inline int 412pci_release_msi(device_t dev) 413{ 414 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 415} 416 417static __inline int 418pci_msi_count(device_t dev) 419{ 420 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 421} 422 423static __inline int 424pci_msix_count(device_t dev) 425{ 426 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 427} 428 429device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 430device_t pci_find_device(uint16_t, uint16_t); 431 432/* Used by MD code to program MSI and MSI-X registers. */ 433void pci_enable_msi(device_t dev, uint64_t address, uint16_t data); 434void pci_enable_msix(device_t dev, u_int index, uint64_t address, 435 uint32_t data); 436void pci_mask_msix(device_t dev, u_int index); 437int pci_pending_msix(device_t dev, u_int index); 438void pci_unmask_msix(device_t dev, u_int index); 439int pci_msi_device_blacklisted(device_t dev); 440 441#endif /* _SYS_BUS_H_ */ 442 443/* 444 * cdev switch for control device, initialised in generic PCI code 445 */ 446extern struct cdevsw pcicdev; 447 448/* 449 * List of all PCI devices, generation count for the list. 450 */ 451STAILQ_HEAD(devlist, pci_devinfo); 452 453extern struct devlist pci_devq; 454extern uint32_t pci_generation; 455 456#endif /* _PCIVAR_H_ */ 457