pcivar.h revision 165217
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 165217 2006-12-14 16:53:48Z jhb $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36 37#define PCI_BUSMAX 255 /* highest supported bus number */ 38#define PCI_SLOTMAX 31 /* highest supported slot number */ 39#define PCI_FUNCMAX 7 /* highest supported function number */ 40#define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46typedef uint64_t pci_addr_t; 47 48/* Interesting values for PCI power management */ 49struct pcicfg_pp { 50 uint16_t pp_cap; /* PCI power management capabilities */ 51 uint8_t pp_status; /* config space address of PCI power status reg */ 52 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 53 uint8_t pp_data; /* config space address of PCI power data reg */ 54}; 55 56struct vpd_readonly { 57 char keyword[2]; 58 char *value; 59}; 60 61struct vpd_write { 62 char keyword[2]; 63 char *value; 64 int start; 65 int len; 66}; 67 68struct pcicfg_vpd { 69 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 70 char *vpd_ident; /* string identifier */ 71 int vpd_rocnt; 72 struct vpd_readonly *vpd_ros; 73 int vpd_wcnt; 74 struct vpd_write *vpd_w; 75}; 76 77/* Interesting values for PCI MSI */ 78struct pcicfg_msi { 79 uint16_t msi_ctrl; /* Message Control */ 80 uint8_t msi_location; /* Offset of MSI capability registers. */ 81 uint8_t msi_msgnum; /* Number of messages */ 82 int msi_alloc; /* Number of allocated messages. */ 83 uint64_t msi_addr; /* Contents of address register. */ 84 uint16_t msi_data; /* Contents of data register. */ 85}; 86 87/* Interesting values for PCI MSI-X */ 88struct pcicfg_msix { 89 uint16_t msix_ctrl; /* Message Control */ 90 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 91 uint16_t msix_msgnum; /* Number of messages */ 92 int msix_alloc; /* Number of allocated messages. */ 93 uint8_t msix_table_bar; /* BAR containing vector table. */ 94 uint8_t msix_pba_bar; /* BAR containing PBA. */ 95 uint32_t msix_table_offset; 96 uint32_t msix_pba_offset; 97 struct resource *msix_table_res; /* Resource containing vector table. */ 98 struct resource *msix_pba_res; /* Resource containing PBA. */ 99}; 100 101/* config header information common to all header types */ 102typedef struct pcicfg { 103 struct device *dev; /* device which owns this */ 104 105 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 106 uint32_t bios; /* BIOS mapping */ 107 108 uint16_t subvendor; /* card vendor ID */ 109 uint16_t subdevice; /* card device ID, assigned by card vendor */ 110 uint16_t vendor; /* chip vendor ID */ 111 uint16_t device; /* chip device ID, assigned by chip vendor */ 112 113 uint16_t cmdreg; /* disable/enable chip and PCI options */ 114 uint16_t statreg; /* supported PCI features and error state */ 115 116 uint8_t baseclass; /* chip PCI class */ 117 uint8_t subclass; /* chip PCI subclass */ 118 uint8_t progif; /* chip PCI programming interface */ 119 uint8_t revid; /* chip revision ID */ 120 121 uint8_t hdrtype; /* chip config header type */ 122 uint8_t cachelnsz; /* cache line size in 4byte units */ 123 uint8_t intpin; /* PCI interrupt pin */ 124 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 125 126 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 127 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 128 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 129 130 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 131 uint8_t nummaps; /* actual number of PCI maps used */ 132 133 uint8_t bus; /* config space bus address */ 134 uint8_t slot; /* config space slot address */ 135 uint8_t func; /* config space function number */ 136 137 struct pcicfg_pp pp; /* pci power management */ 138 struct pcicfg_vpd vpd; /* pci vital product data */ 139 struct pcicfg_msi msi; /* pci msi */ 140 struct pcicfg_msix msix; /* pci msi-x */ 141} pcicfgregs; 142 143/* additional type 1 device config header information (PCI to PCI bridge) */ 144 145#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 146#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 147#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 148#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 149 150typedef struct { 151 pci_addr_t pmembase; /* base address of prefetchable memory */ 152 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 153 uint32_t membase; /* base address of memory window */ 154 uint32_t memlimit; /* topmost address of memory window */ 155 uint32_t iobase; /* base address of port window */ 156 uint32_t iolimit; /* topmost address of port window */ 157 uint16_t secstat; /* secondary bus status register */ 158 uint16_t bridgectl; /* bridge control register */ 159 uint8_t seclat; /* CardBus latency timer */ 160} pcih1cfgregs; 161 162/* additional type 2 device config header information (CardBus bridge) */ 163 164typedef struct { 165 uint32_t membase0; /* base address of memory window */ 166 uint32_t memlimit0; /* topmost address of memory window */ 167 uint32_t membase1; /* base address of memory window */ 168 uint32_t memlimit1; /* topmost address of memory window */ 169 uint32_t iobase0; /* base address of port window */ 170 uint32_t iolimit0; /* topmost address of port window */ 171 uint32_t iobase1; /* base address of port window */ 172 uint32_t iolimit1; /* topmost address of port window */ 173 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 174 uint16_t secstat; /* secondary bus status register */ 175 uint16_t bridgectl; /* bridge control register */ 176 uint8_t seclat; /* CardBus latency timer */ 177} pcih2cfgregs; 178 179extern uint32_t pci_numdevs; 180 181/* Only if the prerequisites are present */ 182#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 183struct pci_devinfo { 184 STAILQ_ENTRY(pci_devinfo) pci_links; 185 struct resource_list resources; 186 pcicfgregs cfg; 187 struct pci_conf conf; 188}; 189#endif 190 191#ifdef _SYS_BUS_H_ 192 193#include "pci_if.h" 194 195/* 196 * Define pci-specific resource flags for accessing memory via dense 197 * or bwx memory spaces. These flags are ignored on i386. 198 */ 199#define PCI_RF_DENSE 0x10000 200#define PCI_RF_BWX 0x20000 201 202enum pci_device_ivars { 203 PCI_IVAR_SUBVENDOR, 204 PCI_IVAR_SUBDEVICE, 205 PCI_IVAR_VENDOR, 206 PCI_IVAR_DEVICE, 207 PCI_IVAR_DEVID, 208 PCI_IVAR_CLASS, 209 PCI_IVAR_SUBCLASS, 210 PCI_IVAR_PROGIF, 211 PCI_IVAR_REVID, 212 PCI_IVAR_INTPIN, 213 PCI_IVAR_IRQ, 214 PCI_IVAR_BUS, 215 PCI_IVAR_SLOT, 216 PCI_IVAR_FUNCTION, 217 PCI_IVAR_ETHADDR, 218 PCI_IVAR_CMDREG, 219 PCI_IVAR_CACHELNSZ, 220 PCI_IVAR_MINGNT, 221 PCI_IVAR_MAXLAT, 222 PCI_IVAR_LATTIMER, 223}; 224 225/* 226 * Simplified accessors for pci devices 227 */ 228#define PCI_ACCESSOR(var, ivar, type) \ 229 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 230 231PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 232PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 233PCI_ACCESSOR(vendor, VENDOR, uint16_t) 234PCI_ACCESSOR(device, DEVICE, uint16_t) 235PCI_ACCESSOR(devid, DEVID, uint32_t) 236PCI_ACCESSOR(class, CLASS, uint8_t) 237PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 238PCI_ACCESSOR(progif, PROGIF, uint8_t) 239PCI_ACCESSOR(revid, REVID, uint8_t) 240PCI_ACCESSOR(intpin, INTPIN, uint8_t) 241PCI_ACCESSOR(irq, IRQ, uint8_t) 242PCI_ACCESSOR(bus, BUS, uint8_t) 243PCI_ACCESSOR(slot, SLOT, uint8_t) 244PCI_ACCESSOR(function, FUNCTION, uint8_t) 245PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 246PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 247PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 248PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 249PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 250PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 251 252#undef PCI_ACCESSOR 253 254/* 255 * Operations on configuration space. 256 */ 257static __inline uint32_t 258pci_read_config(device_t dev, int reg, int width) 259{ 260 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 261} 262 263static __inline void 264pci_write_config(device_t dev, int reg, uint32_t val, int width) 265{ 266 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 267} 268 269/* 270 * Ivars for pci bridges. 271 */ 272 273/*typedef enum pci_device_ivars pcib_device_ivars;*/ 274enum pcib_device_ivars { 275 PCIB_IVAR_BUS 276}; 277 278#define PCIB_ACCESSOR(var, ivar, type) \ 279 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 280 281PCIB_ACCESSOR(bus, BUS, uint32_t) 282 283#undef PCIB_ACCESSOR 284 285/* 286 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 287 * on i386 or other platforms should be mapped out in the MD pcireadconf 288 * code and not here, since the only MI invalid IRQ is 255. 289 */ 290#define PCI_INVALID_IRQ 255 291#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 292 293/* 294 * Convenience functions. 295 * 296 * These should be used in preference to manually manipulating 297 * configuration space. 298 */ 299static __inline int 300pci_enable_busmaster(device_t dev) 301{ 302 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 303} 304 305static __inline int 306pci_disable_busmaster(device_t dev) 307{ 308 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 309} 310 311static __inline int 312pci_enable_io(device_t dev, int space) 313{ 314 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 315} 316 317static __inline int 318pci_disable_io(device_t dev, int space) 319{ 320 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 321} 322 323static __inline int 324pci_get_vpd_ident(device_t dev, const char **identptr) 325{ 326 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 327} 328 329static __inline int 330pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 331{ 332 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 333} 334 335/* 336 * Check if the address range falls within the VGA defined address range(s) 337 */ 338static __inline int 339pci_is_vga_ioport_range(u_long start, u_long end) 340{ 341 342 return (((start >= 0x3b0 && end <= 0x3bb) || 343 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 344} 345 346static __inline int 347pci_is_vga_memory_range(u_long start, u_long end) 348{ 349 350 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 351} 352 353/* 354 * PCI power states are as defined by ACPI: 355 * 356 * D0 State in which device is on and running. It is receiving full 357 * power from the system and delivering full functionality to the user. 358 * D1 Class-specific low-power state in which device context may or may not 359 * be lost. Buses in D1 cannot do anything to the bus that would force 360 * devices on that bus to lose context. 361 * D2 Class-specific low-power state in which device context may or may 362 * not be lost. Attains greater power savings than D1. Buses in D2 363 * can cause devices on that bus to lose some context. Devices in D2 364 * must be prepared for the bus to be in D2 or higher. 365 * D3 State in which the device is off and not running. Device context is 366 * lost. Power can be removed from the device. 367 */ 368#define PCI_POWERSTATE_D0 0 369#define PCI_POWERSTATE_D1 1 370#define PCI_POWERSTATE_D2 2 371#define PCI_POWERSTATE_D3 3 372#define PCI_POWERSTATE_UNKNOWN -1 373 374static __inline int 375pci_set_powerstate(device_t dev, int state) 376{ 377 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 378} 379 380static __inline int 381pci_get_powerstate(device_t dev) 382{ 383 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 384} 385 386static __inline int 387pci_find_extcap(device_t dev, int capability, int *capreg) 388{ 389 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 390} 391 392static __inline int 393pci_alloc_msi(device_t dev, int *count) 394{ 395 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 396} 397 398static __inline int 399pci_release_msi(device_t dev) 400{ 401 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 402} 403 404static __inline int 405pci_msi_count(device_t dev) 406{ 407 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 408} 409 410device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 411device_t pci_find_device(uint16_t, uint16_t); 412 413/* Used by MD code to program MSI and MSI-X registers. */ 414void pci_enable_msi(device_t dev, uint64_t address, uint16_t data); 415void pci_enable_msix(device_t dev, u_int index, uint64_t address, 416 uint32_t data); 417void pci_mask_msix(device_t dev, u_int index); 418int pci_pending_msix(device_t dev, u_int index); 419void pci_unmask_msix(device_t dev, u_int index); 420 421#endif /* _SYS_BUS_H_ */ 422 423/* 424 * cdev switch for control device, initialised in generic PCI code 425 */ 426extern struct cdevsw pcicdev; 427 428/* 429 * List of all PCI devices, generation count for the list. 430 */ 431STAILQ_HEAD(devlist, pci_devinfo); 432 433extern struct devlist pci_devq; 434extern uint32_t pci_generation; 435 436#endif /* _PCIVAR_H_ */ 437