pcivar.h revision 139749
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 139749 2005-01-06 01:43:34Z imp $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36 37#define PCI_BUSMAX 255 /* highest supported bus number */ 38#define PCI_SLOTMAX 31 /* highest supported slot number */ 39#define PCI_FUNCMAX 7 /* highest supported function number */ 40#define PCI_REGMAX 255 /* highest supported config register addr. */ 41 42#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 43#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 44#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 45 46/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 47 48#ifdef PCI_A64 49typedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 50#else 51typedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 52#endif 53 54/* Interesting values for PCI power management */ 55struct pcicfg_pp { 56 uint16_t pp_cap; /* PCI power management capabilities */ 57 uint8_t pp_status; /* config space address of PCI power status reg */ 58 uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 59 uint8_t pp_data; /* config space address of PCI power data reg */ 60}; 61 62/* Interesting values for PCI MSI */ 63struct pcicfg_msi { 64 uint16_t msi_ctrl; /* Message Control */ 65 uint8_t msi_msgnum; /* Number of messages */ 66 uint16_t msi_data; /* Location of MSI data word */ 67}; 68 69/* config header information common to all header types */ 70typedef struct pcicfg { 71 struct device *dev; /* device which owns this */ 72 73 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 74 uint32_t bios; /* BIOS mapping */ 75 76 uint16_t subvendor; /* card vendor ID */ 77 uint16_t subdevice; /* card device ID, assigned by card vendor */ 78 uint16_t vendor; /* chip vendor ID */ 79 uint16_t device; /* chip device ID, assigned by chip vendor */ 80 81 uint16_t cmdreg; /* disable/enable chip and PCI options */ 82 uint16_t statreg; /* supported PCI features and error state */ 83 84 uint8_t baseclass; /* chip PCI class */ 85 uint8_t subclass; /* chip PCI subclass */ 86 uint8_t progif; /* chip PCI programming interface */ 87 uint8_t revid; /* chip revision ID */ 88 89 uint8_t hdrtype; /* chip config header type */ 90 uint8_t cachelnsz; /* cache line size in 4byte units */ 91 uint8_t intpin; /* PCI interrupt pin */ 92 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 93 94 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 95 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 96 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 97 98 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 99 uint8_t nummaps; /* actual number of PCI maps used */ 100 101 uint8_t bus; /* config space bus address */ 102 uint8_t slot; /* config space slot address */ 103 uint8_t func; /* config space function number */ 104 105 struct pcicfg_pp pp; /* pci power management */ 106 struct pcicfg_msi msi; /* pci msi */ 107} pcicfgregs; 108 109/* additional type 1 device config header information (PCI to PCI bridge) */ 110 111#ifdef PCI_A64 112#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 113#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 114#else 115#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 116#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 117#endif /* PCI_A64 */ 118 119#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 120#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 121 122typedef struct { 123 pci_addr_t pmembase; /* base address of prefetchable memory */ 124 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 125 uint32_t membase; /* base address of memory window */ 126 uint32_t memlimit; /* topmost address of memory window */ 127 uint32_t iobase; /* base address of port window */ 128 uint32_t iolimit; /* topmost address of port window */ 129 uint16_t secstat; /* secondary bus status register */ 130 uint16_t bridgectl; /* bridge control register */ 131 uint8_t seclat; /* CardBus latency timer */ 132} pcih1cfgregs; 133 134/* additional type 2 device config header information (CardBus bridge) */ 135 136typedef struct { 137 uint32_t membase0; /* base address of memory window */ 138 uint32_t memlimit0; /* topmost address of memory window */ 139 uint32_t membase1; /* base address of memory window */ 140 uint32_t memlimit1; /* topmost address of memory window */ 141 uint32_t iobase0; /* base address of port window */ 142 uint32_t iolimit0; /* topmost address of port window */ 143 uint32_t iobase1; /* base address of port window */ 144 uint32_t iolimit1; /* topmost address of port window */ 145 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 146 uint16_t secstat; /* secondary bus status register */ 147 uint16_t bridgectl; /* bridge control register */ 148 uint8_t seclat; /* CardBus latency timer */ 149} pcih2cfgregs; 150 151extern uint32_t pci_numdevs; 152 153/* Only if the prerequisites are present */ 154#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 155struct pci_devinfo { 156 STAILQ_ENTRY(pci_devinfo) pci_links; 157 struct resource_list resources; 158 pcicfgregs cfg; 159 struct pci_conf conf; 160}; 161#endif 162 163#ifdef __alpha__ 164vm_offset_t pci_cvt_to_dense (vm_offset_t); 165vm_offset_t pci_cvt_to_bwx (vm_offset_t); 166#endif /* __alpha__ */ 167 168#ifdef _SYS_BUS_H_ 169 170#include "pci_if.h" 171 172/* 173 * Define pci-specific resource flags for accessing memory via dense 174 * or bwx memory spaces. These flags are ignored on i386. 175 */ 176#define PCI_RF_DENSE 0x10000 177#define PCI_RF_BWX 0x20000 178 179enum pci_device_ivars { 180 PCI_IVAR_SUBVENDOR, 181 PCI_IVAR_SUBDEVICE, 182 PCI_IVAR_VENDOR, 183 PCI_IVAR_DEVICE, 184 PCI_IVAR_DEVID, 185 PCI_IVAR_CLASS, 186 PCI_IVAR_SUBCLASS, 187 PCI_IVAR_PROGIF, 188 PCI_IVAR_REVID, 189 PCI_IVAR_INTPIN, 190 PCI_IVAR_IRQ, 191 PCI_IVAR_BUS, 192 PCI_IVAR_SLOT, 193 PCI_IVAR_FUNCTION, 194 PCI_IVAR_ETHADDR, 195}; 196 197/* 198 * Simplified accessors for pci devices 199 */ 200#define PCI_ACCESSOR(var, ivar, type) \ 201 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 202 203PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 204PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 205PCI_ACCESSOR(vendor, VENDOR, uint16_t) 206PCI_ACCESSOR(device, DEVICE, uint16_t) 207PCI_ACCESSOR(devid, DEVID, uint32_t) 208PCI_ACCESSOR(class, CLASS, uint8_t) 209PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 210PCI_ACCESSOR(progif, PROGIF, uint8_t) 211PCI_ACCESSOR(revid, REVID, uint8_t) 212PCI_ACCESSOR(intpin, INTPIN, uint8_t) 213PCI_ACCESSOR(irq, IRQ, uint8_t) 214PCI_ACCESSOR(bus, BUS, uint8_t) 215PCI_ACCESSOR(slot, SLOT, uint8_t) 216PCI_ACCESSOR(function, FUNCTION, uint8_t) 217PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 218 219#undef PCI_ACCESSOR 220 221/* 222 * Operations on configuration space. 223 */ 224static __inline uint32_t 225pci_read_config(device_t dev, int reg, int width) 226{ 227 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 228} 229 230static __inline void 231pci_write_config(device_t dev, int reg, uint32_t val, int width) 232{ 233 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 234} 235 236/* 237 * Ivars for pci bridges. 238 */ 239 240/*typedef enum pci_device_ivars pcib_device_ivars;*/ 241enum pcib_device_ivars { 242 PCIB_IVAR_BUS 243}; 244 245#define PCIB_ACCESSOR(var, ivar, type) \ 246 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 247 248PCIB_ACCESSOR(bus, BUS, uint32_t) 249 250#undef PCIB_ACCESSOR 251 252/* 253 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 254 * on i386 or other platforms should be mapped out in the MD pcireadconf 255 * code and not here, since the only MI invalid IRQ is 255. 256 */ 257#define PCI_INVALID_IRQ 255 258#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 259 260/* 261 * Convenience functions. 262 * 263 * These should be used in preference to manually manipulating 264 * configuration space. 265 */ 266static __inline int 267pci_enable_busmaster(device_t dev) 268{ 269 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 270} 271 272static __inline int 273pci_disable_busmaster(device_t dev) 274{ 275 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 276} 277 278static __inline int 279pci_enable_io(device_t dev, int space) 280{ 281 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 282} 283 284static __inline int 285pci_disable_io(device_t dev, int space) 286{ 287 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 288} 289 290/* 291 * PCI power states are as defined by ACPI: 292 * 293 * D0 State in which device is on and running. It is receiving full 294 * power from the system and delivering full functionality to the user. 295 * D1 Class-specific low-power state in which device context may or may not 296 * be lost. Buses in D1 cannot do anything to the bus that would force 297 * devices on that bus to loose context. 298 * D2 Class-specific low-power state in which device context may or may 299 * not be lost. Attains greater power savings than D1. Buses in D2 300 * can cause devices on that bus to loose some context. Devices in D2 301 * must be prepared for the bus to be in D2 or higher. 302 * D3 State in which the device is off and not running. Device context is 303 * lost. Power can be removed from the device. 304 */ 305#define PCI_POWERSTATE_D0 0 306#define PCI_POWERSTATE_D1 1 307#define PCI_POWERSTATE_D2 2 308#define PCI_POWERSTATE_D3 3 309#define PCI_POWERSTATE_UNKNOWN -1 310 311static __inline int 312pci_set_powerstate(device_t dev, int state) 313{ 314 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 315} 316 317static __inline int 318pci_get_powerstate(device_t dev) 319{ 320 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 321} 322 323device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 324device_t pci_find_device(uint16_t, uint16_t); 325#endif /* _SYS_BUS_H_ */ 326 327/* 328 * cdev switch for control device, initialised in generic PCI code 329 */ 330extern struct cdevsw pcicdev; 331 332/* 333 * List of all PCI devices, generation count for the list. 334 */ 335STAILQ_HEAD(devlist, pci_devinfo); 336 337extern struct devlist pci_devq; 338extern uint32_t pci_generation; 339 340#endif /* _PCIVAR_H_ */ 341