pcivar.h revision 120063
126159Sse/* 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2650477Speter * $FreeBSD: head/sys/dev/pci/pcivar.h 120063 2003-09-14 19:30:00Z scottl $ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 3139231Sgibbs#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#include <sys/queue.h> 3439231Sgibbs 3526159Sse/* some PCI bus constants */ 366767Sse 3726159Sse#define PCI_BUSMAX 255 /* highest supported bus number */ 3826159Sse#define PCI_SLOTMAX 31 /* highest supported slot number */ 3926159Sse#define PCI_FUNCMAX 7 /* highest supported function number */ 4026159Sse#define PCI_REGMAX 255 /* highest supported config register addr. */ 416100Sse 4226159Sse#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 4326159Sse#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 4426159Sse#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 456100Sse 4626159Sse/* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 476100Sse 4826159Sse#ifdef PCI_A64 49119266Simptypedef uint64_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 5026159Sse#else 51119266Simptypedef uint32_t pci_addr_t; /* uint64_t for system with 64bit addresses */ 5226159Sse#endif 536100Sse 54120063Sscottl/* Interesting values for PCI power management */ 55120063Sscottlstruct pcicfg_pp { 56120063Sscottl uint16_t pp_cap; /* PCI power management capabilities */ 57120063Sscottl uint8_t pp_status; /* config space address of PCI power status reg */ 58120063Sscottl uint8_t pp_pmcsr; /* config space address of PMCSR reg */ 59120063Sscottl uint8_t pp_data; /* config space address of PCI power data reg */ 60120063Sscottl}; 61120063Sscottl 62120063Sscottl/* Interesting values for PCI MSI */ 63120063Sscottlstruct pcicfg_msi { 64120063Sscottl uint16_t msi_ctrl; /* Message Control */ 65120063Sscottl uint8_t msi_msgnum; /* Number of messages */ 66120063Sscottl uint16_t msi_data; /* Location of MSI data word */ 67120063Sscottl}; 68120063Sscottl 6926159Sse/* config header information common to all header types */ 706100Sse 7126159Ssetypedef struct pcicfg { 7245720Speter struct device *dev; /* device which owns this */ 736100Sse 74119266Simp uint16_t subvendor; /* card vendor ID */ 75119266Simp uint16_t subdevice; /* card device ID, assigned by card vendor */ 76119266Simp uint16_t vendor; /* chip vendor ID */ 77119266Simp uint16_t device; /* chip device ID, assigned by chip vendor */ 786100Sse 79119266Simp uint16_t cmdreg; /* disable/enable chip and PCI options */ 80119266Simp uint16_t statreg; /* supported PCI features and error state */ 817233Sse 82119266Simp uint8_t baseclass; /* chip PCI class */ 83119266Simp uint8_t subclass; /* chip PCI subclass */ 84119266Simp uint8_t progif; /* chip PCI programming interface */ 85119266Simp uint8_t revid; /* chip revision ID */ 866100Sse 87119266Simp uint8_t hdrtype; /* chip config header type */ 88119266Simp uint8_t cachelnsz; /* cache line size in 4byte units */ 89119266Simp uint8_t intpin; /* PCI interrupt pin */ 90119266Simp uint8_t intline; /* interrupt line (IRQ for PC arch) */ 916100Sse 92119266Simp uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 93119266Simp uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 94119266Simp uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 956100Sse 96119266Simp uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 97119266Simp uint8_t nummaps; /* actual number of PCI maps used */ 987233Sse 99119266Simp uint8_t bus; /* config space bus address */ 100119266Simp uint8_t slot; /* config space slot address */ 101119266Simp uint8_t func; /* config space function number */ 1027233Sse 103120063Sscottl struct pcicfg_pp pp; /* pci power management */ 104120063Sscottl struct pcicfg_msi msi; /* pci msi */ 10526159Sse} pcicfgregs; 1066100Sse 10726159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 1086100Sse 10926159Sse#ifdef PCI_A64 11026159Sse#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 11126159Sse#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 11226159Sse#else 11326159Sse#define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 11426159Sse#define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 11526159Sse#endif /* PCI_A64 */ 1166100Sse 11726159Sse#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 11826159Sse#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1197233Sse 12026159Ssetypedef struct { 12126159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 12226159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 123119266Simp uint32_t membase; /* base address of memory window */ 124119266Simp uint32_t memlimit; /* topmost address of memory window */ 125119266Simp uint32_t iobase; /* base address of port window */ 126119266Simp uint32_t iolimit; /* topmost address of port window */ 127119266Simp uint16_t secstat; /* secondary bus status register */ 128119266Simp uint16_t bridgectl; /* bridge control register */ 129119266Simp uint8_t seclat; /* CardBus latency timer */ 13026159Sse} pcih1cfgregs; 1316100Sse 13226159Sse/* additional type 2 device config header information (CardBus bridge) */ 13326159Sse 13426159Ssetypedef struct { 135119266Simp uint32_t membase0; /* base address of memory window */ 136119266Simp uint32_t memlimit0; /* topmost address of memory window */ 137119266Simp uint32_t membase1; /* base address of memory window */ 138119266Simp uint32_t memlimit1; /* topmost address of memory window */ 139119266Simp uint32_t iobase0; /* base address of port window */ 140119266Simp uint32_t iolimit0; /* topmost address of port window */ 141119266Simp uint32_t iobase1; /* base address of port window */ 142119266Simp uint32_t iolimit1; /* topmost address of port window */ 143119266Simp uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 144119266Simp uint16_t secstat; /* secondary bus status register */ 145119266Simp uint16_t bridgectl; /* bridge control register */ 146119266Simp uint8_t seclat; /* CardBus latency timer */ 14726159Sse} pcih2cfgregs; 14826159Sse 149119266Simpextern uint32_t pci_numdevs; 15039231Sgibbs 15161047Speter/* Only if the prerequisites are present */ 15261047Speter#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 15361047Speterstruct pci_devinfo { 15461047Speter STAILQ_ENTRY(pci_devinfo) pci_links; 15561047Speter struct resource_list resources; 15661047Speter pcicfgregs cfg; 15761047Speter struct pci_conf conf; 15861047Speter}; 15961047Speter#endif 16039231Sgibbs 16140004Sdfr#ifdef __alpha__ 16240004Sdfrvm_offset_t pci_cvt_to_dense (vm_offset_t); 16340004Sdfrvm_offset_t pci_cvt_to_bwx (vm_offset_t); 16440004Sdfr#endif /* __alpha__ */ 16545720Speter 16645720Speter#ifdef _SYS_BUS_H_ 16745720Speter 16845720Speter#include "pci_if.h" 16945720Speter 17052243Sdfr/* 17152243Sdfr * Define pci-specific resource flags for accessing memory via dense 17252243Sdfr * or bwx memory spaces. These flags are ignored on i386. 17352243Sdfr */ 17452243Sdfr#define PCI_RF_DENSE 0x10000 17552243Sdfr#define PCI_RF_BWX 0x20000 17652243Sdfr 17745720Speterenum pci_device_ivars { 17869953Smsmith PCI_IVAR_SUBVENDOR, 17969953Smsmith PCI_IVAR_SUBDEVICE, 18069953Smsmith PCI_IVAR_VENDOR, 18169953Smsmith PCI_IVAR_DEVICE, 18269953Smsmith PCI_IVAR_DEVID, 18369953Smsmith PCI_IVAR_CLASS, 18469953Smsmith PCI_IVAR_SUBCLASS, 18569953Smsmith PCI_IVAR_PROGIF, 18669953Smsmith PCI_IVAR_REVID, 18769953Smsmith PCI_IVAR_INTPIN, 18869953Smsmith PCI_IVAR_IRQ, 18969953Smsmith PCI_IVAR_BUS, 19069953Smsmith PCI_IVAR_SLOT, 19169953Smsmith PCI_IVAR_FUNCTION, 192107300Simp PCI_IVAR_ETHADDR, 19345720Speter}; 19445720Speter 19545720Speter/* 19645720Speter * Simplified accessors for pci devices 19745720Speter */ 198102145Smux#define PCI_ACCESSOR(var, ivar, type) \ 19988375Stmm __BUS_ACCESSOR(pci, var, PCI, ivar, type) 20045720Speter 201119266SimpPCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 202119266SimpPCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 203119266SimpPCI_ACCESSOR(vendor, VENDOR, uint16_t) 204119266SimpPCI_ACCESSOR(device, DEVICE, uint16_t) 205119266SimpPCI_ACCESSOR(devid, DEVID, uint32_t) 206119266SimpPCI_ACCESSOR(class, CLASS, uint8_t) 207119266SimpPCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 208119266SimpPCI_ACCESSOR(progif, PROGIF, uint8_t) 209119266SimpPCI_ACCESSOR(revid, REVID, uint8_t) 210119266SimpPCI_ACCESSOR(intpin, INTPIN, uint8_t) 211119266SimpPCI_ACCESSOR(irq, IRQ, uint8_t) 212119266SimpPCI_ACCESSOR(bus, BUS, uint8_t) 213119266SimpPCI_ACCESSOR(slot, SLOT, uint8_t) 214119266SimpPCI_ACCESSOR(function, FUNCTION, uint8_t) 215119266SimpPCI_ACCESSOR(ether, ETHADDR, uint8_t *) 21645720Speter 21766416Speter#undef PCI_ACCESSOR 21866416Speter 21969953Smsmith/* 22069953Smsmith * Operations on configuration space. 22169953Smsmith */ 222119266Simpstatic __inline uint32_t 22345720Speterpci_read_config(device_t dev, int reg, int width) 22445720Speter{ 22545720Speter return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 22645720Speter} 22745720Speter 22845720Speterstatic __inline void 229119266Simppci_write_config(device_t dev, int reg, uint32_t val, int width) 23045720Speter{ 23145720Speter PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 23245720Speter} 23345720Speter 23447339Sgallatin/* 23547339Sgallatin * Ivars for pci bridges. 23647339Sgallatin */ 23747339Sgallatin 23847339Sgallatin/*typedef enum pci_device_ivars pcib_device_ivars;*/ 23947339Sgallatinenum pcib_device_ivars { 24065176Sdfr PCIB_IVAR_BUS 24147339Sgallatin}; 24247339Sgallatin 243102144Smux#define PCIB_ACCESSOR(var, ivar, type) \ 244102144Smux __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 24547339Sgallatin 246119266SimpPCIB_ACCESSOR(bus, BUS, uint32_t) 24747339Sgallatin 24866416Speter#undef PCIB_ACCESSOR 24966416Speter 25069953Smsmith/* 25198017Simp * PCI interrupt validation. Invalid interrupt values such as 0 or 128 25298017Simp * on i386 or other platforms should be mapped out in the MD pcireadconf 25398017Simp * code and not here, since the only MI invalid IRQ is 255. 25490554Smsmith */ 25597695Simp#define PCI_INVALID_IRQ 255 25698017Simp#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 25790554Smsmith 25890554Smsmith/* 25969953Smsmith * Convenience functions. 26069953Smsmith * 26169953Smsmith * These should be used in preference to manually manipulating 26269953Smsmith * configuration space. 26369953Smsmith */ 264113544Smdoddstatic __inline int 26573185Speterpci_enable_busmaster(device_t dev) 26673185Speter{ 267113544Smdodd return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 26873185Speter} 26945720Speter 270113544Smdoddstatic __inline int 27173185Speterpci_disable_busmaster(device_t dev) 27273185Speter{ 273113544Smdodd return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 27473185Speter} 27573185Speter 276113544Smdoddstatic __inline int 27773185Speterpci_enable_io(device_t dev, int space) 27873185Speter{ 279113544Smdodd return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 28073185Speter} 28173185Speter 282113544Smdoddstatic __inline int 28373185Speterpci_disable_io(device_t dev, int space) 28473185Speter{ 285113544Smdodd return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 28673185Speter} 28773185Speter 28869953Smsmith/* 28969953Smsmith * PCI power states are as defined by ACPI: 29069953Smsmith * 29169953Smsmith * D0 State in which device is on and running. It is receiving full 29269953Smsmith * power from the system and delivering full functionality to the user. 29369953Smsmith * D1 Class-specific low-power state in which device context may or may not 29469953Smsmith * be lost. Buses in D1 cannot do anything to the bus that would force 29569953Smsmith * devices on that bus to loose context. 29669953Smsmith * D2 Class-specific low-power state in which device context may or may 29769953Smsmith * not be lost. Attains greater power savings than D1. Buses in D2 29869953Smsmith * can cause devices on that bus to loose some context. Devices in D2 29969953Smsmith * must be prepared for the bus to be in D2 or higher. 30069953Smsmith * D3 State in which the device is off and not running. Device context is 30169953Smsmith * lost. Power can be removed from the device. 30269953Smsmith */ 30369953Smsmith#define PCI_POWERSTATE_D0 0 30469953Smsmith#define PCI_POWERSTATE_D1 1 30569953Smsmith#define PCI_POWERSTATE_D2 2 30669953Smsmith#define PCI_POWERSTATE_D3 3 30769953Smsmith#define PCI_POWERSTATE_UNKNOWN -1 30826159Sse 30973185Speterstatic __inline int 31073185Speterpci_set_powerstate(device_t dev, int state) 31173185Speter{ 31273185Speter return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 31373185Speter} 31458287Speter 31573185Speterstatic __inline int 31673185Speterpci_get_powerstate(device_t dev) 31773185Speter{ 31873185Speter return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 31973185Speter} 32073185Speter 321119266Simpdevice_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 322119266Simpdevice_t pci_find_device(uint16_t, uint16_t); 32369953Smsmith#endif /* _SYS_BUS_H_ */ 32461047Speter 32569953Smsmith/* 32669953Smsmith * cdev switch for control device, initialised in generic PCI code 32769953Smsmith */ 32869953Smsmithextern struct cdevsw pcicdev; 32958287Speter 33069953Smsmith/* 33169953Smsmith * List of all PCI devices, generation count for the list. 33269953Smsmith */ 33388184SmdoddSTAILQ_HEAD(devlist, pci_devinfo); 33412453Sbde 33588184Smdoddextern struct devlist pci_devq; 336119266Simpextern uint32_t pci_generation; 33788184Smdodd 33839231Sgibbs#endif /* _PCIVAR_H_ */ 339