1139749Simp/*- 226159Sse * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 326159Sse * All rights reserved. 426159Sse * 526159Sse * Redistribution and use in source and binary forms, with or without 626159Sse * modification, are permitted provided that the following conditions 726159Sse * are met: 826159Sse * 1. Redistributions of source code must retain the above copyright 926159Sse * notice unmodified, this list of conditions, and the following 1026159Sse * disclaimer. 1126159Sse * 2. Redistributions in binary form must reproduce the above copyright 1226159Sse * notice, this list of conditions and the following disclaimer in the 1326159Sse * documentation and/or other materials provided with the distribution. 1426159Sse * 1526159Sse * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1626159Sse * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1726159Sse * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1826159Sse * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1926159Sse * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2026159Sse * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2126159Sse * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2226159Sse * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2326159Sse * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2426159Sse * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2526159Sse * 2650477Speter * $FreeBSD$ 2726159Sse * 2826159Sse */ 296100Sse 3039231Sgibbs#ifndef _PCIVAR_H_ 31165217Sjhb#define _PCIVAR_H_ 3239231Sgibbs 3339231Sgibbs#include <sys/queue.h> 3439231Sgibbs 3526159Sse/* some PCI bus constants */ 36165217Sjhb#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37165217Sjhb#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38165217Sjhb#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 396100Sse 40163805Simptypedef uint64_t pci_addr_t; 416100Sse 42120063Sscottl/* Interesting values for PCI power management */ 43120063Sscottlstruct pcicfg_pp { 44120063Sscottl uint16_t pp_cap; /* PCI power management capabilities */ 45214122Sjkim uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46214122Sjkim uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47214122Sjkim uint8_t pp_data; /* conf. space addr. of PM data reg */ 48120063Sscottl}; 49220195Sjhb 50220195Sjhbstruct pci_map { 51220195Sjhb pci_addr_t pm_value; /* Raw BAR value */ 52220195Sjhb pci_addr_t pm_size; 53220195Sjhb uint8_t pm_reg; 54220195Sjhb STAILQ_ENTRY(pci_map) pm_link; 55220195Sjhb}; 56220195Sjhb 57163163Sjmgstruct vpd_readonly { 58163163Sjmg char keyword[2]; 59163163Sjmg char *value; 60262134Sjhb int len; 61163163Sjmg}; 62163163Sjmg 63163163Sjmgstruct vpd_write { 64163163Sjmg char keyword[2]; 65163163Sjmg char *value; 66163163Sjmg int start; 67163163Sjmg int len; 68163163Sjmg}; 69163163Sjmg 70163163Sjmgstruct pcicfg_vpd { 71163163Sjmg uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 72167909Sjhb char vpd_cached; 73163163Sjmg char *vpd_ident; /* string identifier */ 74163163Sjmg int vpd_rocnt; 75163163Sjmg struct vpd_readonly *vpd_ros; 76163163Sjmg int vpd_wcnt; 77163163Sjmg struct vpd_write *vpd_w; 78163163Sjmg}; 79163163Sjmg 80120063Sscottl/* Interesting values for PCI MSI */ 81120063Sscottlstruct pcicfg_msi { 82120063Sscottl uint16_t msi_ctrl; /* Message Control */ 83164264Sjhb uint8_t msi_location; /* Offset of MSI capability registers. */ 84120063Sscottl uint8_t msi_msgnum; /* Number of messages */ 85164264Sjhb int msi_alloc; /* Number of allocated messages. */ 86164264Sjhb uint64_t msi_addr; /* Contents of address register. */ 87164264Sjhb uint16_t msi_data; /* Contents of data register. */ 88169221Sjhb u_int msi_handlers; 89120063Sscottl}; 90120063Sscottl 91164282Sjhb/* Interesting values for PCI MSI-X */ 92169221Sjhbstruct msix_vector { 93169221Sjhb uint64_t mv_address; /* Contents of address register. */ 94169221Sjhb uint32_t mv_data; /* Contents of data register. */ 95169221Sjhb int mv_irq; 96169221Sjhb}; 97169221Sjhb 98169221Sjhbstruct msix_table_entry { 99169221Sjhb u_int mte_vector; /* 1-based index into msix_vectors array. */ 100169221Sjhb u_int mte_handlers; 101169221Sjhb}; 102169221Sjhb 103164264Sjhbstruct pcicfg_msix { 104164264Sjhb uint16_t msix_ctrl; /* Message Control */ 105169221Sjhb uint16_t msix_msgnum; /* Number of messages */ 106164282Sjhb uint8_t msix_location; /* Offset of MSI-X capability registers. */ 107164264Sjhb uint8_t msix_table_bar; /* BAR containing vector table. */ 108164264Sjhb uint8_t msix_pba_bar; /* BAR containing PBA. */ 109164264Sjhb uint32_t msix_table_offset; 110164264Sjhb uint32_t msix_pba_offset; 111169221Sjhb int msix_alloc; /* Number of allocated vectors. */ 112169221Sjhb int msix_table_len; /* Length of virtual table. */ 113169221Sjhb struct msix_table_entry *msix_table; /* Virtual table. */ 114169221Sjhb struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 115164264Sjhb struct resource *msix_table_res; /* Resource containing vector table. */ 116164264Sjhb struct resource *msix_pba_res; /* Resource containing PBA. */ 117164264Sjhb}; 118164264Sjhb 119180753Sluoqi/* Interesting values for HyperTransport */ 120180753Sluoqistruct pcicfg_ht { 121219737Sjhb uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 122180753Sluoqi uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 123180753Sluoqi uint16_t ht_msictrl; /* MSI mapping control */ 124180753Sluoqi uint64_t ht_msiaddr; /* MSI mapping base address */ 125180753Sluoqi}; 126180753Sluoqi 12726159Sse/* config header information common to all header types */ 12826159Ssetypedef struct pcicfg { 12945720Speter struct device *dev; /* device which owns this */ 1306100Sse 131220195Sjhb STAILQ_HEAD(, pci_map) maps; /* BARs */ 132128019Simp 133119266Simp uint16_t subvendor; /* card vendor ID */ 134119266Simp uint16_t subdevice; /* card device ID, assigned by card vendor */ 135119266Simp uint16_t vendor; /* chip vendor ID */ 136119266Simp uint16_t device; /* chip device ID, assigned by chip vendor */ 1376100Sse 138119266Simp uint16_t cmdreg; /* disable/enable chip and PCI options */ 139119266Simp uint16_t statreg; /* supported PCI features and error state */ 1407233Sse 141119266Simp uint8_t baseclass; /* chip PCI class */ 142119266Simp uint8_t subclass; /* chip PCI subclass */ 143119266Simp uint8_t progif; /* chip PCI programming interface */ 144119266Simp uint8_t revid; /* chip revision ID */ 1456100Sse 146119266Simp uint8_t hdrtype; /* chip config header type */ 147119266Simp uint8_t cachelnsz; /* cache line size in 4byte units */ 148119266Simp uint8_t intpin; /* PCI interrupt pin */ 149119266Simp uint8_t intline; /* interrupt line (IRQ for PC arch) */ 1506100Sse 151119266Simp uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 152119266Simp uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 153119266Simp uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 1546100Sse 155119266Simp uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 156119266Simp uint8_t nummaps; /* actual number of PCI maps used */ 1577233Sse 158172394Smarius uint32_t domain; /* PCI domain */ 159119266Simp uint8_t bus; /* config space bus address */ 160119266Simp uint8_t slot; /* config space slot address */ 161119266Simp uint8_t func; /* config space function number */ 1627233Sse 163193256Sjhb struct pcicfg_pp pp; /* Power management */ 164193256Sjhb struct pcicfg_vpd vpd; /* Vital product data */ 165193256Sjhb struct pcicfg_msi msi; /* PCI MSI */ 166193256Sjhb struct pcicfg_msix msix; /* PCI MSI-X */ 167180753Sluoqi struct pcicfg_ht ht; /* HyperTransport */ 16826159Sse} pcicfgregs; 1696100Sse 17026159Sse/* additional type 1 device config header information (PCI to PCI bridge) */ 1716100Sse 172165217Sjhb#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 173165217Sjhb#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 174165217Sjhb#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 175165217Sjhb#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 1767233Sse 17726159Ssetypedef struct { 17826159Sse pci_addr_t pmembase; /* base address of prefetchable memory */ 17926159Sse pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 180119266Simp uint32_t membase; /* base address of memory window */ 181119266Simp uint32_t memlimit; /* topmost address of memory window */ 182119266Simp uint32_t iobase; /* base address of port window */ 183119266Simp uint32_t iolimit; /* topmost address of port window */ 184119266Simp uint16_t secstat; /* secondary bus status register */ 185119266Simp uint16_t bridgectl; /* bridge control register */ 186119266Simp uint8_t seclat; /* CardBus latency timer */ 18726159Sse} pcih1cfgregs; 1886100Sse 18926159Sse/* additional type 2 device config header information (CardBus bridge) */ 19026159Sse 19126159Ssetypedef struct { 192119266Simp uint32_t membase0; /* base address of memory window */ 193119266Simp uint32_t memlimit0; /* topmost address of memory window */ 194119266Simp uint32_t membase1; /* base address of memory window */ 195119266Simp uint32_t memlimit1; /* topmost address of memory window */ 196119266Simp uint32_t iobase0; /* base address of port window */ 197119266Simp uint32_t iolimit0; /* topmost address of port window */ 198119266Simp uint32_t iobase1; /* base address of port window */ 199119266Simp uint32_t iolimit1; /* topmost address of port window */ 200119266Simp uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 201119266Simp uint16_t secstat; /* secondary bus status register */ 202119266Simp uint16_t bridgectl; /* bridge control register */ 203119266Simp uint8_t seclat; /* CardBus latency timer */ 20426159Sse} pcih2cfgregs; 20526159Sse 206119266Simpextern uint32_t pci_numdevs; 20739231Sgibbs 20861047Speter/* Only if the prerequisites are present */ 20961047Speter#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 21061047Speterstruct pci_devinfo { 21161047Speter STAILQ_ENTRY(pci_devinfo) pci_links; 21261047Speter struct resource_list resources; 21361047Speter pcicfgregs cfg; 21461047Speter struct pci_conf conf; 21561047Speter}; 21661047Speter#endif 21739231Sgibbs 21845720Speter#ifdef _SYS_BUS_H_ 21945720Speter 22045720Speter#include "pci_if.h" 22145720Speter 22245720Speterenum pci_device_ivars { 22369953Smsmith PCI_IVAR_SUBVENDOR, 22469953Smsmith PCI_IVAR_SUBDEVICE, 22569953Smsmith PCI_IVAR_VENDOR, 22669953Smsmith PCI_IVAR_DEVICE, 22769953Smsmith PCI_IVAR_DEVID, 22869953Smsmith PCI_IVAR_CLASS, 22969953Smsmith PCI_IVAR_SUBCLASS, 23069953Smsmith PCI_IVAR_PROGIF, 23169953Smsmith PCI_IVAR_REVID, 23269953Smsmith PCI_IVAR_INTPIN, 23369953Smsmith PCI_IVAR_IRQ, 234172394Smarius PCI_IVAR_DOMAIN, 23569953Smsmith PCI_IVAR_BUS, 23669953Smsmith PCI_IVAR_SLOT, 23769953Smsmith PCI_IVAR_FUNCTION, 238107300Simp PCI_IVAR_ETHADDR, 239149972Simp PCI_IVAR_CMDREG, 240149972Simp PCI_IVAR_CACHELNSZ, 241149972Simp PCI_IVAR_MINGNT, 242149972Simp PCI_IVAR_MAXLAT, 243178161Sphk PCI_IVAR_LATTIMER 24445720Speter}; 24545720Speter 24645720Speter/* 24745720Speter * Simplified accessors for pci devices 24845720Speter */ 249165217Sjhb#define PCI_ACCESSOR(var, ivar, type) \ 25088375Stmm __BUS_ACCESSOR(pci, var, PCI, ivar, type) 25145720Speter 252119266SimpPCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 253119266SimpPCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 254119266SimpPCI_ACCESSOR(vendor, VENDOR, uint16_t) 255119266SimpPCI_ACCESSOR(device, DEVICE, uint16_t) 256119266SimpPCI_ACCESSOR(devid, DEVID, uint32_t) 257119266SimpPCI_ACCESSOR(class, CLASS, uint8_t) 258119266SimpPCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 259119266SimpPCI_ACCESSOR(progif, PROGIF, uint8_t) 260119266SimpPCI_ACCESSOR(revid, REVID, uint8_t) 261119266SimpPCI_ACCESSOR(intpin, INTPIN, uint8_t) 262119266SimpPCI_ACCESSOR(irq, IRQ, uint8_t) 263172394SmariusPCI_ACCESSOR(domain, DOMAIN, uint32_t) 264119266SimpPCI_ACCESSOR(bus, BUS, uint8_t) 265119266SimpPCI_ACCESSOR(slot, SLOT, uint8_t) 266119266SimpPCI_ACCESSOR(function, FUNCTION, uint8_t) 267119266SimpPCI_ACCESSOR(ether, ETHADDR, uint8_t *) 268149972SimpPCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 269149972SimpPCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 270149972SimpPCI_ACCESSOR(mingnt, MINGNT, uint8_t) 271149972SimpPCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 272149972SimpPCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 27345720Speter 27466416Speter#undef PCI_ACCESSOR 27566416Speter 27669953Smsmith/* 27769953Smsmith * Operations on configuration space. 27869953Smsmith */ 279119266Simpstatic __inline uint32_t 28045720Speterpci_read_config(device_t dev, int reg, int width) 28145720Speter{ 28245720Speter return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 28345720Speter} 28445720Speter 28545720Speterstatic __inline void 286119266Simppci_write_config(device_t dev, int reg, uint32_t val, int width) 28745720Speter{ 28845720Speter PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 28945720Speter} 29045720Speter 29147339Sgallatin/* 29247339Sgallatin * Ivars for pci bridges. 29347339Sgallatin */ 29447339Sgallatin 29547339Sgallatin/*typedef enum pci_device_ivars pcib_device_ivars;*/ 29647339Sgallatinenum pcib_device_ivars { 297172394Smarius PCIB_IVAR_DOMAIN, 29865176Sdfr PCIB_IVAR_BUS 29947339Sgallatin}; 30047339Sgallatin 301165217Sjhb#define PCIB_ACCESSOR(var, ivar, type) \ 302102144Smux __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 30347339Sgallatin 304172394SmariusPCIB_ACCESSOR(domain, DOMAIN, uint32_t) 305119266SimpPCIB_ACCESSOR(bus, BUS, uint32_t) 30647339Sgallatin 30766416Speter#undef PCIB_ACCESSOR 30866416Speter 30969953Smsmith/* 31098017Simp * PCI interrupt validation. Invalid interrupt values such as 0 or 128 31198017Simp * on i386 or other platforms should be mapped out in the MD pcireadconf 31298017Simp * code and not here, since the only MI invalid IRQ is 255. 31390554Smsmith */ 314165217Sjhb#define PCI_INVALID_IRQ 255 315165217Sjhb#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 31690554Smsmith 31790554Smsmith/* 31869953Smsmith * Convenience functions. 31969953Smsmith * 32069953Smsmith * These should be used in preference to manually manipulating 32169953Smsmith * configuration space. 32269953Smsmith */ 323113544Smdoddstatic __inline int 32473185Speterpci_enable_busmaster(device_t dev) 32573185Speter{ 326113544Smdodd return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 32773185Speter} 32845720Speter 329113544Smdoddstatic __inline int 33073185Speterpci_disable_busmaster(device_t dev) 33173185Speter{ 332113544Smdodd return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 33373185Speter} 33473185Speter 335113544Smdoddstatic __inline int 33673185Speterpci_enable_io(device_t dev, int space) 33773185Speter{ 338113544Smdodd return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 33973185Speter} 34073185Speter 341113544Smdoddstatic __inline int 34273185Speterpci_disable_io(device_t dev, int space) 34373185Speter{ 344113544Smdodd return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 34573185Speter} 34673185Speter 347163163Sjmgstatic __inline int 348163163Sjmgpci_get_vpd_ident(device_t dev, const char **identptr) 349163163Sjmg{ 350163163Sjmg return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 351163163Sjmg} 352163163Sjmg 353163163Sjmgstatic __inline int 354163163Sjmgpci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) 355163163Sjmg{ 356163163Sjmg return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); 357163163Sjmg} 358163163Sjmg 35969953Smsmith/* 360145651Smarcel * Check if the address range falls within the VGA defined address range(s) 361145651Smarcel */ 362145651Smarcelstatic __inline int 363145651Smarcelpci_is_vga_ioport_range(u_long start, u_long end) 364145651Smarcel{ 365145651Smarcel 366145651Smarcel return (((start >= 0x3b0 && end <= 0x3bb) || 367145651Smarcel (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 368145651Smarcel} 369145651Smarcel 370145651Smarcelstatic __inline int 371145651Smarcelpci_is_vga_memory_range(u_long start, u_long end) 372145651Smarcel{ 373145651Smarcel 374145651Smarcel return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 375145651Smarcel} 376145651Smarcel 377145651Smarcel/* 37869953Smsmith * PCI power states are as defined by ACPI: 37969953Smsmith * 38069953Smsmith * D0 State in which device is on and running. It is receiving full 38169953Smsmith * power from the system and delivering full functionality to the user. 38269953Smsmith * D1 Class-specific low-power state in which device context may or may not 38369953Smsmith * be lost. Buses in D1 cannot do anything to the bus that would force 384160964Syar * devices on that bus to lose context. 38569953Smsmith * D2 Class-specific low-power state in which device context may or may 38669953Smsmith * not be lost. Attains greater power savings than D1. Buses in D2 387160964Syar * can cause devices on that bus to lose some context. Devices in D2 38869953Smsmith * must be prepared for the bus to be in D2 or higher. 38969953Smsmith * D3 State in which the device is off and not running. Device context is 39069953Smsmith * lost. Power can be removed from the device. 39169953Smsmith */ 392165217Sjhb#define PCI_POWERSTATE_D0 0 393165217Sjhb#define PCI_POWERSTATE_D1 1 394165217Sjhb#define PCI_POWERSTATE_D2 2 395165217Sjhb#define PCI_POWERSTATE_D3 3 396165217Sjhb#define PCI_POWERSTATE_UNKNOWN -1 39726159Sse 39873185Speterstatic __inline int 39973185Speterpci_set_powerstate(device_t dev, int state) 40073185Speter{ 40173185Speter return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 40273185Speter} 40358287Speter 40473185Speterstatic __inline int 40573185Speterpci_get_powerstate(device_t dev) 40673185Speter{ 40773185Speter return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 40873185Speter} 40973185Speter 410153560Sjhbstatic __inline int 411219865Sjhbpci_find_cap(device_t dev, int capability, int *capreg) 412219865Sjhb{ 413219865Sjhb return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 414219865Sjhb} 415219865Sjhb 416219865Sjhbstatic __inline int 417153560Sjhbpci_find_extcap(device_t dev, int capability, int *capreg) 418153560Sjhb{ 419219865Sjhb return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 420153560Sjhb} 421153560Sjhb 422164264Sjhbstatic __inline int 423164264Sjhbpci_alloc_msi(device_t dev, int *count) 424164264Sjhb{ 425164264Sjhb return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 426164264Sjhb} 427164264Sjhb 428164264Sjhbstatic __inline int 429166176Sjhbpci_alloc_msix(device_t dev, int *count) 430166176Sjhb{ 431166176Sjhb return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 432166176Sjhb} 433166176Sjhb 434166176Sjhbstatic __inline int 435169221Sjhbpci_remap_msix(device_t dev, int count, const u_int *vectors) 436166176Sjhb{ 437169221Sjhb return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 438166176Sjhb} 439166176Sjhb 440166176Sjhbstatic __inline int 441164264Sjhbpci_release_msi(device_t dev) 442164264Sjhb{ 443164264Sjhb return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 444164264Sjhb} 445164264Sjhb 446164264Sjhbstatic __inline int 447164264Sjhbpci_msi_count(device_t dev) 448164264Sjhb{ 449164264Sjhb return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 450164264Sjhb} 451164264Sjhb 452166176Sjhbstatic __inline int 453166176Sjhbpci_msix_count(device_t dev) 454166176Sjhb{ 455166176Sjhb return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 456166176Sjhb} 457166176Sjhb 458119266Simpdevice_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 459172394Smariusdevice_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 460119266Simpdevice_t pci_find_device(uint16_t, uint16_t); 461223885Skibdevice_t pci_find_class(uint8_t class, uint8_t subclass); 462164264Sjhb 463169221Sjhb/* Can be used by drivers to manage the MSI-X table. */ 464164264Sjhbint pci_pending_msix(device_t dev, u_int index); 465169221Sjhb 466165228Sjhbint pci_msi_device_blacklisted(device_t dev); 467253273Smariusint pci_msix_device_blacklisted(device_t dev); 468164264Sjhb 469180753Sluoqivoid pci_ht_map_msi(device_t dev, uint64_t addr); 470180753Sluoqi 471203528Smavint pci_get_max_read_req(device_t dev); 472233379Sjhbvoid pci_restore_state(device_t dev); 473233379Sjhbvoid pci_save_state(device_t dev); 474203528Smavint pci_set_max_read_req(device_t dev, int size); 475203528Smav 47669953Smsmith#endif /* _SYS_BUS_H_ */ 47761047Speter 47869953Smsmith/* 47969953Smsmith * cdev switch for control device, initialised in generic PCI code 48069953Smsmith */ 48169953Smsmithextern struct cdevsw pcicdev; 48258287Speter 48369953Smsmith/* 48469953Smsmith * List of all PCI devices, generation count for the list. 48569953Smsmith */ 48688184SmdoddSTAILQ_HEAD(devlist, pci_devinfo); 48712453Sbde 48888184Smdoddextern struct devlist pci_devq; 489119266Simpextern uint32_t pci_generation; 49088184Smdodd 491220195Sjhbstruct pci_map *pci_find_bar(device_t dev, int reg); 492220195Sjhbint pci_bar_enabled(device_t dev, struct pci_map *pm); 493262134Sjhbstruct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 494220195Sjhb 495261622Sdumbbell#define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 496261622Sdumbbell#define VGA_PCI_BIOS_SHADOW_SIZE 131072 497261622Sdumbbell 498261622Sdumbbellint vga_pci_is_boot_display(device_t dev); 499261622Sdumbbellvoid * vga_pci_map_bios(device_t dev, size_t *size); 500261622Sdumbbellvoid vga_pci_unmap_bios(device_t dev, void *bios); 501261622Sdumbbell 50239231Sgibbs#endif /* _PCIVAR_H_ */ 503