1171095Ssam/*- 2171095Ssam * Copyright (c) 2002-2007 Neterion, Inc. 3171095Ssam * All rights reserved. 4171095Ssam * 5171095Ssam * Redistribution and use in source and binary forms, with or without 6171095Ssam * modification, are permitted provided that the following conditions 7171095Ssam * are met: 8171095Ssam * 1. Redistributions of source code must retain the above copyright 9171095Ssam * notice, this list of conditions and the following disclaimer. 10171095Ssam * 2. Redistributions in binary form must reproduce the above copyright 11171095Ssam * notice, this list of conditions and the following disclaimer in the 12171095Ssam * documentation and/or other materials provided with the distribution. 13171095Ssam * 14171095Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15171095Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16171095Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17171095Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18171095Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19171095Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20171095Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21171095Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22171095Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23171095Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24171095Ssam * SUCH DAMAGE. 25171095Ssam * 26171095Ssam * $FreeBSD$ 27171095Ssam */ 28171095Ssam 29171095Ssam#ifndef XGE_HAL_FIFO_H 30171095Ssam#define XGE_HAL_FIFO_H 31171095Ssam 32171095Ssam#include <dev/nxge/include/xgehal-channel.h> 33171095Ssam#include <dev/nxge/include/xgehal-config.h> 34171095Ssam#include <dev/nxge/include/xgehal-mm.h> 35171095Ssam 36171095Ssam__EXTERN_BEGIN_DECLS 37171095Ssam 38171095Ssam/* HW fifo configuration */ 39173139Srwatson#define XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD 65 40173139Srwatson#define XGE_HAL_FIFO_MAX_WRR 5 41173139Srwatson#define XGE_HAL_FIFO_MAX_PARTITION 4 42173139Srwatson#define XGE_HAL_FIFO_MAX_WRR_STATE 36 43173139Srwatson#define XGE_HAL_FIFO_HW_PAIR_OFFSET 0x20000 44171095Ssam 45171095Ssam/* HW FIFO Weight Calender */ 46171095Ssam#define XGE_HAL_FIFO_WRR_0 0x0706050407030602ULL 47171095Ssam#define XGE_HAL_FIFO_WRR_1 0x0507040601070503ULL 48171095Ssam#define XGE_HAL_FIFO_WRR_2 0x0604070205060700ULL 49171095Ssam#define XGE_HAL_FIFO_WRR_3 0x0403060705010207ULL 50171095Ssam#define XGE_HAL_FIFO_WRR_4 0x0604050300000000ULL 51171095Ssam/* 52171095Ssam * xge_hal_fifo_hw_pair_t 53171095Ssam * 54171095Ssam * Represent a single fifo in the BAR1 memory space. 55171095Ssam */ 56171095Ssamtypedef struct { 57171095Ssam u64 txdl_pointer; /* offset 0x0 */ 58171095Ssam 59171095Ssam u64 reserved[2]; 60171095Ssam 61171095Ssam u64 list_control; /* offset 0x18 */ 62171095Ssam#define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) 63171095Ssam#define XGE_HAL_TX_FIFO_FIRST_LIST BIT(14) 64171095Ssam#define XGE_HAL_TX_FIFO_LAST_LIST BIT(15) 65171095Ssam#define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) 66171095Ssam#define XGE_HAL_TX_FIFO_SPECIAL_FUNC BIT(23) 67171095Ssam#define XGE_HAL_TX_FIFO_NO_SNOOP(n) vBIT(n,30,2) 68171095Ssam} xge_hal_fifo_hw_pair_t; 69171095Ssam 70171095Ssam 71171095Ssam/* Bad TxDL transfer codes */ 72173139Srwatson#define XGE_HAL_TXD_T_CODE_OK 0x0 73173139Srwatson#define XGE_HAL_TXD_T_CODE_UNUSED_1 0x1 74173139Srwatson#define XGE_HAL_TXD_T_CODE_ABORT_BUFFER 0x2 75173139Srwatson#define XGE_HAL_TXD_T_CODE_ABORT_DTOR 0x3 76173139Srwatson#define XGE_HAL_TXD_T_CODE_UNUSED_5 0x5 77173139Srwatson#define XGE_HAL_TXD_T_CODE_PARITY 0x7 78173139Srwatson#define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK 0xA 79173139Srwatson#define XGE_HAL_TXD_T_CODE_GENERAL_ERR 0xF 80171095Ssam 81171095Ssam 82171095Ssam/** 83171095Ssam * struct xge_hal_fifo_txd_t - TxD. 84171095Ssam * @control_1: Control_1. 85171095Ssam * @control_2: Control_2. 86171095Ssam * @buffer_pointer: Buffer_Address. 87171095Ssam * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the Xframe 88171095Ssam * descriptor prior to posting the latter on the channel 89171095Ssam * via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post(). 90171095Ssam * The %host_control is returned as is to the ULD with each 91171095Ssam * completed descriptor. 92171095Ssam * 93171095Ssam * Transmit descriptor (TxD).Fifo descriptor contains configured number 94171095Ssam * (list) of TxDs. * For more details please refer to Xframe User Guide, 95171095Ssam * Section 5.4.2 "Transmit Descriptor (TxD) Format". 96171095Ssam */ 97171095Ssamtypedef struct xge_hal_fifo_txd_t { 98171095Ssam u64 control_1; 99171095Ssam#define XGE_HAL_TXD_LIST_OWN_XENA BIT(7) 100173139Srwatson#define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 101171095Ssam#define XGE_HAL_GET_TXD_T_CODE(val) ((val & XGE_HAL_TXD_T_CODE)>>48) 102171095Ssam#define XGE_HAL_SET_TXD_T_CODE(x, val) (x |= (((u64)val & 0xF) << 48)) 103171095Ssam#define XGE_HAL_TXD_GATHER_CODE (BIT(22) | BIT(23)) 104171095Ssam#define XGE_HAL_TXD_GATHER_CODE_FIRST BIT(22) 105171095Ssam#define XGE_HAL_TXD_GATHER_CODE_LAST BIT(23) 106173139Srwatson#define XGE_HAL_TXD_NO_LSO 0 107173139Srwatson#define XGE_HAL_TXD_UDF_COF 1 108173139Srwatson#define XGE_HAL_TXD_TCP_LSO 2 109173139Srwatson#define XGE_HAL_TXD_UDP_LSO 3 110171095Ssam#define XGE_HAL_TXD_LSO_COF_CTRL(val) vBIT(val,30,2) 111171095Ssam#define XGE_HAL_TXD_TCP_LSO_MSS(val) vBIT(val,34,14) 112171095Ssam#define XGE_HAL_TXD_BUFFER0_SIZE(val) vBIT(val,48,16) 113171095Ssam#define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32) 114171095Ssam u64 control_2; 115171095Ssam#define XGE_HAL_TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7)) 116171095Ssam#define XGE_HAL_TXD_TX_CKO_IPV4_EN BIT(5) 117171095Ssam#define XGE_HAL_TXD_TX_CKO_TCP_EN BIT(6) 118171095Ssam#define XGE_HAL_TXD_TX_CKO_UDP_EN BIT(7) 119171095Ssam#define XGE_HAL_TXD_VLAN_ENABLE BIT(15) 120171095Ssam#define XGE_HAL_TXD_VLAN_TAG(val) vBIT(val,16,16) 121171095Ssam#define XGE_HAL_TXD_INT_NUMBER(val) vBIT(val,34,6) 122171095Ssam#define XGE_HAL_TXD_INT_TYPE_PER_LIST BIT(47) 123171095Ssam#define XGE_HAL_TXD_INT_TYPE_UTILZ BIT(46) 124171095Ssam#define XGE_HAL_TXD_SET_MARKER vBIT(0x6,0,4) 125171095Ssam 126171095Ssam u64 buffer_pointer; 127171095Ssam 128171095Ssam u64 host_control; 129171095Ssam 130171095Ssam} xge_hal_fifo_txd_t; 131171095Ssam 132171095Ssamtypedef xge_hal_fifo_txd_t* xge_hal_fifo_txdl_t; 133171095Ssam 134171095Ssam/** 135171095Ssam * struct xge_hal_fifo_t - Fifo channel. 136171095Ssam * @channel: Channel "base" of this fifo, the common part of all HAL 137171095Ssam * channels. 138171095Ssam * @post_lock_ptr: Points to a lock that serializes (pointer, control) PIOs. 139171095Ssam * Note that for Xena the serialization is done across all device 140171095Ssam * fifos. 141171095Ssam * @hw_pair: Per-fifo (Pointer, Control) pair used to send descriptors to the 142171095Ssam * Xframe hardware (for details see Xframe user guide). 143171095Ssam * @config: Fifo configuration, part of device configuration 144171095Ssam * (see xge_hal_device_config_t{}). 145171095Ssam * @no_snoop_bits: See xge_hal_fifo_config_t{}. 146171095Ssam * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock. 147171095Ssam * on TxDL please refer to Xframe UG. 148171095Ssam * @interrupt_type: FIXME: to-be-defined. 149171095Ssam * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus 150171095Ssam * per-TxDL HAL private space (xge_hal_fifo_txdl_priv_t). 151171095Ssam * @priv_size: Per-Tx descriptor space reserved for upper-layer driver 152171095Ssam * usage. 153171095Ssam * @mempool: Memory pool, from which descriptors get allocated. 154171095Ssam * @align_size: TBD 155171095Ssam * 156171095Ssam * Fifo channel. 157171095Ssam * Note: The structure is cache line aligned. 158171095Ssam */ 159171095Ssamtypedef struct xge_hal_fifo_t { 160173139Srwatson xge_hal_channel_t channel; 161173139Srwatson spinlock_t *post_lock_ptr; 162173139Srwatson xge_hal_fifo_hw_pair_t *hw_pair; 163173139Srwatson xge_hal_fifo_config_t *config; 164173139Srwatson int no_snoop_bits; 165173139Srwatson int txdl_per_memblock; 166173139Srwatson u64 interrupt_type; 167173139Srwatson int txdl_size; 168173139Srwatson int priv_size; 169173139Srwatson xge_hal_mempool_t *mempool; 170173139Srwatson int align_size; 171171095Ssam} __xge_os_attr_cacheline_aligned xge_hal_fifo_t; 172171095Ssam 173171095Ssam/** 174171095Ssam * struct xge_hal_fifo_txdl_priv_t - Transmit descriptor HAL-private 175171095Ssam * data. 176171095Ssam * @dma_addr: DMA (mapped) address of _this_ descriptor. 177171095Ssam * @dma_handle: DMA handle used to map the descriptor onto device. 178171095Ssam * @dma_offset: Descriptor's offset in the memory block. HAL allocates 179171095Ssam * descriptors in memory blocks (see 180171095Ssam * xge_hal_fifo_config_t{}) 181171095Ssam * Each memblock is a contiguous block of DMA-able memory. 182171095Ssam * @frags: Total number of fragments (that is, contiguous data buffers) 183171095Ssam * carried by this TxDL. 184171095Ssam * @align_vaddr_start: (TODO). 185171095Ssam * @align_vaddr: Virtual address of the per-TxDL area in memory used for 186171095Ssam * alignement. Used to place one or more mis-aligned fragments 187171095Ssam * (the maximum defined by configration variable 188171095Ssam * @max_aligned_frags). 189171095Ssam * @align_dma_addr: DMA address translated from the @align_vaddr. 190171095Ssam * @align_dma_handle: DMA handle that corresponds to @align_dma_addr. 191171095Ssam * @align_dma_acch: DMA access handle corresponds to @align_dma_addr. 192171095Ssam * @align_dma_offset: The current offset into the @align_vaddr area. 193171095Ssam * Grows while filling the descriptor, gets reset. 194171095Ssam * @align_used_frags: (TODO). 195171095Ssam * @alloc_frags: Total number of fragments allocated. 196171095Ssam * @dang_frags: Number of fragments kept from release until this TxDL is freed. 197171095Ssam * @bytes_sent: TODO 198171095Ssam * @unused: TODO 199171095Ssam * @dang_txdl: (TODO). 200171095Ssam * @next_txdl_priv: (TODO). 201171095Ssam * @first_txdp: (TODO). 202171095Ssam * @dang_dtrh: Pointer to TxDL (list) kept from release until this TxDL 203171095Ssam * is freed. 204171095Ssam * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous 205171095Ssam * TxDL list. 206171095Ssam * @dtrh: Corresponding dtrh to this TxDL. 207171095Ssam * @memblock: Pointer to the TxDL memory block or memory page. 208171095Ssam * on the next send operation. 209171095Ssam * @dma_object: DMA address and handle of the memory block that contains 210171095Ssam * the descriptor. This member is used only in the "checked" 211171095Ssam * version of the HAL (to enforce certain assertions); 212171095Ssam * otherwise it gets compiled out. 213171095Ssam * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 214171095Ssam * 215171095Ssam * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA 216171095Ssam * information associated with the descriptor. Note that ULD can ask HAL 217171095Ssam * to allocate additional per-descriptor space for its own (ULD-specific) 218171095Ssam * purposes. 219171095Ssam * 220171095Ssam * See also: xge_hal_ring_rxd_priv_t{}. 221171095Ssam */ 222171095Ssamtypedef struct xge_hal_fifo_txdl_priv_t { 223173139Srwatson dma_addr_t dma_addr; 224173139Srwatson pci_dma_h dma_handle; 225173139Srwatson ptrdiff_t dma_offset; 226173139Srwatson int frags; 227173139Srwatson char *align_vaddr_start; 228173139Srwatson char *align_vaddr; 229173139Srwatson dma_addr_t align_dma_addr; 230173139Srwatson pci_dma_h align_dma_handle; 231173139Srwatson pci_dma_acc_h align_dma_acch; 232173139Srwatson ptrdiff_t align_dma_offset; 233173139Srwatson int align_used_frags; 234173139Srwatson int alloc_frags; 235173139Srwatson int dang_frags; 236173139Srwatson unsigned int bytes_sent; 237173139Srwatson int unused; 238173139Srwatson xge_hal_fifo_txd_t *dang_txdl; 239173139Srwatson struct xge_hal_fifo_txdl_priv_t *next_txdl_priv; 240173139Srwatson xge_hal_fifo_txd_t *first_txdp; 241173139Srwatson void *memblock; 242171095Ssam#ifdef XGE_DEBUG_ASSERT 243173139Srwatson xge_hal_mempool_dma_t *dma_object; 244171095Ssam#endif 245171095Ssam#ifdef XGE_OS_MEMORY_CHECK 246173139Srwatson int allocated; 247171095Ssam#endif 248171095Ssam} xge_hal_fifo_txdl_priv_t; 249171095Ssam 250171095Ssam/** 251171095Ssam * xge_hal_fifo_get_max_frags_cnt - Return the max fragments allocated 252171095Ssam * for the fifo. 253171095Ssam * @channelh: Channel handle. 254171095Ssam */ 255171095Ssamstatic inline int 256171095Ssamxge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh) 257171095Ssam{ 258171095Ssam return ((xge_hal_fifo_t *)channelh)->config->max_frags; 259171095Ssam} 260171095Ssam/* ========================= FIFO PRIVATE API ============================= */ 261171095Ssam 262171095Ssamxge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh, 263173139Srwatson xge_hal_channel_attr_t *attr); 264171095Ssam 265171095Ssamvoid __hal_fifo_close(xge_hal_channel_h channelh); 266171095Ssam 267171095Ssamvoid __hal_fifo_hw_initialize(xge_hal_device_h hldev); 268171095Ssam 269171095Ssamxge_hal_status_e 270171095Ssam__hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 271171095Ssam 272171095Ssamvoid 273171095Ssam__hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 274171095Ssam 275171095Ssam#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_FIFO) 276171095Ssam#define __HAL_STATIC_FIFO 277171095Ssam#define __HAL_INLINE_FIFO 278171095Ssam 279171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t* 280171095Ssam__hal_fifo_txdl_priv(xge_hal_dtr_h dtrh); 281171095Ssam 282171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 283171095Ssam__hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 284173139Srwatson u64 ctrl_1); 285171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 286171095Ssam__hal_fifo_txdl_restore_many(xge_hal_channel_h channelh, 287173139Srwatson xge_hal_fifo_txd_t *txdp, int txdl_count); 288171095Ssam 289171095Ssam/* ========================= FIFO PUBLIC API ============================== */ 290171095Ssam 291171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 292171095Ssamxge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 293171095Ssam 294173139Srwatson__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 295173139Srwatsonxge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 296173139Srwatson const int frags); 297173139Srwatson 298171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void* 299171095Ssamxge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh); 300171095Ssam 301171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO int 302171095Ssamxge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh); 303171095Ssam 304171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 305171095Ssamxge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size, 306173139Srwatson xge_hal_dtr_h dtr_sp); 307171095Ssam 308171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 309173139Srwatsonxge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 310171095Ssam 311171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 312171095Ssamxge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num, 313173139Srwatson xge_hal_dtr_h dtrs[]); 314171095Ssam 315171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 316171095Ssamxge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 317173139Srwatson u8 *t_code); 318171095Ssam 319171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 320173139Srwatsonxge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr); 321171095Ssam 322171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 323171095Ssamxge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 324173139Srwatson int frag_idx, dma_addr_t dma_pointer, int size); 325171095Ssam 326171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 327171095Ssamxge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh, 328173139Srwatson xge_hal_dtr_h dtrh, int frag_idx, void *vaddr, 329173139Srwatson dma_addr_t dma_pointer, int size, int misaligned_size); 330171095Ssam 331171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 332171095Ssamxge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 333173139Srwatson void *vaddr, int size); 334171095Ssam 335171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 336171095Ssamxge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 337173139Srwatson int frag_idx); 338171095Ssam 339171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 340171095Ssamxge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss); 341171095Ssam 342171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 343171095Ssamxge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits); 344171095Ssam 345171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 346173139Srwatsonxge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag); 347171095Ssam 348171095Ssam__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 349171095Ssamxge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh); 350171095Ssam 351171095Ssam#else /* XGE_FASTPATH_EXTERN */ 352171095Ssam#define __HAL_STATIC_FIFO static 353171095Ssam#define __HAL_INLINE_FIFO inline 354171095Ssam#include <dev/nxge/xgehal/xgehal-fifo-fp.c> 355171095Ssam#endif /* XGE_FASTPATH_INLINE */ 356171095Ssam 357171095Ssam__EXTERN_END_DECLS 358171095Ssam 359171095Ssam#endif /* XGE_HAL_FIFO_H */ 360