1/*- 2 * Copyright (c) 2002-2007 Neterion, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef XGE_HAL_FIFO_H 30#define XGE_HAL_FIFO_H 31 32#include <dev/nxge/include/xgehal-channel.h> 33#include <dev/nxge/include/xgehal-config.h> 34#include <dev/nxge/include/xgehal-mm.h> 35 36__EXTERN_BEGIN_DECLS 37 38/* HW fifo configuration */ 39#define XGE_HAL_FIFO_INT_PER_LIST_THRESHOLD 65 40#define XGE_HAL_FIFO_MAX_WRR 5 41#define XGE_HAL_FIFO_MAX_PARTITION 4 42#define XGE_HAL_FIFO_MAX_WRR_STATE 36 43#define XGE_HAL_FIFO_HW_PAIR_OFFSET 0x20000 44 45/* HW FIFO Weight Calender */ 46#define XGE_HAL_FIFO_WRR_0 0x0706050407030602ULL 47#define XGE_HAL_FIFO_WRR_1 0x0507040601070503ULL 48#define XGE_HAL_FIFO_WRR_2 0x0604070205060700ULL 49#define XGE_HAL_FIFO_WRR_3 0x0403060705010207ULL 50#define XGE_HAL_FIFO_WRR_4 0x0604050300000000ULL 51/* 52 * xge_hal_fifo_hw_pair_t 53 * 54 * Represent a single fifo in the BAR1 memory space. 55 */ 56typedef struct { 57 u64 txdl_pointer; /* offset 0x0 */ 58 59 u64 reserved[2]; 60 61 u64 list_control; /* offset 0x18 */ 62#define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) 63#define XGE_HAL_TX_FIFO_FIRST_LIST BIT(14) 64#define XGE_HAL_TX_FIFO_LAST_LIST BIT(15) 65#define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) 66#define XGE_HAL_TX_FIFO_SPECIAL_FUNC BIT(23) 67#define XGE_HAL_TX_FIFO_NO_SNOOP(n) vBIT(n,30,2) 68} xge_hal_fifo_hw_pair_t; 69 70 71/* Bad TxDL transfer codes */ 72#define XGE_HAL_TXD_T_CODE_OK 0x0 73#define XGE_HAL_TXD_T_CODE_UNUSED_1 0x1 74#define XGE_HAL_TXD_T_CODE_ABORT_BUFFER 0x2 75#define XGE_HAL_TXD_T_CODE_ABORT_DTOR 0x3 76#define XGE_HAL_TXD_T_CODE_UNUSED_5 0x5 77#define XGE_HAL_TXD_T_CODE_PARITY 0x7 78#define XGE_HAL_TXD_T_CODE_LOSS_OF_LINK 0xA 79#define XGE_HAL_TXD_T_CODE_GENERAL_ERR 0xF 80 81 82/** 83 * struct xge_hal_fifo_txd_t - TxD. 84 * @control_1: Control_1. 85 * @control_2: Control_2. 86 * @buffer_pointer: Buffer_Address. 87 * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the Xframe 88 * descriptor prior to posting the latter on the channel 89 * via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post(). 90 * The %host_control is returned as is to the ULD with each 91 * completed descriptor. 92 * 93 * Transmit descriptor (TxD).Fifo descriptor contains configured number 94 * (list) of TxDs. * For more details please refer to Xframe User Guide, 95 * Section 5.4.2 "Transmit Descriptor (TxD) Format". 96 */ 97typedef struct xge_hal_fifo_txd_t { 98 u64 control_1; 99#define XGE_HAL_TXD_LIST_OWN_XENA BIT(7) 100#define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 101#define XGE_HAL_GET_TXD_T_CODE(val) ((val & XGE_HAL_TXD_T_CODE)>>48) 102#define XGE_HAL_SET_TXD_T_CODE(x, val) (x |= (((u64)val & 0xF) << 48)) 103#define XGE_HAL_TXD_GATHER_CODE (BIT(22) | BIT(23)) 104#define XGE_HAL_TXD_GATHER_CODE_FIRST BIT(22) 105#define XGE_HAL_TXD_GATHER_CODE_LAST BIT(23) 106#define XGE_HAL_TXD_NO_LSO 0 107#define XGE_HAL_TXD_UDF_COF 1 108#define XGE_HAL_TXD_TCP_LSO 2 109#define XGE_HAL_TXD_UDP_LSO 3 110#define XGE_HAL_TXD_LSO_COF_CTRL(val) vBIT(val,30,2) 111#define XGE_HAL_TXD_TCP_LSO_MSS(val) vBIT(val,34,14) 112#define XGE_HAL_TXD_BUFFER0_SIZE(val) vBIT(val,48,16) 113#define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32) 114 u64 control_2; 115#define XGE_HAL_TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7)) 116#define XGE_HAL_TXD_TX_CKO_IPV4_EN BIT(5) 117#define XGE_HAL_TXD_TX_CKO_TCP_EN BIT(6) 118#define XGE_HAL_TXD_TX_CKO_UDP_EN BIT(7) 119#define XGE_HAL_TXD_VLAN_ENABLE BIT(15) 120#define XGE_HAL_TXD_VLAN_TAG(val) vBIT(val,16,16) 121#define XGE_HAL_TXD_INT_NUMBER(val) vBIT(val,34,6) 122#define XGE_HAL_TXD_INT_TYPE_PER_LIST BIT(47) 123#define XGE_HAL_TXD_INT_TYPE_UTILZ BIT(46) 124#define XGE_HAL_TXD_SET_MARKER vBIT(0x6,0,4) 125 126 u64 buffer_pointer; 127 128 u64 host_control; 129 130} xge_hal_fifo_txd_t; 131 132typedef xge_hal_fifo_txd_t* xge_hal_fifo_txdl_t; 133 134/** 135 * struct xge_hal_fifo_t - Fifo channel. 136 * @channel: Channel "base" of this fifo, the common part of all HAL 137 * channels. 138 * @post_lock_ptr: Points to a lock that serializes (pointer, control) PIOs. 139 * Note that for Xena the serialization is done across all device 140 * fifos. 141 * @hw_pair: Per-fifo (Pointer, Control) pair used to send descriptors to the 142 * Xframe hardware (for details see Xframe user guide). 143 * @config: Fifo configuration, part of device configuration 144 * (see xge_hal_device_config_t{}). 145 * @no_snoop_bits: See xge_hal_fifo_config_t{}. 146 * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock. 147 * on TxDL please refer to Xframe UG. 148 * @interrupt_type: FIXME: to-be-defined. 149 * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus 150 * per-TxDL HAL private space (xge_hal_fifo_txdl_priv_t). 151 * @priv_size: Per-Tx descriptor space reserved for upper-layer driver 152 * usage. 153 * @mempool: Memory pool, from which descriptors get allocated. 154 * @align_size: TBD 155 * 156 * Fifo channel. 157 * Note: The structure is cache line aligned. 158 */ 159typedef struct xge_hal_fifo_t { 160 xge_hal_channel_t channel; 161 spinlock_t *post_lock_ptr; 162 xge_hal_fifo_hw_pair_t *hw_pair; 163 xge_hal_fifo_config_t *config; 164 int no_snoop_bits; 165 int txdl_per_memblock; 166 u64 interrupt_type; 167 int txdl_size; 168 int priv_size; 169 xge_hal_mempool_t *mempool; 170 int align_size; 171} __xge_os_attr_cacheline_aligned xge_hal_fifo_t; 172 173/** 174 * struct xge_hal_fifo_txdl_priv_t - Transmit descriptor HAL-private 175 * data. 176 * @dma_addr: DMA (mapped) address of _this_ descriptor. 177 * @dma_handle: DMA handle used to map the descriptor onto device. 178 * @dma_offset: Descriptor's offset in the memory block. HAL allocates 179 * descriptors in memory blocks (see 180 * xge_hal_fifo_config_t{}) 181 * Each memblock is a contiguous block of DMA-able memory. 182 * @frags: Total number of fragments (that is, contiguous data buffers) 183 * carried by this TxDL. 184 * @align_vaddr_start: (TODO). 185 * @align_vaddr: Virtual address of the per-TxDL area in memory used for 186 * alignement. Used to place one or more mis-aligned fragments 187 * (the maximum defined by configration variable 188 * @max_aligned_frags). 189 * @align_dma_addr: DMA address translated from the @align_vaddr. 190 * @align_dma_handle: DMA handle that corresponds to @align_dma_addr. 191 * @align_dma_acch: DMA access handle corresponds to @align_dma_addr. 192 * @align_dma_offset: The current offset into the @align_vaddr area. 193 * Grows while filling the descriptor, gets reset. 194 * @align_used_frags: (TODO). 195 * @alloc_frags: Total number of fragments allocated. 196 * @dang_frags: Number of fragments kept from release until this TxDL is freed. 197 * @bytes_sent: TODO 198 * @unused: TODO 199 * @dang_txdl: (TODO). 200 * @next_txdl_priv: (TODO). 201 * @first_txdp: (TODO). 202 * @dang_dtrh: Pointer to TxDL (list) kept from release until this TxDL 203 * is freed. 204 * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous 205 * TxDL list. 206 * @dtrh: Corresponding dtrh to this TxDL. 207 * @memblock: Pointer to the TxDL memory block or memory page. 208 * on the next send operation. 209 * @dma_object: DMA address and handle of the memory block that contains 210 * the descriptor. This member is used only in the "checked" 211 * version of the HAL (to enforce certain assertions); 212 * otherwise it gets compiled out. 213 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 214 * 215 * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA 216 * information associated with the descriptor. Note that ULD can ask HAL 217 * to allocate additional per-descriptor space for its own (ULD-specific) 218 * purposes. 219 * 220 * See also: xge_hal_ring_rxd_priv_t{}. 221 */ 222typedef struct xge_hal_fifo_txdl_priv_t { 223 dma_addr_t dma_addr; 224 pci_dma_h dma_handle; 225 ptrdiff_t dma_offset; 226 int frags; 227 char *align_vaddr_start; 228 char *align_vaddr; 229 dma_addr_t align_dma_addr; 230 pci_dma_h align_dma_handle; 231 pci_dma_acc_h align_dma_acch; 232 ptrdiff_t align_dma_offset; 233 int align_used_frags; 234 int alloc_frags; 235 int dang_frags; 236 unsigned int bytes_sent; 237 int unused; 238 xge_hal_fifo_txd_t *dang_txdl; 239 struct xge_hal_fifo_txdl_priv_t *next_txdl_priv; 240 xge_hal_fifo_txd_t *first_txdp; 241 void *memblock; 242#ifdef XGE_DEBUG_ASSERT 243 xge_hal_mempool_dma_t *dma_object; 244#endif 245#ifdef XGE_OS_MEMORY_CHECK 246 int allocated; 247#endif 248} xge_hal_fifo_txdl_priv_t; 249 250/** 251 * xge_hal_fifo_get_max_frags_cnt - Return the max fragments allocated 252 * for the fifo. 253 * @channelh: Channel handle. 254 */ 255static inline int 256xge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh) 257{ 258 return ((xge_hal_fifo_t *)channelh)->config->max_frags; 259} 260/* ========================= FIFO PRIVATE API ============================= */ 261 262xge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh, 263 xge_hal_channel_attr_t *attr); 264 265void __hal_fifo_close(xge_hal_channel_h channelh); 266 267void __hal_fifo_hw_initialize(xge_hal_device_h hldev); 268 269xge_hal_status_e 270__hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 271 272void 273__hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 274 275#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_FIFO) 276#define __HAL_STATIC_FIFO 277#define __HAL_INLINE_FIFO 278 279__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t* 280__hal_fifo_txdl_priv(xge_hal_dtr_h dtrh); 281 282__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 283__hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 284 u64 ctrl_1); 285__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 286__hal_fifo_txdl_restore_many(xge_hal_channel_h channelh, 287 xge_hal_fifo_txd_t *txdp, int txdl_count); 288 289/* ========================= FIFO PUBLIC API ============================== */ 290 291__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 292xge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 293 294__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 295xge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 296 const int frags); 297 298__HAL_STATIC_FIFO __HAL_INLINE_FIFO void* 299xge_hal_fifo_dtr_private(xge_hal_dtr_h dtrh); 300 301__HAL_STATIC_FIFO __HAL_INLINE_FIFO int 302xge_hal_fifo_dtr_buffer_cnt(xge_hal_dtr_h dtrh); 303 304__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 305xge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size, 306 xge_hal_dtr_h dtr_sp); 307 308__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 309xge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 310 311__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 312xge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num, 313 xge_hal_dtr_h dtrs[]); 314 315__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 316xge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 317 u8 *t_code); 318 319__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 320xge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr); 321 322__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 323xge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 324 int frag_idx, dma_addr_t dma_pointer, int size); 325 326__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 327xge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh, 328 xge_hal_dtr_h dtrh, int frag_idx, void *vaddr, 329 dma_addr_t dma_pointer, int size, int misaligned_size); 330 331__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 332xge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 333 void *vaddr, int size); 334 335__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 336xge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 337 int frag_idx); 338 339__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 340xge_hal_fifo_dtr_mss_set(xge_hal_dtr_h dtrh, int mss); 341 342__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 343xge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits); 344 345__HAL_STATIC_FIFO __HAL_INLINE_FIFO void 346xge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag); 347 348__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_status_e 349xge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh); 350 351#else /* XGE_FASTPATH_EXTERN */ 352#define __HAL_STATIC_FIFO static 353#define __HAL_INLINE_FIFO inline 354#include <dev/nxge/xgehal/xgehal-fifo-fp.c> 355#endif /* XGE_FASTPATH_INLINE */ 356 357__EXTERN_END_DECLS 358 359#endif /* XGE_HAL_FIFO_H */ 360