1240616Sjimharris/*- 2265565Sjimharris * Copyright (C) 2012-2014 Intel Corporation 3240616Sjimharris * All rights reserved. 4240616Sjimharris * 5240616Sjimharris * Redistribution and use in source and binary forms, with or without 6240616Sjimharris * modification, are permitted provided that the following conditions 7240616Sjimharris * are met: 8240616Sjimharris * 1. Redistributions of source code must retain the above copyright 9240616Sjimharris * notice, this list of conditions and the following disclaimer. 10240616Sjimharris * 2. Redistributions in binary form must reproduce the above copyright 11240616Sjimharris * notice, this list of conditions and the following disclaimer in the 12240616Sjimharris * documentation and/or other materials provided with the distribution. 13240616Sjimharris * 14240616Sjimharris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15240616Sjimharris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16240616Sjimharris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17240616Sjimharris * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18240616Sjimharris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19240616Sjimharris * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20240616Sjimharris * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21240616Sjimharris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22240616Sjimharris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23240616Sjimharris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24240616Sjimharris * SUCH DAMAGE. 25240616Sjimharris */ 26240616Sjimharris 27240616Sjimharris#include <sys/cdefs.h> 28240616Sjimharris__FBSDID("$FreeBSD$"); 29240616Sjimharris 30240616Sjimharris#include <sys/param.h> 31252222Sjimharris#include <sys/systm.h> 32252222Sjimharris#include <sys/buf.h> 33240616Sjimharris#include <sys/bus.h> 34240616Sjimharris#include <sys/conf.h> 35240616Sjimharris#include <sys/ioccom.h> 36252222Sjimharris#include <sys/proc.h> 37240616Sjimharris#include <sys/smp.h> 38252222Sjimharris#include <sys/uio.h> 39240616Sjimharris 40240616Sjimharris#include <dev/pci/pcireg.h> 41240616Sjimharris#include <dev/pci/pcivar.h> 42240616Sjimharris 43240616Sjimharris#include "nvme_private.h" 44240616Sjimharris 45252222Sjimharrisstatic void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 46252222Sjimharris struct nvme_async_event_request *aer); 47240616Sjimharris 48240616Sjimharrisstatic int 49240616Sjimharrisnvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 50240616Sjimharris{ 51240616Sjimharris 52240616Sjimharris /* Chatham puts the NVMe MMRs behind BAR 2/3, not BAR 0/1. */ 53240616Sjimharris if (pci_get_devid(ctrlr->dev) == CHATHAM_PCI_ID) 54240616Sjimharris ctrlr->resource_id = PCIR_BAR(2); 55240616Sjimharris else 56240616Sjimharris ctrlr->resource_id = PCIR_BAR(0); 57240616Sjimharris 58240616Sjimharris ctrlr->resource = bus_alloc_resource(ctrlr->dev, SYS_RES_MEMORY, 59240616Sjimharris &ctrlr->resource_id, 0, ~0, 1, RF_ACTIVE); 60240616Sjimharris 61240616Sjimharris if(ctrlr->resource == NULL) { 62252222Sjimharris nvme_printf(ctrlr, "unable to allocate pci resource\n"); 63240616Sjimharris return (ENOMEM); 64240616Sjimharris } 65240616Sjimharris 66240616Sjimharris ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 67240616Sjimharris ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 68240616Sjimharris ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 69240616Sjimharris 70252222Sjimharris /* 71252222Sjimharris * The NVMe spec allows for the MSI-X table to be placed behind 72252222Sjimharris * BAR 4/5, separate from the control/doorbell registers. Always 73252222Sjimharris * try to map this bar, because it must be mapped prior to calling 74252222Sjimharris * pci_alloc_msix(). If the table isn't behind BAR 4/5, 75252222Sjimharris * bus_alloc_resource() will just return NULL which is OK. 76252222Sjimharris */ 77252222Sjimharris ctrlr->bar4_resource_id = PCIR_BAR(4); 78252222Sjimharris ctrlr->bar4_resource = bus_alloc_resource(ctrlr->dev, SYS_RES_MEMORY, 79252222Sjimharris &ctrlr->bar4_resource_id, 0, ~0, 1, RF_ACTIVE); 80252222Sjimharris 81240616Sjimharris return (0); 82240616Sjimharris} 83240616Sjimharris 84240616Sjimharris#ifdef CHATHAM2 85240616Sjimharrisstatic int 86240616Sjimharrisnvme_ctrlr_allocate_chatham_bar(struct nvme_controller *ctrlr) 87240616Sjimharris{ 88240616Sjimharris 89240616Sjimharris ctrlr->chatham_resource_id = PCIR_BAR(CHATHAM_CONTROL_BAR); 90240616Sjimharris ctrlr->chatham_resource = bus_alloc_resource(ctrlr->dev, 91240616Sjimharris SYS_RES_MEMORY, &ctrlr->chatham_resource_id, 0, ~0, 1, 92240616Sjimharris RF_ACTIVE); 93240616Sjimharris 94240616Sjimharris if(ctrlr->chatham_resource == NULL) { 95252222Sjimharris nvme_printf(ctrlr, "unable to alloc pci resource\n"); 96240616Sjimharris return (ENOMEM); 97240616Sjimharris } 98240616Sjimharris 99240616Sjimharris ctrlr->chatham_bus_tag = rman_get_bustag(ctrlr->chatham_resource); 100240616Sjimharris ctrlr->chatham_bus_handle = 101240616Sjimharris rman_get_bushandle(ctrlr->chatham_resource); 102240616Sjimharris 103240616Sjimharris return (0); 104240616Sjimharris} 105240616Sjimharris 106240616Sjimharrisstatic void 107240616Sjimharrisnvme_ctrlr_setup_chatham(struct nvme_controller *ctrlr) 108240616Sjimharris{ 109240616Sjimharris uint64_t reg1, reg2, reg3; 110240616Sjimharris uint64_t temp1, temp2; 111240616Sjimharris uint32_t temp3; 112240616Sjimharris uint32_t use_flash_timings = 0; 113240616Sjimharris 114240616Sjimharris DELAY(10000); 115240616Sjimharris 116240616Sjimharris temp3 = chatham_read_4(ctrlr, 0x8080); 117240616Sjimharris 118240616Sjimharris device_printf(ctrlr->dev, "Chatham version: 0x%x\n", temp3); 119240616Sjimharris 120240616Sjimharris ctrlr->chatham_lbas = chatham_read_4(ctrlr, 0x8068) - 0x110; 121240616Sjimharris ctrlr->chatham_size = ctrlr->chatham_lbas * 512; 122240616Sjimharris 123252222Sjimharris device_printf(ctrlr->dev, "Chatham size: %jd\n", 124252222Sjimharris (intmax_t)ctrlr->chatham_size); 125240616Sjimharris 126240616Sjimharris reg1 = reg2 = reg3 = ctrlr->chatham_size - 1; 127240616Sjimharris 128240616Sjimharris TUNABLE_INT_FETCH("hw.nvme.use_flash_timings", &use_flash_timings); 129240616Sjimharris if (use_flash_timings) { 130240616Sjimharris device_printf(ctrlr->dev, "Chatham: using flash timings\n"); 131240616Sjimharris temp1 = 0x00001b58000007d0LL; 132240616Sjimharris temp2 = 0x000000cb00000131LL; 133240616Sjimharris } else { 134240616Sjimharris device_printf(ctrlr->dev, "Chatham: using DDR timings\n"); 135240616Sjimharris temp1 = temp2 = 0x0LL; 136240616Sjimharris } 137240616Sjimharris 138240616Sjimharris chatham_write_8(ctrlr, 0x8000, reg1); 139240616Sjimharris chatham_write_8(ctrlr, 0x8008, reg2); 140240616Sjimharris chatham_write_8(ctrlr, 0x8010, reg3); 141240616Sjimharris 142240616Sjimharris chatham_write_8(ctrlr, 0x8020, temp1); 143240616Sjimharris temp3 = chatham_read_4(ctrlr, 0x8020); 144240616Sjimharris 145240616Sjimharris chatham_write_8(ctrlr, 0x8028, temp2); 146240616Sjimharris temp3 = chatham_read_4(ctrlr, 0x8028); 147240616Sjimharris 148240616Sjimharris chatham_write_8(ctrlr, 0x8030, temp1); 149240616Sjimharris chatham_write_8(ctrlr, 0x8038, temp2); 150240616Sjimharris chatham_write_8(ctrlr, 0x8040, temp1); 151240616Sjimharris chatham_write_8(ctrlr, 0x8048, temp2); 152240616Sjimharris chatham_write_8(ctrlr, 0x8050, temp1); 153240616Sjimharris chatham_write_8(ctrlr, 0x8058, temp2); 154240616Sjimharris 155240616Sjimharris DELAY(10000); 156240616Sjimharris} 157240616Sjimharris 158240616Sjimharrisstatic void 159240616Sjimharrisnvme_chatham_populate_cdata(struct nvme_controller *ctrlr) 160240616Sjimharris{ 161240616Sjimharris struct nvme_controller_data *cdata; 162240616Sjimharris 163240616Sjimharris cdata = &ctrlr->cdata; 164240616Sjimharris 165240616Sjimharris cdata->vid = 0x8086; 166240616Sjimharris cdata->ssvid = 0x2011; 167240616Sjimharris 168240616Sjimharris /* 169240616Sjimharris * Chatham2 puts garbage data in these fields when we 170240616Sjimharris * invoke IDENTIFY_CONTROLLER, so we need to re-zero 171240616Sjimharris * the fields before calling bcopy(). 172240616Sjimharris */ 173240616Sjimharris memset(cdata->sn, 0, sizeof(cdata->sn)); 174240616Sjimharris memcpy(cdata->sn, "2012", strlen("2012")); 175240616Sjimharris memset(cdata->mn, 0, sizeof(cdata->mn)); 176240616Sjimharris memcpy(cdata->mn, "CHATHAM2", strlen("CHATHAM2")); 177240616Sjimharris memset(cdata->fr, 0, sizeof(cdata->fr)); 178240616Sjimharris memcpy(cdata->fr, "0", strlen("0")); 179240616Sjimharris cdata->rab = 8; 180240616Sjimharris cdata->aerl = 3; 181240616Sjimharris cdata->lpa.ns_smart = 1; 182240616Sjimharris cdata->sqes.min = 6; 183240616Sjimharris cdata->sqes.max = 6; 184265559Sjimharris cdata->cqes.min = 4; 185265559Sjimharris cdata->cqes.max = 4; 186240616Sjimharris cdata->nn = 1; 187240616Sjimharris 188240616Sjimharris /* Chatham2 doesn't support DSM command */ 189240616Sjimharris cdata->oncs.dsm = 0; 190240616Sjimharris 191240616Sjimharris cdata->vwc.present = 1; 192240616Sjimharris} 193240616Sjimharris#endif /* CHATHAM2 */ 194240616Sjimharris 195240616Sjimharrisstatic void 196240616Sjimharrisnvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) 197240616Sjimharris{ 198240616Sjimharris struct nvme_qpair *qpair; 199240616Sjimharris uint32_t num_entries; 200240616Sjimharris 201240616Sjimharris qpair = &ctrlr->adminq; 202240616Sjimharris 203240616Sjimharris num_entries = NVME_ADMIN_ENTRIES; 204240616Sjimharris TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries); 205240616Sjimharris /* 206240616Sjimharris * If admin_entries was overridden to an invalid value, revert it 207240616Sjimharris * back to our default value. 208240616Sjimharris */ 209240616Sjimharris if (num_entries < NVME_MIN_ADMIN_ENTRIES || 210240616Sjimharris num_entries > NVME_MAX_ADMIN_ENTRIES) { 211252222Sjimharris nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d " 212252222Sjimharris "specified\n", num_entries); 213240616Sjimharris num_entries = NVME_ADMIN_ENTRIES; 214240616Sjimharris } 215240616Sjimharris 216240616Sjimharris /* 217240616Sjimharris * The admin queue's max xfer size is treated differently than the 218240616Sjimharris * max I/O xfer size. 16KB is sufficient here - maybe even less? 219240616Sjimharris */ 220252222Sjimharris nvme_qpair_construct(qpair, 221252222Sjimharris 0, /* qpair ID */ 222252222Sjimharris 0, /* vector */ 223252222Sjimharris num_entries, 224252222Sjimharris NVME_ADMIN_TRACKERS, 225252222Sjimharris ctrlr); 226240616Sjimharris} 227240616Sjimharris 228240616Sjimharrisstatic int 229240616Sjimharrisnvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr) 230240616Sjimharris{ 231240616Sjimharris struct nvme_qpair *qpair; 232240616Sjimharris union cap_lo_register cap_lo; 233252222Sjimharris int i, num_entries, num_trackers; 234240616Sjimharris 235240616Sjimharris num_entries = NVME_IO_ENTRIES; 236240616Sjimharris TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries); 237240616Sjimharris 238240616Sjimharris /* 239240616Sjimharris * NVMe spec sets a hard limit of 64K max entries, but 240240616Sjimharris * devices may specify a smaller limit, so we need to check 241240616Sjimharris * the MQES field in the capabilities register. 242240616Sjimharris */ 243240616Sjimharris cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo); 244240616Sjimharris num_entries = min(num_entries, cap_lo.bits.mqes+1); 245240616Sjimharris 246252222Sjimharris num_trackers = NVME_IO_TRACKERS; 247252222Sjimharris TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers); 248252222Sjimharris 249252222Sjimharris num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS); 250252222Sjimharris num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS); 251252222Sjimharris /* 252252222Sjimharris * No need to have more trackers than entries in the submit queue. 253252222Sjimharris * Note also that for a queue size of N, we can only have (N-1) 254252222Sjimharris * commands outstanding, hence the "-1" here. 255252222Sjimharris */ 256252222Sjimharris num_trackers = min(num_trackers, (num_entries-1)); 257252222Sjimharris 258240616Sjimharris ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair), 259252222Sjimharris M_NVME, M_ZERO | M_WAITOK); 260240616Sjimharris 261240616Sjimharris for (i = 0; i < ctrlr->num_io_queues; i++) { 262240616Sjimharris qpair = &ctrlr->ioq[i]; 263240616Sjimharris 264240616Sjimharris /* 265240616Sjimharris * Admin queue has ID=0. IO queues start at ID=1 - 266240616Sjimharris * hence the 'i+1' here. 267240616Sjimharris * 268240616Sjimharris * For I/O queues, use the controller-wide max_xfer_size 269240616Sjimharris * calculated in nvme_attach(). 270240616Sjimharris */ 271240616Sjimharris nvme_qpair_construct(qpair, 272240616Sjimharris i+1, /* qpair ID */ 273240616Sjimharris ctrlr->msix_enabled ? i+1 : 0, /* vector */ 274240616Sjimharris num_entries, 275252222Sjimharris num_trackers, 276240616Sjimharris ctrlr); 277240616Sjimharris 278240616Sjimharris if (ctrlr->per_cpu_io_queues) 279240616Sjimharris bus_bind_intr(ctrlr->dev, qpair->res, i); 280240616Sjimharris } 281240616Sjimharris 282240616Sjimharris return (0); 283240616Sjimharris} 284240616Sjimharris 285252222Sjimharrisstatic void 286252222Sjimharrisnvme_ctrlr_fail(struct nvme_controller *ctrlr) 287252222Sjimharris{ 288252222Sjimharris int i; 289252222Sjimharris 290252222Sjimharris ctrlr->is_failed = TRUE; 291252222Sjimharris nvme_qpair_fail(&ctrlr->adminq); 292252222Sjimharris for (i = 0; i < ctrlr->num_io_queues; i++) 293252222Sjimharris nvme_qpair_fail(&ctrlr->ioq[i]); 294252222Sjimharris nvme_notify_fail_consumers(ctrlr); 295252222Sjimharris} 296252222Sjimharris 297252222Sjimharrisvoid 298252222Sjimharrisnvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 299252222Sjimharris struct nvme_request *req) 300252222Sjimharris{ 301252222Sjimharris 302252222Sjimharris mtx_lock(&ctrlr->lock); 303252222Sjimharris STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq); 304252222Sjimharris mtx_unlock(&ctrlr->lock); 305252222Sjimharris taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task); 306252222Sjimharris} 307252222Sjimharris 308252222Sjimharrisstatic void 309252222Sjimharrisnvme_ctrlr_fail_req_task(void *arg, int pending) 310252222Sjimharris{ 311252222Sjimharris struct nvme_controller *ctrlr = arg; 312252222Sjimharris struct nvme_request *req; 313252222Sjimharris 314252222Sjimharris mtx_lock(&ctrlr->lock); 315252222Sjimharris while (!STAILQ_EMPTY(&ctrlr->fail_req)) { 316252222Sjimharris req = STAILQ_FIRST(&ctrlr->fail_req); 317252222Sjimharris STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq); 318252222Sjimharris nvme_qpair_manual_complete_request(req->qpair, req, 319252222Sjimharris NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, TRUE); 320252222Sjimharris } 321252222Sjimharris mtx_unlock(&ctrlr->lock); 322252222Sjimharris} 323252222Sjimharris 324240616Sjimharrisstatic int 325240616Sjimharrisnvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr) 326240616Sjimharris{ 327240616Sjimharris int ms_waited; 328240616Sjimharris union cc_register cc; 329240616Sjimharris union csts_register csts; 330240616Sjimharris 331240616Sjimharris cc.raw = nvme_mmio_read_4(ctrlr, cc); 332240616Sjimharris csts.raw = nvme_mmio_read_4(ctrlr, csts); 333240616Sjimharris 334240616Sjimharris if (!cc.bits.en) { 335252222Sjimharris nvme_printf(ctrlr, "%s called with cc.en = 0\n", __func__); 336240616Sjimharris return (ENXIO); 337240616Sjimharris } 338240616Sjimharris 339240616Sjimharris ms_waited = 0; 340240616Sjimharris 341240616Sjimharris while (!csts.bits.rdy) { 342240616Sjimharris DELAY(1000); 343240616Sjimharris if (ms_waited++ > ctrlr->ready_timeout_in_ms) { 344252222Sjimharris nvme_printf(ctrlr, "controller did not become ready " 345252222Sjimharris "within %d ms\n", ctrlr->ready_timeout_in_ms); 346240616Sjimharris return (ENXIO); 347240616Sjimharris } 348240616Sjimharris csts.raw = nvme_mmio_read_4(ctrlr, csts); 349240616Sjimharris } 350240616Sjimharris 351240616Sjimharris return (0); 352240616Sjimharris} 353240616Sjimharris 354240616Sjimharrisstatic void 355240616Sjimharrisnvme_ctrlr_disable(struct nvme_controller *ctrlr) 356240616Sjimharris{ 357240616Sjimharris union cc_register cc; 358240616Sjimharris union csts_register csts; 359240616Sjimharris 360240616Sjimharris cc.raw = nvme_mmio_read_4(ctrlr, cc); 361240616Sjimharris csts.raw = nvme_mmio_read_4(ctrlr, csts); 362240616Sjimharris 363240616Sjimharris if (cc.bits.en == 1 && csts.bits.rdy == 0) 364240616Sjimharris nvme_ctrlr_wait_for_ready(ctrlr); 365240616Sjimharris 366240616Sjimharris cc.bits.en = 0; 367240616Sjimharris nvme_mmio_write_4(ctrlr, cc, cc.raw); 368240616Sjimharris DELAY(5000); 369240616Sjimharris} 370240616Sjimharris 371240616Sjimharrisstatic int 372240616Sjimharrisnvme_ctrlr_enable(struct nvme_controller *ctrlr) 373240616Sjimharris{ 374240616Sjimharris union cc_register cc; 375240616Sjimharris union csts_register csts; 376240616Sjimharris union aqa_register aqa; 377240616Sjimharris 378240616Sjimharris cc.raw = nvme_mmio_read_4(ctrlr, cc); 379240616Sjimharris csts.raw = nvme_mmio_read_4(ctrlr, csts); 380240616Sjimharris 381240616Sjimharris if (cc.bits.en == 1) { 382240616Sjimharris if (csts.bits.rdy == 1) 383240616Sjimharris return (0); 384240616Sjimharris else 385240616Sjimharris return (nvme_ctrlr_wait_for_ready(ctrlr)); 386240616Sjimharris } 387240616Sjimharris 388240616Sjimharris nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); 389240616Sjimharris DELAY(5000); 390240616Sjimharris nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); 391240616Sjimharris DELAY(5000); 392240616Sjimharris 393240616Sjimharris aqa.raw = 0; 394240616Sjimharris /* acqs and asqs are 0-based. */ 395240616Sjimharris aqa.bits.acqs = ctrlr->adminq.num_entries-1; 396240616Sjimharris aqa.bits.asqs = ctrlr->adminq.num_entries-1; 397240616Sjimharris nvme_mmio_write_4(ctrlr, aqa, aqa.raw); 398240616Sjimharris DELAY(5000); 399240616Sjimharris 400240616Sjimharris cc.bits.en = 1; 401240616Sjimharris cc.bits.css = 0; 402240616Sjimharris cc.bits.ams = 0; 403240616Sjimharris cc.bits.shn = 0; 404240616Sjimharris cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */ 405240616Sjimharris cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */ 406240616Sjimharris 407240616Sjimharris /* This evaluates to 0, which is according to spec. */ 408240616Sjimharris cc.bits.mps = (PAGE_SIZE >> 13); 409240616Sjimharris 410240616Sjimharris nvme_mmio_write_4(ctrlr, cc, cc.raw); 411240616Sjimharris DELAY(5000); 412240616Sjimharris 413240616Sjimharris return (nvme_ctrlr_wait_for_ready(ctrlr)); 414240616Sjimharris} 415240616Sjimharris 416240616Sjimharrisint 417252222Sjimharrisnvme_ctrlr_hw_reset(struct nvme_controller *ctrlr) 418240616Sjimharris{ 419252222Sjimharris int i; 420240616Sjimharris 421252222Sjimharris nvme_admin_qpair_disable(&ctrlr->adminq); 422252222Sjimharris for (i = 0; i < ctrlr->num_io_queues; i++) 423252222Sjimharris nvme_io_qpair_disable(&ctrlr->ioq[i]); 424252222Sjimharris 425252222Sjimharris DELAY(100*1000); 426252222Sjimharris 427240616Sjimharris nvme_ctrlr_disable(ctrlr); 428240616Sjimharris return (nvme_ctrlr_enable(ctrlr)); 429240616Sjimharris} 430240616Sjimharris 431252222Sjimharrisvoid 432252222Sjimharrisnvme_ctrlr_reset(struct nvme_controller *ctrlr) 433240616Sjimharris{ 434252222Sjimharris int cmpset; 435240616Sjimharris 436252222Sjimharris cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1); 437240616Sjimharris 438252222Sjimharris if (cmpset == 0 || ctrlr->is_failed) 439252222Sjimharris /* 440252222Sjimharris * Controller is already resetting or has failed. Return 441252222Sjimharris * immediately since there is no need to kick off another 442252222Sjimharris * reset in these cases. 443252222Sjimharris */ 444252222Sjimharris return; 445240616Sjimharris 446252222Sjimharris taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task); 447240616Sjimharris} 448240616Sjimharris 449240616Sjimharrisstatic int 450240616Sjimharrisnvme_ctrlr_identify(struct nvme_controller *ctrlr) 451240616Sjimharris{ 452252222Sjimharris struct nvme_completion_poll_status status; 453240616Sjimharris 454252222Sjimharris status.done = FALSE; 455240616Sjimharris nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata, 456252222Sjimharris nvme_completion_poll_cb, &status); 457252222Sjimharris while (status.done == FALSE) 458253627Sjimharris pause("nvme", 1); 459252222Sjimharris if (nvme_completion_is_error(&status.cpl)) { 460252222Sjimharris nvme_printf(ctrlr, "nvme_identify_controller failed!\n"); 461240616Sjimharris return (ENXIO); 462240616Sjimharris } 463240616Sjimharris 464240616Sjimharris#ifdef CHATHAM2 465240616Sjimharris if (pci_get_devid(ctrlr->dev) == CHATHAM_PCI_ID) 466240616Sjimharris nvme_chatham_populate_cdata(ctrlr); 467240616Sjimharris#endif 468240616Sjimharris 469252222Sjimharris /* 470252222Sjimharris * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 471252222Sjimharris * controller supports. 472252222Sjimharris */ 473252222Sjimharris if (ctrlr->cdata.mdts > 0) 474252222Sjimharris ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 475252222Sjimharris ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts))); 476252222Sjimharris 477240616Sjimharris return (0); 478240616Sjimharris} 479240616Sjimharris 480240616Sjimharrisstatic int 481240616Sjimharrisnvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr) 482240616Sjimharris{ 483252222Sjimharris struct nvme_completion_poll_status status; 484252222Sjimharris int cq_allocated, i, sq_allocated; 485240616Sjimharris 486252222Sjimharris status.done = FALSE; 487240616Sjimharris nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues, 488252222Sjimharris nvme_completion_poll_cb, &status); 489252222Sjimharris while (status.done == FALSE) 490253627Sjimharris pause("nvme", 1); 491252222Sjimharris if (nvme_completion_is_error(&status.cpl)) { 492252222Sjimharris nvme_printf(ctrlr, "nvme_set_num_queues failed!\n"); 493240616Sjimharris return (ENXIO); 494240616Sjimharris } 495240616Sjimharris 496240616Sjimharris /* 497240616Sjimharris * Data in cdw0 is 0-based. 498240616Sjimharris * Lower 16-bits indicate number of submission queues allocated. 499240616Sjimharris * Upper 16-bits indicate number of completion queues allocated. 500240616Sjimharris */ 501252222Sjimharris sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1; 502252222Sjimharris cq_allocated = (status.cpl.cdw0 >> 16) + 1; 503240616Sjimharris 504240616Sjimharris /* 505240616Sjimharris * Check that the controller was able to allocate the number of 506252222Sjimharris * queues we requested. If not, revert to one IO queue pair. 507240616Sjimharris */ 508240616Sjimharris if (sq_allocated < ctrlr->num_io_queues || 509240616Sjimharris cq_allocated < ctrlr->num_io_queues) { 510252222Sjimharris 511252222Sjimharris /* 512252222Sjimharris * Destroy extra IO queue pairs that were created at 513252222Sjimharris * controller construction time but are no longer 514252222Sjimharris * needed. This will only happen when a controller 515252222Sjimharris * supports fewer queues than MSI-X vectors. This 516252222Sjimharris * is not the normal case, but does occur with the 517252222Sjimharris * Chatham prototype board. 518252222Sjimharris */ 519252222Sjimharris for (i = 1; i < ctrlr->num_io_queues; i++) 520252222Sjimharris nvme_io_qpair_destroy(&ctrlr->ioq[i]); 521252222Sjimharris 522240616Sjimharris ctrlr->num_io_queues = 1; 523240616Sjimharris ctrlr->per_cpu_io_queues = 0; 524240616Sjimharris } 525240616Sjimharris 526240616Sjimharris return (0); 527240616Sjimharris} 528240616Sjimharris 529240616Sjimharrisstatic int 530240616Sjimharrisnvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr) 531240616Sjimharris{ 532252222Sjimharris struct nvme_completion_poll_status status; 533252222Sjimharris struct nvme_qpair *qpair; 534252222Sjimharris int i; 535240616Sjimharris 536240616Sjimharris for (i = 0; i < ctrlr->num_io_queues; i++) { 537240616Sjimharris qpair = &ctrlr->ioq[i]; 538240616Sjimharris 539252222Sjimharris status.done = FALSE; 540240616Sjimharris nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, qpair->vector, 541252222Sjimharris nvme_completion_poll_cb, &status); 542252222Sjimharris while (status.done == FALSE) 543253627Sjimharris pause("nvme", 1); 544252222Sjimharris if (nvme_completion_is_error(&status.cpl)) { 545252222Sjimharris nvme_printf(ctrlr, "nvme_create_io_cq failed!\n"); 546240616Sjimharris return (ENXIO); 547240616Sjimharris } 548240616Sjimharris 549252222Sjimharris status.done = FALSE; 550240616Sjimharris nvme_ctrlr_cmd_create_io_sq(qpair->ctrlr, qpair, 551252222Sjimharris nvme_completion_poll_cb, &status); 552252222Sjimharris while (status.done == FALSE) 553253627Sjimharris pause("nvme", 1); 554252222Sjimharris if (nvme_completion_is_error(&status.cpl)) { 555252222Sjimharris nvme_printf(ctrlr, "nvme_create_io_sq failed!\n"); 556240616Sjimharris return (ENXIO); 557240616Sjimharris } 558240616Sjimharris } 559240616Sjimharris 560240616Sjimharris return (0); 561240616Sjimharris} 562240616Sjimharris 563240616Sjimharrisstatic int 564240616Sjimharrisnvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr) 565240616Sjimharris{ 566240616Sjimharris struct nvme_namespace *ns; 567240616Sjimharris int i, status; 568240616Sjimharris 569240616Sjimharris for (i = 0; i < ctrlr->cdata.nn; i++) { 570240616Sjimharris ns = &ctrlr->ns[i]; 571240616Sjimharris status = nvme_ns_construct(ns, i+1, ctrlr); 572240616Sjimharris if (status != 0) 573240616Sjimharris return (status); 574240616Sjimharris } 575240616Sjimharris 576240616Sjimharris return (0); 577240616Sjimharris} 578240616Sjimharris 579252222Sjimharrisstatic boolean_t 580252222Sjimharrisis_log_page_id_valid(uint8_t page_id) 581252222Sjimharris{ 582252222Sjimharris 583252222Sjimharris switch (page_id) { 584252222Sjimharris case NVME_LOG_ERROR: 585252222Sjimharris case NVME_LOG_HEALTH_INFORMATION: 586252222Sjimharris case NVME_LOG_FIRMWARE_SLOT: 587252222Sjimharris return (TRUE); 588252222Sjimharris } 589252222Sjimharris 590252222Sjimharris return (FALSE); 591252222Sjimharris} 592252222Sjimharris 593252222Sjimharrisstatic uint32_t 594252222Sjimharrisnvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id) 595252222Sjimharris{ 596252222Sjimharris uint32_t log_page_size; 597252222Sjimharris 598252222Sjimharris switch (page_id) { 599252222Sjimharris case NVME_LOG_ERROR: 600252222Sjimharris log_page_size = min( 601252222Sjimharris sizeof(struct nvme_error_information_entry) * 602252222Sjimharris ctrlr->cdata.elpe, 603252222Sjimharris NVME_MAX_AER_LOG_SIZE); 604252222Sjimharris break; 605252222Sjimharris case NVME_LOG_HEALTH_INFORMATION: 606252222Sjimharris log_page_size = sizeof(struct nvme_health_information_page); 607252222Sjimharris break; 608252222Sjimharris case NVME_LOG_FIRMWARE_SLOT: 609252222Sjimharris log_page_size = sizeof(struct nvme_firmware_page); 610252222Sjimharris break; 611252222Sjimharris default: 612252222Sjimharris log_page_size = 0; 613252222Sjimharris break; 614252222Sjimharris } 615252222Sjimharris 616252222Sjimharris return (log_page_size); 617252222Sjimharris} 618252222Sjimharris 619240616Sjimharrisstatic void 620257590Sjimharrisnvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr, 621257590Sjimharris union nvme_critical_warning_state state) 622257590Sjimharris{ 623257590Sjimharris 624257590Sjimharris if (state.bits.available_spare == 1) 625257590Sjimharris nvme_printf(ctrlr, "available spare space below threshold\n"); 626257590Sjimharris 627257590Sjimharris if (state.bits.temperature == 1) 628257590Sjimharris nvme_printf(ctrlr, "temperature above threshold\n"); 629257590Sjimharris 630257590Sjimharris if (state.bits.device_reliability == 1) 631257590Sjimharris nvme_printf(ctrlr, "device reliability degraded\n"); 632257590Sjimharris 633257590Sjimharris if (state.bits.read_only == 1) 634257590Sjimharris nvme_printf(ctrlr, "media placed in read only mode\n"); 635257590Sjimharris 636257590Sjimharris if (state.bits.volatile_memory_backup == 1) 637257590Sjimharris nvme_printf(ctrlr, "volatile memory backup device failed\n"); 638257590Sjimharris 639257590Sjimharris if (state.bits.reserved != 0) 640257590Sjimharris nvme_printf(ctrlr, 641257590Sjimharris "unknown critical warning(s): state = 0x%02x\n", state.raw); 642257590Sjimharris} 643257590Sjimharris 644257590Sjimharrisstatic void 645252222Sjimharrisnvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl) 646252222Sjimharris{ 647257590Sjimharris struct nvme_async_event_request *aer = arg; 648257590Sjimharris struct nvme_health_information_page *health_info; 649252222Sjimharris 650252222Sjimharris /* 651252222Sjimharris * If the log page fetch for some reason completed with an error, 652252222Sjimharris * don't pass log page data to the consumers. In practice, this case 653252222Sjimharris * should never happen. 654252222Sjimharris */ 655252222Sjimharris if (nvme_completion_is_error(cpl)) 656252222Sjimharris nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 657252222Sjimharris aer->log_page_id, NULL, 0); 658257590Sjimharris else { 659257590Sjimharris if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) { 660257590Sjimharris health_info = (struct nvme_health_information_page *) 661257590Sjimharris aer->log_page_buffer; 662257590Sjimharris nvme_ctrlr_log_critical_warnings(aer->ctrlr, 663257590Sjimharris health_info->critical_warning); 664257590Sjimharris /* 665257590Sjimharris * Critical warnings reported through the 666257590Sjimharris * SMART/health log page are persistent, so 667257590Sjimharris * clear the associated bits in the async event 668257590Sjimharris * config so that we do not receive repeated 669257590Sjimharris * notifications for the same event. 670257590Sjimharris */ 671257590Sjimharris aer->ctrlr->async_event_config.raw &= 672257590Sjimharris ~health_info->critical_warning.raw; 673257590Sjimharris nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr, 674257590Sjimharris aer->ctrlr->async_event_config, NULL, NULL); 675257590Sjimharris } 676257590Sjimharris 677257590Sjimharris 678252222Sjimharris /* 679252222Sjimharris * Pass the cpl data from the original async event completion, 680252222Sjimharris * not the log page fetch. 681252222Sjimharris */ 682252222Sjimharris nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 683252222Sjimharris aer->log_page_id, aer->log_page_buffer, aer->log_page_size); 684257590Sjimharris } 685252222Sjimharris 686252222Sjimharris /* 687252222Sjimharris * Repost another asynchronous event request to replace the one 688252222Sjimharris * that just completed. 689252222Sjimharris */ 690252222Sjimharris nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 691252222Sjimharris} 692252222Sjimharris 693252222Sjimharrisstatic void 694252222Sjimharrisnvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl) 695252222Sjimharris{ 696252222Sjimharris struct nvme_async_event_request *aer = arg; 697252222Sjimharris 698253295Sjimharris if (nvme_completion_is_error(cpl)) { 699252222Sjimharris /* 700253295Sjimharris * Do not retry failed async event requests. This avoids 701253295Sjimharris * infinite loops where a new async event request is submitted 702253295Sjimharris * to replace the one just failed, only to fail again and 703253295Sjimharris * perpetuate the loop. 704252222Sjimharris */ 705252222Sjimharris return; 706252222Sjimharris } 707252222Sjimharris 708252222Sjimharris /* Associated log page is in bits 23:16 of completion entry dw0. */ 709252222Sjimharris aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16; 710252222Sjimharris 711252222Sjimharris nvme_printf(aer->ctrlr, "async event occurred (log page id=0x%x)\n", 712252222Sjimharris aer->log_page_id); 713252222Sjimharris 714252222Sjimharris if (is_log_page_id_valid(aer->log_page_id)) { 715252222Sjimharris aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr, 716252222Sjimharris aer->log_page_id); 717252222Sjimharris memcpy(&aer->cpl, cpl, sizeof(*cpl)); 718252222Sjimharris nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id, 719252222Sjimharris NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer, 720252222Sjimharris aer->log_page_size, nvme_ctrlr_async_event_log_page_cb, 721252222Sjimharris aer); 722252222Sjimharris /* Wait to notify consumers until after log page is fetched. */ 723252222Sjimharris } else { 724252222Sjimharris nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id, 725252222Sjimharris NULL, 0); 726252222Sjimharris 727252222Sjimharris /* 728252222Sjimharris * Repost another asynchronous event request to replace the one 729252222Sjimharris * that just completed. 730252222Sjimharris */ 731252222Sjimharris nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 732252222Sjimharris } 733252222Sjimharris} 734252222Sjimharris 735252222Sjimharrisstatic void 736252222Sjimharrisnvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 737252222Sjimharris struct nvme_async_event_request *aer) 738252222Sjimharris{ 739252222Sjimharris struct nvme_request *req; 740252222Sjimharris 741252222Sjimharris aer->ctrlr = ctrlr; 742252222Sjimharris req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer); 743252222Sjimharris aer->req = req; 744252222Sjimharris 745252222Sjimharris /* 746252222Sjimharris * Disable timeout here, since asynchronous event requests should by 747252222Sjimharris * nature never be timed out. 748252222Sjimharris */ 749252222Sjimharris req->timeout = FALSE; 750252222Sjimharris req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST; 751252222Sjimharris nvme_ctrlr_submit_admin_request(ctrlr, req); 752252222Sjimharris} 753252222Sjimharris 754252222Sjimharrisstatic void 755240616Sjimharrisnvme_ctrlr_configure_aer(struct nvme_controller *ctrlr) 756240616Sjimharris{ 757257589Sjimharris struct nvme_completion_poll_status status; 758252222Sjimharris struct nvme_async_event_request *aer; 759252222Sjimharris uint32_t i; 760240616Sjimharris 761257590Sjimharris ctrlr->async_event_config.raw = 0xFF; 762257590Sjimharris ctrlr->async_event_config.bits.reserved = 0; 763257589Sjimharris 764257589Sjimharris status.done = FALSE; 765257589Sjimharris nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD, 766257589Sjimharris 0, NULL, 0, nvme_completion_poll_cb, &status); 767257589Sjimharris while (status.done == FALSE) 768257589Sjimharris pause("nvme", 1); 769257589Sjimharris if (nvme_completion_is_error(&status.cpl) || 770257589Sjimharris (status.cpl.cdw0 & 0xFFFF) == 0xFFFF || 771257589Sjimharris (status.cpl.cdw0 & 0xFFFF) == 0x0000) { 772257589Sjimharris nvme_printf(ctrlr, "temperature threshold not supported\n"); 773257590Sjimharris ctrlr->async_event_config.bits.temperature = 0; 774257589Sjimharris } 775257589Sjimharris 776257590Sjimharris nvme_ctrlr_cmd_set_async_event_config(ctrlr, 777257590Sjimharris ctrlr->async_event_config, NULL, NULL); 778240616Sjimharris 779240616Sjimharris /* aerl is a zero-based value, so we need to add 1 here. */ 780252222Sjimharris ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1)); 781240616Sjimharris 782252222Sjimharris /* Chatham doesn't support AERs. */ 783252222Sjimharris if (pci_get_devid(ctrlr->dev) == CHATHAM_PCI_ID) 784252222Sjimharris ctrlr->num_aers = 0; 785252222Sjimharris 786252222Sjimharris for (i = 0; i < ctrlr->num_aers; i++) { 787252222Sjimharris aer = &ctrlr->aer[i]; 788252222Sjimharris nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 789252222Sjimharris } 790240616Sjimharris} 791240616Sjimharris 792240616Sjimharrisstatic void 793240616Sjimharrisnvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr) 794240616Sjimharris{ 795240616Sjimharris 796240616Sjimharris ctrlr->int_coal_time = 0; 797240616Sjimharris TUNABLE_INT_FETCH("hw.nvme.int_coal_time", 798240616Sjimharris &ctrlr->int_coal_time); 799240616Sjimharris 800240616Sjimharris ctrlr->int_coal_threshold = 0; 801240616Sjimharris TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold", 802240616Sjimharris &ctrlr->int_coal_threshold); 803240616Sjimharris 804240616Sjimharris nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time, 805240616Sjimharris ctrlr->int_coal_threshold, NULL, NULL); 806240616Sjimharris} 807240616Sjimharris 808252222Sjimharrisstatic void 809240616Sjimharrisnvme_ctrlr_start(void *ctrlr_arg) 810240616Sjimharris{ 811240616Sjimharris struct nvme_controller *ctrlr = ctrlr_arg; 812252222Sjimharris int i; 813240616Sjimharris 814252222Sjimharris nvme_qpair_reset(&ctrlr->adminq); 815252222Sjimharris for (i = 0; i < ctrlr->num_io_queues; i++) 816252222Sjimharris nvme_qpair_reset(&ctrlr->ioq[i]); 817240616Sjimharris 818252222Sjimharris nvme_admin_qpair_enable(&ctrlr->adminq); 819240616Sjimharris 820252222Sjimharris if (nvme_ctrlr_identify(ctrlr) != 0) { 821252222Sjimharris nvme_ctrlr_fail(ctrlr); 822252222Sjimharris return; 823252222Sjimharris } 824240616Sjimharris 825252222Sjimharris if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) { 826252222Sjimharris nvme_ctrlr_fail(ctrlr); 827252222Sjimharris return; 828252222Sjimharris } 829240616Sjimharris 830252222Sjimharris if (nvme_ctrlr_create_qpairs(ctrlr) != 0) { 831252222Sjimharris nvme_ctrlr_fail(ctrlr); 832252222Sjimharris return; 833252222Sjimharris } 834252222Sjimharris 835252222Sjimharris if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) { 836252222Sjimharris nvme_ctrlr_fail(ctrlr); 837252222Sjimharris return; 838252222Sjimharris } 839252222Sjimharris 840240616Sjimharris nvme_ctrlr_configure_aer(ctrlr); 841240616Sjimharris nvme_ctrlr_configure_int_coalescing(ctrlr); 842240616Sjimharris 843252222Sjimharris for (i = 0; i < ctrlr->num_io_queues; i++) 844252222Sjimharris nvme_io_qpair_enable(&ctrlr->ioq[i]); 845252222Sjimharris} 846252222Sjimharris 847252222Sjimharrisvoid 848252222Sjimharrisnvme_ctrlr_start_config_hook(void *arg) 849252222Sjimharris{ 850252222Sjimharris struct nvme_controller *ctrlr = arg; 851252222Sjimharris 852252222Sjimharris nvme_ctrlr_start(ctrlr); 853240616Sjimharris config_intrhook_disestablish(&ctrlr->config_hook); 854265565Sjimharris 855265565Sjimharris ctrlr->is_initialized = 1; 856265565Sjimharris nvme_notify_new_controller(ctrlr); 857240616Sjimharris} 858240616Sjimharris 859240616Sjimharrisstatic void 860252222Sjimharrisnvme_ctrlr_reset_task(void *arg, int pending) 861240616Sjimharris{ 862252222Sjimharris struct nvme_controller *ctrlr = arg; 863252222Sjimharris int status; 864240616Sjimharris 865252222Sjimharris nvme_printf(ctrlr, "resetting controller\n"); 866252222Sjimharris status = nvme_ctrlr_hw_reset(ctrlr); 867252222Sjimharris /* 868252222Sjimharris * Use pause instead of DELAY, so that we yield to any nvme interrupt 869252222Sjimharris * handlers on this CPU that were blocked on a qpair lock. We want 870252222Sjimharris * all nvme interrupts completed before proceeding with restarting the 871252222Sjimharris * controller. 872252222Sjimharris * 873252222Sjimharris * XXX - any way to guarantee the interrupt handlers have quiesced? 874252222Sjimharris */ 875252222Sjimharris pause("nvmereset", hz / 10); 876252222Sjimharris if (status == 0) 877252222Sjimharris nvme_ctrlr_start(ctrlr); 878252222Sjimharris else 879252222Sjimharris nvme_ctrlr_fail(ctrlr); 880240616Sjimharris 881252222Sjimharris atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 882240616Sjimharris} 883240616Sjimharris 884240616Sjimharrisstatic void 885240616Sjimharrisnvme_ctrlr_intx_handler(void *arg) 886240616Sjimharris{ 887240616Sjimharris struct nvme_controller *ctrlr = arg; 888240616Sjimharris 889240616Sjimharris nvme_mmio_write_4(ctrlr, intms, 1); 890252222Sjimharris 891252222Sjimharris nvme_qpair_process_completions(&ctrlr->adminq); 892252222Sjimharris 893252222Sjimharris if (ctrlr->ioq[0].cpl) 894252222Sjimharris nvme_qpair_process_completions(&ctrlr->ioq[0]); 895252222Sjimharris 896252222Sjimharris nvme_mmio_write_4(ctrlr, intmc, 1); 897240616Sjimharris} 898240616Sjimharris 899240616Sjimharrisstatic int 900240616Sjimharrisnvme_ctrlr_configure_intx(struct nvme_controller *ctrlr) 901240616Sjimharris{ 902240616Sjimharris 903240616Sjimharris ctrlr->num_io_queues = 1; 904240616Sjimharris ctrlr->per_cpu_io_queues = 0; 905240616Sjimharris ctrlr->rid = 0; 906240616Sjimharris ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 907240616Sjimharris &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 908240616Sjimharris 909240616Sjimharris if (ctrlr->res == NULL) { 910252222Sjimharris nvme_printf(ctrlr, "unable to allocate shared IRQ\n"); 911240616Sjimharris return (ENOMEM); 912240616Sjimharris } 913240616Sjimharris 914240616Sjimharris bus_setup_intr(ctrlr->dev, ctrlr->res, 915240616Sjimharris INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler, 916240616Sjimharris ctrlr, &ctrlr->tag); 917240616Sjimharris 918240616Sjimharris if (ctrlr->tag == NULL) { 919252222Sjimharris nvme_printf(ctrlr, "unable to setup intx handler\n"); 920240616Sjimharris return (ENOMEM); 921240616Sjimharris } 922240616Sjimharris 923240616Sjimharris return (0); 924240616Sjimharris} 925240616Sjimharris 926252222Sjimharrisstatic void 927252222Sjimharrisnvme_pt_done(void *arg, const struct nvme_completion *cpl) 928252222Sjimharris{ 929252222Sjimharris struct nvme_pt_command *pt = arg; 930252222Sjimharris 931252222Sjimharris bzero(&pt->cpl, sizeof(pt->cpl)); 932252222Sjimharris pt->cpl.cdw0 = cpl->cdw0; 933252222Sjimharris pt->cpl.status = cpl->status; 934252222Sjimharris pt->cpl.status.p = 0; 935252222Sjimharris 936252222Sjimharris mtx_lock(pt->driver_lock); 937252222Sjimharris wakeup(pt); 938252222Sjimharris mtx_unlock(pt->driver_lock); 939252222Sjimharris} 940252222Sjimharris 941252222Sjimharrisint 942252222Sjimharrisnvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 943252222Sjimharris struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer, 944252222Sjimharris int is_admin_cmd) 945252222Sjimharris{ 946252222Sjimharris struct nvme_request *req; 947252222Sjimharris struct mtx *mtx; 948252222Sjimharris struct buf *buf = NULL; 949252222Sjimharris int ret = 0; 950252222Sjimharris 951252665Sjimharris if (pt->len > 0) { 952252665Sjimharris if (pt->len > ctrlr->max_xfer_size) { 953252665Sjimharris nvme_printf(ctrlr, "pt->len (%d) " 954252665Sjimharris "exceeds max_xfer_size (%d)\n", pt->len, 955252665Sjimharris ctrlr->max_xfer_size); 956252665Sjimharris return EIO; 957252665Sjimharris } 958252222Sjimharris if (is_user_buffer) { 959252222Sjimharris /* 960252222Sjimharris * Ensure the user buffer is wired for the duration of 961252222Sjimharris * this passthrough command. 962252222Sjimharris */ 963252222Sjimharris PHOLD(curproc); 964252222Sjimharris buf = getpbuf(NULL); 965252222Sjimharris buf->b_saveaddr = buf->b_data; 966252222Sjimharris buf->b_data = pt->buf; 967252222Sjimharris buf->b_bufsize = pt->len; 968252222Sjimharris buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE; 969252222Sjimharris#ifdef NVME_UNMAPPED_BIO_SUPPORT 970252222Sjimharris if (vmapbuf(buf, 1) < 0) { 971252222Sjimharris#else 972252222Sjimharris if (vmapbuf(buf) < 0) { 973252222Sjimharris#endif 974252222Sjimharris ret = EFAULT; 975252222Sjimharris goto err; 976252222Sjimharris } 977252222Sjimharris req = nvme_allocate_request_vaddr(buf->b_data, pt->len, 978252222Sjimharris nvme_pt_done, pt); 979252222Sjimharris } else 980252222Sjimharris req = nvme_allocate_request_vaddr(pt->buf, pt->len, 981252222Sjimharris nvme_pt_done, pt); 982252665Sjimharris } else 983252222Sjimharris req = nvme_allocate_request_null(nvme_pt_done, pt); 984252222Sjimharris 985252222Sjimharris req->cmd.opc = pt->cmd.opc; 986252222Sjimharris req->cmd.cdw10 = pt->cmd.cdw10; 987252222Sjimharris req->cmd.cdw11 = pt->cmd.cdw11; 988252222Sjimharris req->cmd.cdw12 = pt->cmd.cdw12; 989252222Sjimharris req->cmd.cdw13 = pt->cmd.cdw13; 990252222Sjimharris req->cmd.cdw14 = pt->cmd.cdw14; 991252222Sjimharris req->cmd.cdw15 = pt->cmd.cdw15; 992252222Sjimharris 993252222Sjimharris req->cmd.nsid = nsid; 994252222Sjimharris 995252222Sjimharris if (is_admin_cmd) 996252222Sjimharris mtx = &ctrlr->lock; 997252222Sjimharris else 998252222Sjimharris mtx = &ctrlr->ns[nsid-1].lock; 999252222Sjimharris 1000252222Sjimharris mtx_lock(mtx); 1001252222Sjimharris pt->driver_lock = mtx; 1002252222Sjimharris 1003252222Sjimharris if (is_admin_cmd) 1004252222Sjimharris nvme_ctrlr_submit_admin_request(ctrlr, req); 1005252222Sjimharris else 1006252222Sjimharris nvme_ctrlr_submit_io_request(ctrlr, req); 1007252222Sjimharris 1008252222Sjimharris mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0); 1009252222Sjimharris mtx_unlock(mtx); 1010252222Sjimharris 1011252222Sjimharris pt->driver_lock = NULL; 1012252222Sjimharris 1013252222Sjimharriserr: 1014252222Sjimharris if (buf != NULL) { 1015252222Sjimharris relpbuf(buf, NULL); 1016252222Sjimharris PRELE(curproc); 1017252222Sjimharris } 1018252222Sjimharris 1019252222Sjimharris return (ret); 1020252222Sjimharris} 1021252222Sjimharris 1022240616Sjimharrisstatic int 1023240616Sjimharrisnvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag, 1024240616Sjimharris struct thread *td) 1025240616Sjimharris{ 1026252222Sjimharris struct nvme_controller *ctrlr; 1027252222Sjimharris struct nvme_pt_command *pt; 1028240616Sjimharris 1029240616Sjimharris ctrlr = cdev->si_drv1; 1030240616Sjimharris 1031240616Sjimharris switch (cmd) { 1032252222Sjimharris case NVME_RESET_CONTROLLER: 1033252222Sjimharris nvme_ctrlr_reset(ctrlr); 1034240616Sjimharris break; 1035252222Sjimharris case NVME_PASSTHROUGH_CMD: 1036252222Sjimharris pt = (struct nvme_pt_command *)arg; 1037265559Sjimharris#ifdef CHATHAM2 1038265559Sjimharris /* 1039265559Sjimharris * Chatham IDENTIFY data is spoofed, so copy the spoofed data 1040265559Sjimharris * rather than issuing the command to the Chatham controller. 1041265559Sjimharris */ 1042265559Sjimharris if (pci_get_devid(ctrlr->dev) == CHATHAM_PCI_ID && 1043265559Sjimharris pt->cmd.opc == NVME_OPC_IDENTIFY) { 1044265559Sjimharris if (pt->cmd.cdw10 == 1) { 1045265559Sjimharris if (pt->len != sizeof(ctrlr->cdata)) 1046265559Sjimharris return (EINVAL); 1047265559Sjimharris return (copyout(&ctrlr->cdata, pt->buf, 1048265559Sjimharris pt->len)); 1049265559Sjimharris } else { 1050265559Sjimharris if (pt->len != sizeof(ctrlr->ns[0].data) || 1051265559Sjimharris pt->cmd.nsid != 1) 1052265559Sjimharris return (EINVAL); 1053265559Sjimharris return (copyout(&ctrlr->ns[0].data, pt->buf, 1054265559Sjimharris pt->len)); 1055265559Sjimharris } 1056265559Sjimharris } 1057265559Sjimharris#endif 1058252222Sjimharris return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, pt->cmd.nsid, 1059252222Sjimharris 1 /* is_user_buffer */, 1 /* is_admin_cmd */)); 1060240616Sjimharris default: 1061240616Sjimharris return (ENOTTY); 1062240616Sjimharris } 1063240616Sjimharris 1064240616Sjimharris return (0); 1065240616Sjimharris} 1066240616Sjimharris 1067240616Sjimharrisstatic struct cdevsw nvme_ctrlr_cdevsw = { 1068240616Sjimharris .d_version = D_VERSION, 1069240616Sjimharris .d_flags = 0, 1070240616Sjimharris .d_ioctl = nvme_ctrlr_ioctl 1071240616Sjimharris}; 1072240616Sjimharris 1073240616Sjimharrisint 1074240616Sjimharrisnvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) 1075240616Sjimharris{ 1076240616Sjimharris union cap_lo_register cap_lo; 1077240616Sjimharris union cap_hi_register cap_hi; 1078265566Sjimharris int i, num_vectors, per_cpu_io_queues, rid; 1079265566Sjimharris int status, timeout_period; 1080240616Sjimharris 1081240616Sjimharris ctrlr->dev = dev; 1082240616Sjimharris 1083252222Sjimharris mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); 1084252222Sjimharris 1085240616Sjimharris status = nvme_ctrlr_allocate_bar(ctrlr); 1086240616Sjimharris 1087240616Sjimharris if (status != 0) 1088240616Sjimharris return (status); 1089240616Sjimharris 1090240616Sjimharris#ifdef CHATHAM2 1091240616Sjimharris if (pci_get_devid(dev) == CHATHAM_PCI_ID) { 1092240616Sjimharris status = nvme_ctrlr_allocate_chatham_bar(ctrlr); 1093240616Sjimharris if (status != 0) 1094240616Sjimharris return (status); 1095240616Sjimharris nvme_ctrlr_setup_chatham(ctrlr); 1096240616Sjimharris } 1097240616Sjimharris#endif 1098240616Sjimharris 1099240616Sjimharris /* 1100240616Sjimharris * Software emulators may set the doorbell stride to something 1101240616Sjimharris * other than zero, but this driver is not set up to handle that. 1102240616Sjimharris */ 1103240616Sjimharris cap_hi.raw = nvme_mmio_read_4(ctrlr, cap_hi); 1104240616Sjimharris if (cap_hi.bits.dstrd != 0) 1105240616Sjimharris return (ENXIO); 1106240616Sjimharris 1107252222Sjimharris ctrlr->min_page_size = 1 << (12 + cap_hi.bits.mpsmin); 1108252222Sjimharris 1109240616Sjimharris /* Get ready timeout value from controller, in units of 500ms. */ 1110240616Sjimharris cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo); 1111240616Sjimharris ctrlr->ready_timeout_in_ms = cap_lo.bits.to * 500; 1112240616Sjimharris 1113252222Sjimharris timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD; 1114252222Sjimharris TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period); 1115252222Sjimharris timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 1116252222Sjimharris timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 1117252222Sjimharris ctrlr->timeout_period = timeout_period; 1118252222Sjimharris 1119252222Sjimharris nvme_retry_count = NVME_DEFAULT_RETRY_COUNT; 1120252222Sjimharris TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count); 1121252222Sjimharris 1122240616Sjimharris per_cpu_io_queues = 1; 1123240616Sjimharris TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 1124240616Sjimharris ctrlr->per_cpu_io_queues = per_cpu_io_queues ? TRUE : FALSE; 1125240616Sjimharris 1126240616Sjimharris if (ctrlr->per_cpu_io_queues) 1127240616Sjimharris ctrlr->num_io_queues = mp_ncpus; 1128240616Sjimharris else 1129240616Sjimharris ctrlr->num_io_queues = 1; 1130240616Sjimharris 1131240616Sjimharris ctrlr->force_intx = 0; 1132240616Sjimharris TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx); 1133240616Sjimharris 1134252222Sjimharris ctrlr->enable_aborts = 0; 1135252222Sjimharris TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); 1136252222Sjimharris 1137240616Sjimharris ctrlr->msix_enabled = 1; 1138240616Sjimharris 1139240616Sjimharris if (ctrlr->force_intx) { 1140240616Sjimharris ctrlr->msix_enabled = 0; 1141240616Sjimharris goto intx; 1142240616Sjimharris } 1143240616Sjimharris 1144240616Sjimharris /* One vector per IO queue, plus one vector for admin queue. */ 1145240616Sjimharris num_vectors = ctrlr->num_io_queues + 1; 1146240616Sjimharris 1147240616Sjimharris if (pci_msix_count(dev) < num_vectors) { 1148240616Sjimharris ctrlr->msix_enabled = 0; 1149240616Sjimharris goto intx; 1150240616Sjimharris } 1151240616Sjimharris 1152265566Sjimharris if (pci_alloc_msix(dev, &num_vectors) != 0) { 1153240616Sjimharris ctrlr->msix_enabled = 0; 1154265566Sjimharris goto intx; 1155265566Sjimharris } 1156240616Sjimharris 1157265566Sjimharris /* 1158265566Sjimharris * On earlier FreeBSD releases, there are reports that 1159265566Sjimharris * pci_alloc_msix() can return successfully with all vectors 1160265566Sjimharris * requested, but a subsequent bus_alloc_resource_any() 1161265566Sjimharris * for one of those vectors fails. This issue occurs more 1162265566Sjimharris * readily with multiple devices using per-CPU vectors. 1163265566Sjimharris * To workaround this issue, try to allocate the resources now, 1164265566Sjimharris * and fall back to INTx if we cannot allocate all of them. 1165265566Sjimharris * This issue cannot be reproduced on more recent versions of 1166265566Sjimharris * FreeBSD which have increased the maximum number of MSI-X 1167265566Sjimharris * vectors, but adding the workaround makes it easier for 1168265566Sjimharris * vendors wishing to import this driver into kernels based on 1169265566Sjimharris * older versions of FreeBSD. 1170265566Sjimharris */ 1171265566Sjimharris for (i = 0; i < num_vectors; i++) { 1172265566Sjimharris rid = i + 1; 1173265566Sjimharris ctrlr->msi_res[i] = bus_alloc_resource_any(ctrlr->dev, 1174265566Sjimharris SYS_RES_IRQ, &rid, RF_ACTIVE); 1175265566Sjimharris 1176265566Sjimharris if (ctrlr->msi_res[i] == NULL) { 1177265566Sjimharris ctrlr->msix_enabled = 0; 1178265566Sjimharris while (i > 0) { 1179265566Sjimharris i--; 1180265566Sjimharris bus_release_resource(ctrlr->dev, 1181265566Sjimharris SYS_RES_IRQ, 1182265566Sjimharris rman_get_rid(ctrlr->msi_res[i]), 1183265566Sjimharris ctrlr->msi_res[i]); 1184265566Sjimharris } 1185265566Sjimharris pci_release_msi(dev); 1186265566Sjimharris nvme_printf(ctrlr, "could not obtain all MSI-X " 1187265566Sjimharris "resources, reverting to intx\n"); 1188265566Sjimharris break; 1189265566Sjimharris } 1190265566Sjimharris } 1191265566Sjimharris 1192240616Sjimharrisintx: 1193240616Sjimharris 1194240616Sjimharris if (!ctrlr->msix_enabled) 1195240616Sjimharris nvme_ctrlr_configure_intx(ctrlr); 1196240616Sjimharris 1197252664Sjimharris ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE; 1198240616Sjimharris nvme_ctrlr_construct_admin_qpair(ctrlr); 1199240616Sjimharris status = nvme_ctrlr_construct_io_qpairs(ctrlr); 1200240616Sjimharris 1201240616Sjimharris if (status != 0) 1202240616Sjimharris return (status); 1203240616Sjimharris 1204257709Sjimharris ctrlr->cdev = make_dev(&nvme_ctrlr_cdevsw, device_get_unit(dev), 1205257709Sjimharris UID_ROOT, GID_WHEEL, 0600, "nvme%d", device_get_unit(dev)); 1206240616Sjimharris 1207240616Sjimharris if (ctrlr->cdev == NULL) 1208240616Sjimharris return (ENXIO); 1209240616Sjimharris 1210240616Sjimharris ctrlr->cdev->si_drv1 = (void *)ctrlr; 1211240616Sjimharris 1212252222Sjimharris ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK, 1213252222Sjimharris taskqueue_thread_enqueue, &ctrlr->taskqueue); 1214252222Sjimharris taskqueue_start_threads(&ctrlr->taskqueue, 1, PI_DISK, "nvme taskq"); 1215252222Sjimharris 1216252222Sjimharris ctrlr->is_resetting = 0; 1217265565Sjimharris ctrlr->is_initialized = 0; 1218265565Sjimharris ctrlr->notification_sent = 0; 1219252222Sjimharris TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr); 1220252222Sjimharris 1221252222Sjimharris TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr); 1222252222Sjimharris STAILQ_INIT(&ctrlr->fail_req); 1223252222Sjimharris ctrlr->is_failed = FALSE; 1224252222Sjimharris 1225240616Sjimharris return (0); 1226240616Sjimharris} 1227252222Sjimharris 1228252222Sjimharrisvoid 1229252222Sjimharrisnvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev) 1230252222Sjimharris{ 1231252222Sjimharris int i; 1232252222Sjimharris 1233263273Sjimharris /* 1234263273Sjimharris * Notify the controller of a shutdown, even though this is due to 1235263273Sjimharris * a driver unload, not a system shutdown (this path is not invoked 1236263273Sjimharris * during shutdown). This ensures the controller receives a 1237263273Sjimharris * shutdown notification in case the system is shutdown before 1238263273Sjimharris * reloading the driver. 1239263273Sjimharris * 1240263273Sjimharris * Chatham does not let you re-enable the controller after shutdown 1241263273Sjimharris * notification has been received, so do not send it in this case. 1242263273Sjimharris * This is OK because Chatham does not depend on the shutdown 1243263273Sjimharris * notification anyways. 1244263273Sjimharris */ 1245263273Sjimharris if (pci_get_devid(ctrlr->dev) != CHATHAM_PCI_ID) 1246263273Sjimharris nvme_ctrlr_shutdown(ctrlr); 1247263273Sjimharris 1248252222Sjimharris nvme_ctrlr_disable(ctrlr); 1249252222Sjimharris taskqueue_free(ctrlr->taskqueue); 1250252222Sjimharris 1251252222Sjimharris for (i = 0; i < NVME_MAX_NAMESPACES; i++) 1252252222Sjimharris nvme_ns_destruct(&ctrlr->ns[i]); 1253252222Sjimharris 1254252222Sjimharris if (ctrlr->cdev) 1255252222Sjimharris destroy_dev(ctrlr->cdev); 1256252222Sjimharris 1257252222Sjimharris for (i = 0; i < ctrlr->num_io_queues; i++) { 1258252222Sjimharris nvme_io_qpair_destroy(&ctrlr->ioq[i]); 1259252222Sjimharris } 1260252222Sjimharris 1261252222Sjimharris free(ctrlr->ioq, M_NVME); 1262252222Sjimharris 1263252222Sjimharris nvme_admin_qpair_destroy(&ctrlr->adminq); 1264252222Sjimharris 1265252222Sjimharris if (ctrlr->resource != NULL) { 1266252222Sjimharris bus_release_resource(dev, SYS_RES_MEMORY, 1267252222Sjimharris ctrlr->resource_id, ctrlr->resource); 1268252222Sjimharris } 1269252222Sjimharris 1270252222Sjimharris if (ctrlr->bar4_resource != NULL) { 1271252222Sjimharris bus_release_resource(dev, SYS_RES_MEMORY, 1272252222Sjimharris ctrlr->bar4_resource_id, ctrlr->bar4_resource); 1273252222Sjimharris } 1274252222Sjimharris 1275252222Sjimharris#ifdef CHATHAM2 1276252222Sjimharris if (ctrlr->chatham_resource != NULL) { 1277252222Sjimharris bus_release_resource(dev, SYS_RES_MEMORY, 1278252222Sjimharris ctrlr->chatham_resource_id, ctrlr->chatham_resource); 1279252222Sjimharris } 1280252222Sjimharris#endif 1281252222Sjimharris 1282252222Sjimharris if (ctrlr->tag) 1283252222Sjimharris bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag); 1284252222Sjimharris 1285252222Sjimharris if (ctrlr->res) 1286252222Sjimharris bus_release_resource(ctrlr->dev, SYS_RES_IRQ, 1287252222Sjimharris rman_get_rid(ctrlr->res), ctrlr->res); 1288252222Sjimharris 1289252222Sjimharris if (ctrlr->msix_enabled) 1290252222Sjimharris pci_release_msi(dev); 1291252222Sjimharris} 1292252222Sjimharris 1293252222Sjimharrisvoid 1294263273Sjimharrisnvme_ctrlr_shutdown(struct nvme_controller *ctrlr) 1295263273Sjimharris{ 1296263273Sjimharris union cc_register cc; 1297263273Sjimharris union csts_register csts; 1298263273Sjimharris int ticks = 0; 1299263273Sjimharris 1300263273Sjimharris cc.raw = nvme_mmio_read_4(ctrlr, cc); 1301263273Sjimharris cc.bits.shn = NVME_SHN_NORMAL; 1302263273Sjimharris nvme_mmio_write_4(ctrlr, cc, cc.raw); 1303263273Sjimharris csts.raw = nvme_mmio_read_4(ctrlr, csts); 1304263273Sjimharris while ((csts.bits.shst != NVME_SHST_COMPLETE) && (ticks++ < 5*hz)) { 1305263273Sjimharris pause("nvme shn", 1); 1306263273Sjimharris csts.raw = nvme_mmio_read_4(ctrlr, csts); 1307263273Sjimharris } 1308263273Sjimharris if (csts.bits.shst != NVME_SHST_COMPLETE) 1309263273Sjimharris nvme_printf(ctrlr, "did not complete shutdown within 5 seconds " 1310263273Sjimharris "of notification\n"); 1311263273Sjimharris} 1312263273Sjimharris 1313263273Sjimharrisvoid 1314252222Sjimharrisnvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 1315252222Sjimharris struct nvme_request *req) 1316252222Sjimharris{ 1317252222Sjimharris 1318252222Sjimharris nvme_qpair_submit_request(&ctrlr->adminq, req); 1319252222Sjimharris} 1320252222Sjimharris 1321252222Sjimharrisvoid 1322252222Sjimharrisnvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 1323252222Sjimharris struct nvme_request *req) 1324252222Sjimharris{ 1325252222Sjimharris struct nvme_qpair *qpair; 1326252222Sjimharris 1327252222Sjimharris if (ctrlr->per_cpu_io_queues) 1328252222Sjimharris qpair = &ctrlr->ioq[curcpu]; 1329252222Sjimharris else 1330252222Sjimharris qpair = &ctrlr->ioq[0]; 1331252222Sjimharris 1332252222Sjimharris nvme_qpair_submit_request(qpair, req); 1333252222Sjimharris} 1334252222Sjimharris 1335252222Sjimharrisdevice_t 1336252222Sjimharrisnvme_ctrlr_get_device(struct nvme_controller *ctrlr) 1337252222Sjimharris{ 1338252222Sjimharris 1339252222Sjimharris return (ctrlr->dev); 1340252222Sjimharris} 1341252222Sjimharris 1342252222Sjimharrisconst struct nvme_controller_data * 1343252222Sjimharrisnvme_ctrlr_get_data(struct nvme_controller *ctrlr) 1344252222Sjimharris{ 1345252222Sjimharris 1346252222Sjimharris return (&ctrlr->cdata); 1347252222Sjimharris} 1348