1/*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <vm/uma.h> 42#include <machine/stdarg.h> 43#include <machine/resource.h> 44#include <machine/bus.h> 45#include <sys/rman.h> 46#include <dev/pci/pcivar.h> 47#include "mvs.h" 48 49#include <cam/cam.h> 50#include <cam/cam_ccb.h> 51#include <cam/cam_sim.h> 52#include <cam/cam_xpt_sim.h> 53#include <cam/cam_debug.h> 54 55/* local prototypes */ 56static int mvs_ch_init(device_t dev); 57static int mvs_ch_deinit(device_t dev); 58static int mvs_ch_suspend(device_t dev); 59static int mvs_ch_resume(device_t dev); 60static void mvs_dmainit(device_t dev); 61static void mvs_dmasetupc_cb(void *xsc, 62 bus_dma_segment_t *segs, int nsegs, int error); 63static void mvs_dmafini(device_t dev); 64static void mvs_slotsalloc(device_t dev); 65static void mvs_slotsfree(device_t dev); 66static void mvs_setup_edma_queues(device_t dev); 67static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode); 68static void mvs_ch_pm(void *arg); 69static void mvs_ch_intr_locked(void *data); 70static void mvs_ch_intr(void *data); 71static void mvs_reset(device_t dev); 72static void mvs_softreset(device_t dev, union ccb *ccb); 73 74static int mvs_sata_connect(struct mvs_channel *ch); 75static int mvs_sata_phy_reset(device_t dev); 76static int mvs_wait(device_t dev, u_int s, u_int c, int t); 77static void mvs_tfd_read(device_t dev, union ccb *ccb); 78static void mvs_tfd_write(device_t dev, union ccb *ccb); 79static void mvs_legacy_intr(device_t dev, int poll); 80static void mvs_crbq_intr(device_t dev); 81static void mvs_begin_transaction(device_t dev, union ccb *ccb); 82static void mvs_legacy_execute_transaction(struct mvs_slot *slot); 83static void mvs_timeout(struct mvs_slot *slot); 84static void mvs_dmasetprd(void *arg, 85 bus_dma_segment_t *segs, int nsegs, int error); 86static void mvs_requeue_frozen(device_t dev); 87static void mvs_execute_transaction(struct mvs_slot *slot); 88static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et); 89 90static void mvs_issue_recovery(device_t dev); 91static void mvs_process_read_log(device_t dev, union ccb *ccb); 92static void mvs_process_request_sense(device_t dev, union ccb *ccb); 93 94static void mvsaction(struct cam_sim *sim, union ccb *ccb); 95static void mvspoll(struct cam_sim *sim); 96 97static MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers"); 98 99#define recovery_type spriv_field0 100#define RECOVERY_NONE 0 101#define RECOVERY_READ_LOG 1 102#define RECOVERY_REQUEST_SENSE 2 103#define recovery_slot spriv_field1 104 105static int 106mvs_ch_probe(device_t dev) 107{ 108 109 device_set_desc_copy(dev, "Marvell SATA channel"); 110 return (0); 111} 112 113static int 114mvs_ch_attach(device_t dev) 115{ 116 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev)); 117 struct mvs_channel *ch = device_get_softc(dev); 118 struct cam_devq *devq; 119 int rid, error, i, sata_rev = 0; 120 121 ch->dev = dev; 122 ch->unit = (intptr_t)device_get_ivars(dev); 123 ch->quirks = ctlr->quirks; 124 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF); 125 resource_int_value(device_get_name(dev), 126 device_get_unit(dev), "pm_level", &ch->pm_level); 127 if (ch->pm_level > 3) 128 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 129 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 130 resource_int_value(device_get_name(dev), 131 device_get_unit(dev), "sata_rev", &sata_rev); 132 for (i = 0; i < 16; i++) { 133 ch->user[i].revision = sata_rev; 134 ch->user[i].mode = 0; 135 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048; 136 ch->user[i].tags = MVS_MAX_SLOTS; 137 ch->curr[i] = ch->user[i]; 138 if (ch->pm_level) { 139 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 140 CTS_SATA_CAPS_H_APST | 141 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 142 } 143 ch->user[i].caps |= CTS_SATA_CAPS_H_AN; 144 } 145 rid = ch->unit; 146 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 147 &rid, RF_ACTIVE))) 148 return (ENXIO); 149 mvs_dmainit(dev); 150 mvs_slotsalloc(dev); 151 mvs_ch_init(dev); 152 mtx_lock(&ch->mtx); 153 rid = ATA_IRQ_RID; 154 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 155 &rid, RF_SHAREABLE | RF_ACTIVE))) { 156 device_printf(dev, "Unable to map interrupt\n"); 157 error = ENXIO; 158 goto err0; 159 } 160 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 161 mvs_ch_intr_locked, dev, &ch->ih))) { 162 device_printf(dev, "Unable to setup interrupt\n"); 163 error = ENXIO; 164 goto err1; 165 } 166 /* Create the device queue for our SIM. */ 167 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1); 168 if (devq == NULL) { 169 device_printf(dev, "Unable to allocate simq\n"); 170 error = ENOMEM; 171 goto err1; 172 } 173 /* Construct SIM entry */ 174 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch, 175 device_get_unit(dev), &ch->mtx, 176 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1, 177 devq); 178 if (ch->sim == NULL) { 179 cam_simq_free(devq); 180 device_printf(dev, "unable to allocate sim\n"); 181 error = ENOMEM; 182 goto err1; 183 } 184 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 185 device_printf(dev, "unable to register xpt bus\n"); 186 error = ENXIO; 187 goto err2; 188 } 189 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 190 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 191 device_printf(dev, "unable to create path\n"); 192 error = ENXIO; 193 goto err3; 194 } 195 if (ch->pm_level > 3) { 196 callout_reset(&ch->pm_timer, 197 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 198 mvs_ch_pm, dev); 199 } 200 mtx_unlock(&ch->mtx); 201 return (0); 202 203err3: 204 xpt_bus_deregister(cam_sim_path(ch->sim)); 205err2: 206 cam_sim_free(ch->sim, /*free_devq*/TRUE); 207err1: 208 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 209err0: 210 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 211 mtx_unlock(&ch->mtx); 212 mtx_destroy(&ch->mtx); 213 return (error); 214} 215 216static int 217mvs_ch_detach(device_t dev) 218{ 219 struct mvs_channel *ch = device_get_softc(dev); 220 221 mtx_lock(&ch->mtx); 222 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 223 /* Forget about reset. */ 224 if (ch->resetting) { 225 ch->resetting = 0; 226 xpt_release_simq(ch->sim, TRUE); 227 } 228 xpt_free_path(ch->path); 229 xpt_bus_deregister(cam_sim_path(ch->sim)); 230 cam_sim_free(ch->sim, /*free_devq*/TRUE); 231 mtx_unlock(&ch->mtx); 232 233 if (ch->pm_level > 3) 234 callout_drain(&ch->pm_timer); 235 callout_drain(&ch->reset_timer); 236 bus_teardown_intr(dev, ch->r_irq, ch->ih); 237 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 238 239 mvs_ch_deinit(dev); 240 mvs_slotsfree(dev); 241 mvs_dmafini(dev); 242 243 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 244 mtx_destroy(&ch->mtx); 245 return (0); 246} 247 248static int 249mvs_ch_init(device_t dev) 250{ 251 struct mvs_channel *ch = device_get_softc(dev); 252 uint32_t reg; 253 254 /* Disable port interrupts */ 255 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 256 /* Stop EDMA */ 257 ch->curr_mode = MVS_EDMA_UNKNOWN; 258 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 259 /* Clear and configure FIS interrupts. */ 260 ATA_OUTL(ch->r_mem, SATA_FISIC, 0); 261 reg = ATA_INL(ch->r_mem, SATA_FISC); 262 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 263 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 264 reg = ATA_INL(ch->r_mem, SATA_FISIM); 265 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 266 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 267 /* Clear SATA error register. */ 268 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 269 /* Clear any outstanding error interrupts. */ 270 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 271 /* Unmask all error interrupts */ 272 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 273 return (0); 274} 275 276static int 277mvs_ch_deinit(device_t dev) 278{ 279 struct mvs_channel *ch = device_get_softc(dev); 280 281 /* Stop EDMA */ 282 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 283 /* Disable port interrupts. */ 284 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 285 return (0); 286} 287 288static int 289mvs_ch_suspend(device_t dev) 290{ 291 struct mvs_channel *ch = device_get_softc(dev); 292 293 mtx_lock(&ch->mtx); 294 xpt_freeze_simq(ch->sim, 1); 295 while (ch->oslots) 296 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100); 297 /* Forget about reset. */ 298 if (ch->resetting) { 299 ch->resetting = 0; 300 callout_stop(&ch->reset_timer); 301 xpt_release_simq(ch->sim, TRUE); 302 } 303 mvs_ch_deinit(dev); 304 mtx_unlock(&ch->mtx); 305 return (0); 306} 307 308static int 309mvs_ch_resume(device_t dev) 310{ 311 struct mvs_channel *ch = device_get_softc(dev); 312 313 mtx_lock(&ch->mtx); 314 mvs_ch_init(dev); 315 mvs_reset(dev); 316 xpt_release_simq(ch->sim, TRUE); 317 mtx_unlock(&ch->mtx); 318 return (0); 319} 320 321struct mvs_dc_cb_args { 322 bus_addr_t maddr; 323 int error; 324}; 325 326static void 327mvs_dmainit(device_t dev) 328{ 329 struct mvs_channel *ch = device_get_softc(dev); 330 struct mvs_dc_cb_args dcba; 331 332 /* EDMA command request area. */ 333 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 334 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 335 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE, 336 0, NULL, NULL, &ch->dma.workrq_tag)) 337 goto error; 338 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0, 339 &ch->dma.workrq_map)) 340 goto error; 341 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, 342 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 343 dcba.error) { 344 bus_dmamem_free(ch->dma.workrq_tag, 345 ch->dma.workrq, ch->dma.workrq_map); 346 goto error; 347 } 348 ch->dma.workrq_bus = dcba.maddr; 349 /* EDMA command response area. */ 350 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0, 351 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 352 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE, 353 0, NULL, NULL, &ch->dma.workrp_tag)) 354 goto error; 355 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0, 356 &ch->dma.workrp_map)) 357 goto error; 358 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, 359 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 360 dcba.error) { 361 bus_dmamem_free(ch->dma.workrp_tag, 362 ch->dma.workrp, ch->dma.workrp_map); 363 goto error; 364 } 365 ch->dma.workrp_bus = dcba.maddr; 366 /* Data area. */ 367 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX, 368 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 369 NULL, NULL, 370 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS, 371 MVS_SG_ENTRIES, MVS_EPRD_MAX, 372 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 373 goto error; 374 } 375 return; 376 377error: 378 device_printf(dev, "WARNING - DMA initialization failed\n"); 379 mvs_dmafini(dev); 380} 381 382static void 383mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 384{ 385 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc; 386 387 if (!(dcba->error = error)) 388 dcba->maddr = segs[0].ds_addr; 389} 390 391static void 392mvs_dmafini(device_t dev) 393{ 394 struct mvs_channel *ch = device_get_softc(dev); 395 396 if (ch->dma.data_tag) { 397 bus_dma_tag_destroy(ch->dma.data_tag); 398 ch->dma.data_tag = NULL; 399 } 400 if (ch->dma.workrp_bus) { 401 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map); 402 bus_dmamem_free(ch->dma.workrp_tag, 403 ch->dma.workrp, ch->dma.workrp_map); 404 ch->dma.workrp_bus = 0; 405 ch->dma.workrp_map = NULL; 406 ch->dma.workrp = NULL; 407 } 408 if (ch->dma.workrp_tag) { 409 bus_dma_tag_destroy(ch->dma.workrp_tag); 410 ch->dma.workrp_tag = NULL; 411 } 412 if (ch->dma.workrq_bus) { 413 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map); 414 bus_dmamem_free(ch->dma.workrq_tag, 415 ch->dma.workrq, ch->dma.workrq_map); 416 ch->dma.workrq_bus = 0; 417 ch->dma.workrq_map = NULL; 418 ch->dma.workrq = NULL; 419 } 420 if (ch->dma.workrq_tag) { 421 bus_dma_tag_destroy(ch->dma.workrq_tag); 422 ch->dma.workrq_tag = NULL; 423 } 424} 425 426static void 427mvs_slotsalloc(device_t dev) 428{ 429 struct mvs_channel *ch = device_get_softc(dev); 430 int i; 431 432 /* Alloc and setup command/dma slots */ 433 bzero(ch->slot, sizeof(ch->slot)); 434 for (i = 0; i < MVS_MAX_SLOTS; i++) { 435 struct mvs_slot *slot = &ch->slot[i]; 436 437 slot->dev = dev; 438 slot->slot = i; 439 slot->state = MVS_SLOT_EMPTY; 440 slot->ccb = NULL; 441 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 442 443 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 444 device_printf(ch->dev, "FAILURE - create data_map\n"); 445 } 446} 447 448static void 449mvs_slotsfree(device_t dev) 450{ 451 struct mvs_channel *ch = device_get_softc(dev); 452 int i; 453 454 /* Free all dma slots */ 455 for (i = 0; i < MVS_MAX_SLOTS; i++) { 456 struct mvs_slot *slot = &ch->slot[i]; 457 458 callout_drain(&slot->timeout); 459 if (slot->dma.data_map) { 460 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 461 slot->dma.data_map = NULL; 462 } 463 } 464} 465 466static void 467mvs_setup_edma_queues(device_t dev) 468{ 469 struct mvs_channel *ch = device_get_softc(dev); 470 uint64_t work; 471 472 /* Requests queue. */ 473 work = ch->dma.workrq_bus; 474 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); 475 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); 476 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); 477 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 478 BUS_DMASYNC_PREWRITE); 479 /* Reponses queue. */ 480 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE); 481 work = ch->dma.workrp_bus; 482 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); 483 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff); 484 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff); 485 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 486 BUS_DMASYNC_PREREAD); 487 ch->out_idx = 0; 488 ch->in_idx = 0; 489} 490 491static void 492mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode) 493{ 494 struct mvs_channel *ch = device_get_softc(dev); 495 int timeout; 496 uint32_t ecfg, fcfg, hc, ltm, unkn; 497 498 if (mode == ch->curr_mode) 499 return; 500 /* If we are running, we should stop first. */ 501 if (ch->curr_mode != MVS_EDMA_OFF) { 502 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA); 503 timeout = 0; 504 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) { 505 DELAY(1000); 506 if (timeout++ > 1000) { 507 device_printf(dev, "stopping EDMA engine failed\n"); 508 break; 509 } 510 }; 511 } 512 ch->curr_mode = mode; 513 ch->fbs_enabled = 0; 514 ch->fake_busy = 0; 515 /* Report mode to controller. Needed for correct CCC operation. */ 516 MVS_EDMA(device_get_parent(dev), dev, mode); 517 /* Configure new mode. */ 518 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN; 519 if (ch->pm_present) { 520 ecfg |= EDMA_CFG_EMASKRXPM; 521 if (ch->quirks & MVS_Q_GENIIE) { 522 ecfg |= EDMA_CFG_EEDMAFBS; 523 ch->fbs_enabled = 1; 524 } 525 } 526 if (ch->quirks & MVS_Q_GENI) 527 ecfg |= EDMA_CFG_ERDBSZ; 528 else if (ch->quirks & MVS_Q_GENII) 529 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN; 530 if (ch->quirks & MVS_Q_CT) 531 ecfg |= EDMA_CFG_ECUTTHROUGHEN; 532 if (mode != MVS_EDMA_OFF) 533 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN; 534 if (mode == MVS_EDMA_QUEUED) 535 ecfg |= EDMA_CFG_EQUE; 536 else if (mode == MVS_EDMA_NCQ) 537 ecfg |= EDMA_CFG_ESATANATVCMDQUE; 538 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg); 539 mvs_setup_edma_queues(dev); 540 if (ch->quirks & MVS_Q_GENIIE) { 541 /* Configure FBS-related registers */ 542 fcfg = ATA_INL(ch->r_mem, SATA_FISC); 543 ltm = ATA_INL(ch->r_mem, SATA_LTM); 544 hc = ATA_INL(ch->r_mem, EDMA_HC); 545 if (ch->fbs_enabled) { 546 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP; 547 if (mode == MVS_EDMA_NCQ) { 548 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 549 hc &= ~EDMA_IE_EDEVERR; 550 } else { 551 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0; 552 hc |= EDMA_IE_EDEVERR; 553 } 554 ltm |= (1 << 8); 555 } else { 556 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP; 557 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 558 hc |= EDMA_IE_EDEVERR; 559 ltm &= ~(1 << 8); 560 } 561 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg); 562 ATA_OUTL(ch->r_mem, SATA_LTM, ltm); 563 ATA_OUTL(ch->r_mem, EDMA_HC, hc); 564 /* This is some magic, required to handle several DRQs 565 * with basic DMA. */ 566 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD); 567 if (mode == MVS_EDMA_OFF) 568 unkn |= 1; 569 else 570 unkn &= ~1; 571 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn); 572 } 573 /* Run EDMA. */ 574 if (mode != MVS_EDMA_OFF) 575 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA); 576} 577 578devclass_t mvs_devclass; 579devclass_t mvsch_devclass; 580static device_method_t mvsch_methods[] = { 581 DEVMETHOD(device_probe, mvs_ch_probe), 582 DEVMETHOD(device_attach, mvs_ch_attach), 583 DEVMETHOD(device_detach, mvs_ch_detach), 584 DEVMETHOD(device_suspend, mvs_ch_suspend), 585 DEVMETHOD(device_resume, mvs_ch_resume), 586 { 0, 0 } 587}; 588static driver_t mvsch_driver = { 589 "mvsch", 590 mvsch_methods, 591 sizeof(struct mvs_channel) 592}; 593DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0); 594DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0); 595 596static void 597mvs_phy_check_events(device_t dev, u_int32_t serr) 598{ 599 struct mvs_channel *ch = device_get_softc(dev); 600 601 if (ch->pm_level == 0) { 602 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS); 603 union ccb *ccb; 604 605 if (bootverbose) { 606 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 607 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 608 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) { 609 device_printf(dev, "CONNECT requested\n"); 610 } else 611 device_printf(dev, "DISCONNECT requested\n"); 612 } 613 mvs_reset(dev); 614 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 615 return; 616 if (xpt_create_path(&ccb->ccb_h.path, NULL, 617 cam_sim_path(ch->sim), 618 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 619 xpt_free_ccb(ccb); 620 return; 621 } 622 xpt_rescan(ccb); 623 } 624} 625 626static void 627mvs_notify_events(device_t dev) 628{ 629 struct mvs_channel *ch = device_get_softc(dev); 630 struct cam_path *dpath; 631 uint32_t fis; 632 int d; 633 634 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */ 635 fis = ATA_INL(ch->r_mem, SATA_FISDW0); 636 if ((fis & 0x80ff) == 0x80a1) 637 d = (fis & 0x0f00) >> 8; 638 else 639 d = ch->pm_present ? 15 : 0; 640 if (bootverbose) 641 device_printf(dev, "SNTF %d\n", d); 642 if (xpt_create_path(&dpath, NULL, 643 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) { 644 xpt_async(AC_SCSI_AEN, dpath, NULL); 645 xpt_free_path(dpath); 646 } 647} 648 649static void 650mvs_ch_intr_locked(void *data) 651{ 652 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 653 device_t dev = (device_t)arg->arg; 654 struct mvs_channel *ch = device_get_softc(dev); 655 656 mtx_lock(&ch->mtx); 657 xpt_batch_start(ch->sim); 658 mvs_ch_intr(data); 659 xpt_batch_done(ch->sim); 660 mtx_unlock(&ch->mtx); 661} 662 663static void 664mvs_ch_pm(void *arg) 665{ 666 device_t dev = (device_t)arg; 667 struct mvs_channel *ch = device_get_softc(dev); 668 uint32_t work; 669 670 if (ch->numrslots != 0) 671 return; 672 /* If we are idle - request power state transition. */ 673 work = ATA_INL(ch->r_mem, SATA_SC); 674 work &= ~SATA_SC_SPM_MASK; 675 if (ch->pm_level == 4) 676 work |= SATA_SC_SPM_PARTIAL; 677 else 678 work |= SATA_SC_SPM_SLUMBER; 679 ATA_OUTL(ch->r_mem, SATA_SC, work); 680} 681 682static void 683mvs_ch_pm_wake(device_t dev) 684{ 685 struct mvs_channel *ch = device_get_softc(dev); 686 uint32_t work; 687 int timeout = 0; 688 689 work = ATA_INL(ch->r_mem, SATA_SS); 690 if (work & SATA_SS_IPM_ACTIVE) 691 return; 692 /* If we are not in active state - request power state transition. */ 693 work = ATA_INL(ch->r_mem, SATA_SC); 694 work &= ~SATA_SC_SPM_MASK; 695 work |= SATA_SC_SPM_ACTIVE; 696 ATA_OUTL(ch->r_mem, SATA_SC, work); 697 /* Wait for transition to happen. */ 698 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 && 699 timeout++ < 100) { 700 DELAY(100); 701 } 702} 703 704static void 705mvs_ch_intr(void *data) 706{ 707 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 708 device_t dev = (device_t)arg->arg; 709 struct mvs_channel *ch = device_get_softc(dev); 710 uint32_t iec, serr = 0, fisic = 0; 711 enum mvs_err_type et; 712 int i, ccs, port = -1, selfdis = 0; 713 int edma = (ch->numtslots != 0 || ch->numdslots != 0); 714 715 /* New item in response queue. */ 716 if ((arg->cause & 2) && edma) 717 mvs_crbq_intr(dev); 718 /* Some error or special event. */ 719 if (arg->cause & 1) { 720 iec = ATA_INL(ch->r_mem, EDMA_IEC); 721 if (iec & EDMA_IE_SERRINT) { 722 serr = ATA_INL(ch->r_mem, SATA_SE); 723 ATA_OUTL(ch->r_mem, SATA_SE, serr); 724 } 725 /* EDMA self-disabled due to error. */ 726 if (iec & EDMA_IE_ESELFDIS) 727 selfdis = 1; 728 /* Transport interrupt. */ 729 if (iec & EDMA_IE_ETRANSINT) { 730 /* For Gen-I this bit means self-disable. */ 731 if (ch->quirks & MVS_Q_GENI) 732 selfdis = 1; 733 /* For Gen-II this bit means SDB-N. */ 734 else if (ch->quirks & MVS_Q_GENII) 735 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; 736 else /* For Gen-IIe - read FIS interrupt cause. */ 737 fisic = ATA_INL(ch->r_mem, SATA_FISIC); 738 } 739 if (selfdis) 740 ch->curr_mode = MVS_EDMA_UNKNOWN; 741 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec); 742 /* Interface errors or Device error. */ 743 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) { 744 port = -1; 745 if (ch->numpslots != 0) { 746 ccs = 0; 747 } else { 748 if (ch->quirks & MVS_Q_GENIIE) 749 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S)); 750 else 751 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S)); 752 /* Check if error is one-PMP-port-specific, */ 753 if (ch->fbs_enabled) { 754 /* Which ports were active. */ 755 for (i = 0; i < 16; i++) { 756 if (ch->numrslotspd[i] == 0) 757 continue; 758 if (port == -1) 759 port = i; 760 else if (port != i) { 761 port = -2; 762 break; 763 } 764 } 765 /* If several ports were active and EDMA still enabled - 766 * other ports are probably unaffected and may continue. 767 */ 768 if (port == -2 && !selfdis) { 769 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16; 770 port = ffs(p) - 1; 771 if (port != (fls(p) - 1)) 772 port = -2; 773 } 774 } 775 } 776 mvs_requeue_frozen(dev); 777 for (i = 0; i < MVS_MAX_SLOTS; i++) { 778 /* XXX: reqests in loading state. */ 779 if (((ch->rslots >> i) & 1) == 0) 780 continue; 781 if (port >= 0 && 782 ch->slot[i].ccb->ccb_h.target_id != port) 783 continue; 784 if (iec & EDMA_IE_EDEVERR) { /* Device error. */ 785 if (port != -2) { 786 if (ch->numtslots == 0) { 787 /* Untagged operation. */ 788 if (i == ccs) 789 et = MVS_ERR_TFE; 790 else 791 et = MVS_ERR_INNOCENT; 792 } else { 793 /* Tagged operation. */ 794 et = MVS_ERR_NCQ; 795 } 796 } else { 797 et = MVS_ERR_TFE; 798 ch->fatalerr = 1; 799 } 800 } else if (iec & 0xfc1e9000) { 801 if (ch->numtslots == 0 && 802 i != ccs && port != -2) 803 et = MVS_ERR_INNOCENT; 804 else 805 et = MVS_ERR_SATA; 806 } else 807 et = MVS_ERR_INVALID; 808 mvs_end_transaction(&ch->slot[i], et); 809 } 810 } 811 /* Process SDB-N. */ 812 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1) 813 mvs_notify_events(dev); 814 if (fisic) 815 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic); 816 /* Process hot-plug. */ 817 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) || 818 (serr & SATA_SE_PHY_CHANGED)) 819 mvs_phy_check_events(dev, serr); 820 } 821 /* Legacy mode device interrupt. */ 822 if ((arg->cause & 2) && !edma) 823 mvs_legacy_intr(dev, arg->cause & 4); 824} 825 826static uint8_t 827mvs_getstatus(device_t dev, int clear) 828{ 829 struct mvs_channel *ch = device_get_softc(dev); 830 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT); 831 832 if (ch->fake_busy) { 833 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR)) 834 ch->fake_busy = 0; 835 else 836 status |= ATA_S_BUSY; 837 } 838 return (status); 839} 840 841static void 842mvs_legacy_intr(device_t dev, int poll) 843{ 844 struct mvs_channel *ch = device_get_softc(dev); 845 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */ 846 union ccb *ccb = slot->ccb; 847 enum mvs_err_type et = MVS_ERR_NONE; 848 int port; 849 u_int length, resid, size; 850 uint8_t buf[2]; 851 uint8_t status, ireason; 852 853 /* Clear interrupt and get status. */ 854 status = mvs_getstatus(dev, 1); 855 if (slot->state < MVS_SLOT_RUNNING) 856 return; 857 port = ccb->ccb_h.target_id & 0x0f; 858 /* Wait a bit for late !BUSY status update. */ 859 if (status & ATA_S_BUSY) { 860 if (poll) 861 return; 862 DELAY(100); 863 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) { 864 DELAY(1000); 865 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) 866 return; 867 } 868 } 869 /* If we got an error, we are done. */ 870 if (status & ATA_S_ERROR) { 871 et = MVS_ERR_TFE; 872 goto end_finished; 873 } 874 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */ 875 ccb->ataio.res.status = status; 876 /* Are we moving data? */ 877 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 878 /* If data read command - get them. */ 879 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 880 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 881 device_printf(dev, "timeout waiting for read DRQ\n"); 882 et = MVS_ERR_TIMEOUT; 883 xpt_freeze_simq(ch->sim, 1); 884 ch->toslots |= (1 << slot->slot); 885 goto end_finished; 886 } 887 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 888 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 889 ch->transfersize / 2); 890 } 891 /* Update how far we've gotten. */ 892 ch->donecount += ch->transfersize; 893 /* Do we need more? */ 894 if (ccb->ataio.dxfer_len > ch->donecount) { 895 /* Set this transfer size according to HW capabilities */ 896 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount, 897 ch->transfersize); 898 /* If data write command - put them */ 899 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 900 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 901 device_printf(dev, 902 "timeout waiting for write DRQ\n"); 903 et = MVS_ERR_TIMEOUT; 904 xpt_freeze_simq(ch->sim, 1); 905 ch->toslots |= (1 << slot->slot); 906 goto end_finished; 907 } 908 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 909 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 910 ch->transfersize / 2); 911 return; 912 } 913 /* If data read command, return & wait for interrupt */ 914 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 915 return; 916 } 917 } 918 } else if (ch->basic_dma) { /* ATAPI DMA */ 919 if (status & ATA_S_DWF) 920 et = MVS_ERR_TFE; 921 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR) 922 et = MVS_ERR_TFE; 923 /* Stop basic DMA. */ 924 ATA_OUTL(ch->r_mem, DMA_C, 0); 925 goto end_finished; 926 } else { /* ATAPI PIO */ 927 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | 928 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); 929 size = min(ch->transfersize, length); 930 ireason = ATA_INB(ch->r_mem,ATA_IREASON); 931 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) | 932 (status & ATA_S_DRQ)) { 933 934 case ATAPI_P_CMDOUT: 935 device_printf(dev, "ATAPI CMDOUT\n"); 936 /* Return wait for interrupt */ 937 return; 938 939 case ATAPI_P_WRITE: 940 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 941 device_printf(dev, "trying to write on read buffer\n"); 942 et = MVS_ERR_TFE; 943 goto end_finished; 944 break; 945 } 946 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 947 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 948 (size + 1) / 2); 949 for (resid = ch->transfersize + (size & 1); 950 resid < length; resid += sizeof(int16_t)) 951 ATA_OUTW(ch->r_mem, ATA_DATA, 0); 952 ch->donecount += length; 953 /* Set next transfer size according to HW capabilities */ 954 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 955 ch->curr[ccb->ccb_h.target_id].bytecount); 956 /* Return wait for interrupt */ 957 return; 958 959 case ATAPI_P_READ: 960 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 961 device_printf(dev, "trying to read on write buffer\n"); 962 et = MVS_ERR_TFE; 963 goto end_finished; 964 } 965 if (size >= 2) { 966 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 967 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 968 size / 2); 969 } 970 if (size & 1) { 971 ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1); 972 ((uint8_t *)ccb->csio.data_ptr + ch->donecount + 973 (size & ~1))[0] = buf[0]; 974 } 975 for (resid = ch->transfersize + (size & 1); 976 resid < length; resid += sizeof(int16_t)) 977 ATA_INW(ch->r_mem, ATA_DATA); 978 ch->donecount += length; 979 /* Set next transfer size according to HW capabilities */ 980 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 981 ch->curr[ccb->ccb_h.target_id].bytecount); 982 /* Return wait for interrupt */ 983 return; 984 985 case ATAPI_P_DONEDRQ: 986 device_printf(dev, 987 "WARNING - DONEDRQ non conformant device\n"); 988 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 989 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 990 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 991 length / 2); 992 ch->donecount += length; 993 } 994 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 995 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 996 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 997 length / 2); 998 ch->donecount += length; 999 } 1000 else 1001 et = MVS_ERR_TFE; 1002 /* FALLTHROUGH */ 1003 1004 case ATAPI_P_ABORT: 1005 case ATAPI_P_DONE: 1006 if (status & (ATA_S_ERROR | ATA_S_DWF)) 1007 et = MVS_ERR_TFE; 1008 goto end_finished; 1009 1010 default: 1011 device_printf(dev, "unknown transfer phase" 1012 " (status %02x, ireason %02x)\n", 1013 status, ireason); 1014 et = MVS_ERR_TFE; 1015 } 1016 } 1017 1018end_finished: 1019 mvs_end_transaction(slot, et); 1020} 1021 1022static void 1023mvs_crbq_intr(device_t dev) 1024{ 1025 struct mvs_channel *ch = device_get_softc(dev); 1026 struct mvs_crpb *crpb; 1027 union ccb *ccb; 1028 int in_idx, fin_idx, cin_idx, slot; 1029 uint32_t val; 1030 uint16_t flags; 1031 1032 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 1033 if (val == 0) 1034 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 1035 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >> 1036 EDMA_RESQP_ERPQP_SHIFT; 1037 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1038 BUS_DMASYNC_POSTREAD); 1039 fin_idx = cin_idx = ch->in_idx; 1040 ch->in_idx = in_idx; 1041 while (in_idx != cin_idx) { 1042 crpb = (struct mvs_crpb *) 1043 (ch->dma.workrp + MVS_CRPB_OFFSET + 1044 (MVS_CRPB_SIZE * cin_idx)); 1045 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK; 1046 flags = le16toh(crpb->rspflg); 1047 /* 1048 * Handle only successfull completions here. 1049 * Errors will be handled by main intr handler. 1050 */ 1051#if defined(__i386__) || defined(__amd64__) 1052 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) { 1053 device_printf(dev, "Unfilled CRPB " 1054 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1055 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots); 1056 } else 1057#endif 1058 if (ch->numtslots != 0 || 1059 (flags & EDMA_IE_EDEVERR) == 0) { 1060#if defined(__i386__) || defined(__amd64__) 1061 crpb->id = 0xffff; 1062 crpb->rspflg = 0xffff; 1063#endif 1064 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) { 1065 ccb = ch->slot[slot].ccb; 1066 ccb->ataio.res.status = 1067 (flags & MVS_CRPB_ATASTS_MASK) >> 1068 MVS_CRPB_ATASTS_SHIFT; 1069 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE); 1070 } else { 1071 device_printf(dev, "Unused tag in CRPB " 1072 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1073 cin_idx, fin_idx, in_idx, slot, flags, 1074 ch->rslots); 1075 } 1076 } else { 1077 device_printf(dev, 1078 "CRPB with error %d tag %d flags %04x\n", 1079 cin_idx, slot, flags); 1080 } 1081 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1); 1082 } 1083 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1084 BUS_DMASYNC_PREREAD); 1085 if (cin_idx == ch->in_idx) { 1086 ATA_OUTL(ch->r_mem, EDMA_RESQOP, 1087 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT)); 1088 } 1089} 1090 1091/* Must be called with channel locked. */ 1092static int 1093mvs_check_collision(device_t dev, union ccb *ccb) 1094{ 1095 struct mvs_channel *ch = device_get_softc(dev); 1096 1097 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1098 /* NCQ DMA */ 1099 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1100 /* Can't mix NCQ and non-NCQ DMA commands. */ 1101 if (ch->numdslots != 0) 1102 return (1); 1103 /* Can't mix NCQ and PIO commands. */ 1104 if (ch->numpslots != 0) 1105 return (1); 1106 /* If we have no FBS */ 1107 if (!ch->fbs_enabled) { 1108 /* Tagged command while tagged to other target is active. */ 1109 if (ch->numtslots != 0 && 1110 ch->taggedtarget != ccb->ccb_h.target_id) 1111 return (1); 1112 } 1113 /* Non-NCQ DMA */ 1114 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1115 /* Can't mix non-NCQ DMA and NCQ commands. */ 1116 if (ch->numtslots != 0) 1117 return (1); 1118 /* Can't mix non-NCQ DMA and PIO commands. */ 1119 if (ch->numpslots != 0) 1120 return (1); 1121 /* PIO */ 1122 } else { 1123 /* Can't mix PIO with anything. */ 1124 if (ch->numrslots != 0) 1125 return (1); 1126 } 1127 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1128 /* Atomic command while anything active. */ 1129 if (ch->numrslots != 0) 1130 return (1); 1131 } 1132 } else { /* ATAPI */ 1133 /* ATAPI goes without EDMA, so can't mix it with anything. */ 1134 if (ch->numrslots != 0) 1135 return (1); 1136 } 1137 /* We have some atomic command running. */ 1138 if (ch->aslots != 0) 1139 return (1); 1140 return (0); 1141} 1142 1143static void 1144mvs_tfd_read(device_t dev, union ccb *ccb) 1145{ 1146 struct mvs_channel *ch = device_get_softc(dev); 1147 struct ata_res *res = &ccb->ataio.res; 1148 1149 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT); 1150 res->error = ATA_INB(ch->r_mem, ATA_ERROR); 1151 res->device = ATA_INB(ch->r_mem, ATA_DRIVE); 1152 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB); 1153 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT); 1154 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR); 1155 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1156 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1157 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1158 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT); 1159 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR); 1160 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1161 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1162} 1163 1164static void 1165mvs_tfd_write(device_t dev, union ccb *ccb) 1166{ 1167 struct mvs_channel *ch = device_get_softc(dev); 1168 struct ata_cmd *cmd = &ccb->ataio.cmd; 1169 1170 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device); 1171 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control); 1172 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp); 1173 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features); 1174 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp); 1175 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count); 1176 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp); 1177 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low); 1178 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp); 1179 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid); 1180 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp); 1181 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high); 1182 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command); 1183} 1184 1185 1186/* Must be called with channel locked. */ 1187static void 1188mvs_begin_transaction(device_t dev, union ccb *ccb) 1189{ 1190 struct mvs_channel *ch = device_get_softc(dev); 1191 struct mvs_slot *slot; 1192 int slotn, tag; 1193 1194 if (ch->pm_level > 0) 1195 mvs_ch_pm_wake(dev); 1196 /* Softreset is a special case. */ 1197 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1198 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1199 mvs_softreset(dev, ccb); 1200 return; 1201 } 1202 /* Choose empty slot. */ 1203 slotn = ffs(~ch->oslots) - 1; 1204 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1205 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1206 if (ch->quirks & MVS_Q_GENIIE) 1207 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1; 1208 else 1209 tag = slotn; 1210 } else 1211 tag = 0; 1212 /* Occupy chosen slot. */ 1213 slot = &ch->slot[slotn]; 1214 slot->ccb = ccb; 1215 slot->tag = tag; 1216 /* Stop PM timer. */ 1217 if (ch->numrslots == 0 && ch->pm_level > 3) 1218 callout_stop(&ch->pm_timer); 1219 /* Update channel stats. */ 1220 ch->oslots |= (1 << slot->slot); 1221 ch->numrslots++; 1222 ch->numrslotspd[ccb->ccb_h.target_id]++; 1223 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1224 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1225 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag); 1226 ch->numtslots++; 1227 ch->numtslotspd[ccb->ccb_h.target_id]++; 1228 ch->taggedtarget = ccb->ccb_h.target_id; 1229 mvs_set_edma_mode(dev, MVS_EDMA_NCQ); 1230 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1231 ch->numdslots++; 1232 mvs_set_edma_mode(dev, MVS_EDMA_ON); 1233 } else { 1234 ch->numpslots++; 1235 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1236 } 1237 if (ccb->ataio.cmd.flags & 1238 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1239 ch->aslots |= (1 << slot->slot); 1240 } 1241 } else { 1242 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1243 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes; 1244 ch->numpslots++; 1245 /* Use ATAPI DMA only for commands without under-/overruns. */ 1246 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1247 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA && 1248 (ch->quirks & MVS_Q_SOC) == 0 && 1249 (cdb[0] == 0x08 || 1250 cdb[0] == 0x0a || 1251 cdb[0] == 0x28 || 1252 cdb[0] == 0x2a || 1253 cdb[0] == 0x88 || 1254 cdb[0] == 0x8a || 1255 cdb[0] == 0xa8 || 1256 cdb[0] == 0xaa || 1257 cdb[0] == 0xbe)) { 1258 ch->basic_dma = 1; 1259 } 1260 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1261 } 1262 if (ch->numpslots == 0 || ch->basic_dma) { 1263 slot->state = MVS_SLOT_LOADING; 1264 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, 1265 ccb, mvs_dmasetprd, slot, 0); 1266 } else 1267 mvs_legacy_execute_transaction(slot); 1268} 1269 1270/* Locked by busdma engine. */ 1271static void 1272mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1273{ 1274 struct mvs_slot *slot = arg; 1275 struct mvs_channel *ch = device_get_softc(slot->dev); 1276 struct mvs_eprd *eprd; 1277 int i; 1278 1279 if (error) { 1280 device_printf(slot->dev, "DMA load error\n"); 1281 mvs_end_transaction(slot, MVS_ERR_INVALID); 1282 return; 1283 } 1284 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n")); 1285 /* If there is only one segment - no need to use S/G table on Gen-IIe. */ 1286 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) { 1287 slot->dma.addr = segs[0].ds_addr; 1288 slot->dma.len = segs[0].ds_len; 1289 } else { 1290 slot->dma.addr = 0; 1291 /* Get a piece of the workspace for this EPRD */ 1292 eprd = (struct mvs_eprd *) 1293 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot)); 1294 /* Fill S/G table */ 1295 for (i = 0; i < nsegs; i++) { 1296 eprd[i].prdbal = htole32(segs[i].ds_addr); 1297 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK); 1298 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16); 1299 } 1300 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF); 1301 } 1302 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1303 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1304 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1305 if (ch->basic_dma) 1306 mvs_legacy_execute_transaction(slot); 1307 else 1308 mvs_execute_transaction(slot); 1309} 1310 1311static void 1312mvs_legacy_execute_transaction(struct mvs_slot *slot) 1313{ 1314 device_t dev = slot->dev; 1315 struct mvs_channel *ch = device_get_softc(dev); 1316 bus_addr_t eprd; 1317 union ccb *ccb = slot->ccb; 1318 int port = ccb->ccb_h.target_id & 0x0f; 1319 int timeout; 1320 1321 slot->state = MVS_SLOT_RUNNING; 1322 ch->rslots |= (1 << slot->slot); 1323 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1324 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1325 mvs_tfd_write(dev, ccb); 1326 /* Device reset doesn't interrupt. */ 1327 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { 1328 int timeout = 1000000; 1329 do { 1330 DELAY(10); 1331 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS); 1332 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--); 1333 mvs_legacy_intr(dev, 1); 1334 return; 1335 } 1336 ch->donecount = 0; 1337 if (ccb->ataio.cmd.command == ATA_READ_MUL || 1338 ccb->ataio.cmd.command == ATA_READ_MUL48 || 1339 ccb->ataio.cmd.command == ATA_WRITE_MUL || 1340 ccb->ataio.cmd.command == ATA_WRITE_MUL48) { 1341 ch->transfersize = min(ccb->ataio.dxfer_len, 1342 ch->curr[port].bytecount); 1343 } else 1344 ch->transfersize = min(ccb->ataio.dxfer_len, 512); 1345 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1346 ch->fake_busy = 1; 1347 /* If data write command - output the data */ 1348 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1349 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 1350 device_printf(dev, 1351 "timeout waiting for write DRQ\n"); 1352 xpt_freeze_simq(ch->sim, 1); 1353 ch->toslots |= (1 << slot->slot); 1354 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1355 return; 1356 } 1357 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1358 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 1359 ch->transfersize / 2); 1360 } 1361 } else { 1362 ch->donecount = 0; 1363 ch->transfersize = min(ccb->csio.dxfer_len, 1364 ch->curr[port].bytecount); 1365 /* Write ATA PACKET command. */ 1366 if (ch->basic_dma) { 1367 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA); 1368 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); 1369 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0); 1370 } else { 1371 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0); 1372 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize); 1373 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8); 1374 } 1375 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD); 1376 ch->fake_busy = 1; 1377 /* Wait for ready to write ATAPI command block */ 1378 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) { 1379 device_printf(dev, "timeout waiting for ATAPI !BUSY\n"); 1380 xpt_freeze_simq(ch->sim, 1); 1381 ch->toslots |= (1 << slot->slot); 1382 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1383 return; 1384 } 1385 timeout = 5000; 1386 while (timeout--) { 1387 int reason = ATA_INB(ch->r_mem, ATA_IREASON); 1388 int status = ATA_INB(ch->r_mem, ATA_STATUS); 1389 1390 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 1391 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 1392 break; 1393 DELAY(20); 1394 } 1395 if (timeout <= 0) { 1396 device_printf(dev, 1397 "timeout waiting for ATAPI command ready\n"); 1398 xpt_freeze_simq(ch->sim, 1); 1399 ch->toslots |= (1 << slot->slot); 1400 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1401 return; 1402 } 1403 /* Write ATAPI command. */ 1404 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1405 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1406 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes), 1407 ch->curr[port].atapi / 2); 1408 DELAY(10); 1409 if (ch->basic_dma) { 1410 /* Start basic DMA. */ 1411 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + 1412 (MVS_EPRD_SIZE * slot->slot); 1413 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); 1414 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); 1415 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | 1416 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? 1417 DMA_C_READ : 0)); 1418 } 1419 } 1420 /* Start command execution timeout */ 1421 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1422 (timeout_t*)mvs_timeout, slot); 1423} 1424 1425/* Must be called with channel locked. */ 1426static void 1427mvs_execute_transaction(struct mvs_slot *slot) 1428{ 1429 device_t dev = slot->dev; 1430 struct mvs_channel *ch = device_get_softc(dev); 1431 bus_addr_t eprd; 1432 struct mvs_crqb *crqb; 1433 struct mvs_crqb_gen2e *crqb2e; 1434 union ccb *ccb = slot->ccb; 1435 int port = ccb->ccb_h.target_id & 0x0f; 1436 int i; 1437 1438 /* Get address of the prepared EPRD */ 1439 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); 1440 /* Prepare CRQB. Gen IIe uses different CRQB format. */ 1441 if (ch->quirks & MVS_Q_GENIIE) { 1442 crqb2e = (struct mvs_crqb_gen2e *) 1443 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1444 crqb2e->ctrlflg = htole32( 1445 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) | 1446 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) | 1447 (port << MVS_CRQB2E_PMP_SHIFT) | 1448 (slot->slot << MVS_CRQB2E_HTAG_SHIFT)); 1449 /* If there is only one segment - no need to use S/G table. */ 1450 if (slot->dma.addr != 0) { 1451 eprd = slot->dma.addr; 1452 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD); 1453 crqb2e->drbc = slot->dma.len; 1454 } 1455 crqb2e->cprdbl = htole32(eprd); 1456 crqb2e->cprdbh = htole32((eprd >> 16) >> 16); 1457 crqb2e->cmd[0] = 0; 1458 crqb2e->cmd[1] = 0; 1459 crqb2e->cmd[2] = ccb->ataio.cmd.command; 1460 crqb2e->cmd[3] = ccb->ataio.cmd.features; 1461 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low; 1462 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid; 1463 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high; 1464 crqb2e->cmd[7] = ccb->ataio.cmd.device; 1465 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp; 1466 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp; 1467 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp; 1468 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp; 1469 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1470 crqb2e->cmd[12] = slot->tag << 3; 1471 crqb2e->cmd[13] = 0; 1472 } else { 1473 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count; 1474 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp; 1475 } 1476 crqb2e->cmd[14] = 0; 1477 crqb2e->cmd[15] = 0; 1478 } else { 1479 crqb = (struct mvs_crqb *) 1480 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1481 crqb->cprdbl = htole32(eprd); 1482 crqb->cprdbh = htole32((eprd >> 16) >> 16); 1483 crqb->ctrlflg = htole16( 1484 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) | 1485 (slot->slot << MVS_CRQB_TAG_SHIFT) | 1486 (port << MVS_CRQB_PMP_SHIFT)); 1487 i = 0; 1488 /* 1489 * Controller can handle only 11 of 12 ATA registers, 1490 * so we have to choose which one to skip. 1491 */ 1492 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1493 crqb->cmd[i++] = ccb->ataio.cmd.features_exp; 1494 crqb->cmd[i++] = 0x11; 1495 } 1496 crqb->cmd[i++] = ccb->ataio.cmd.features; 1497 crqb->cmd[i++] = 0x11; 1498 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1499 crqb->cmd[i++] = slot->tag << 3; 1500 crqb->cmd[i++] = 0x12; 1501 } else { 1502 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp; 1503 crqb->cmd[i++] = 0x12; 1504 crqb->cmd[i++] = ccb->ataio.cmd.sector_count; 1505 crqb->cmd[i++] = 0x12; 1506 } 1507 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp; 1508 crqb->cmd[i++] = 0x13; 1509 crqb->cmd[i++] = ccb->ataio.cmd.lba_low; 1510 crqb->cmd[i++] = 0x13; 1511 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp; 1512 crqb->cmd[i++] = 0x14; 1513 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid; 1514 crqb->cmd[i++] = 0x14; 1515 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp; 1516 crqb->cmd[i++] = 0x15; 1517 crqb->cmd[i++] = ccb->ataio.cmd.lba_high; 1518 crqb->cmd[i++] = 0x15; 1519 crqb->cmd[i++] = ccb->ataio.cmd.device; 1520 crqb->cmd[i++] = 0x16; 1521 crqb->cmd[i++] = ccb->ataio.cmd.command; 1522 crqb->cmd[i++] = 0x97; 1523 } 1524 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1525 BUS_DMASYNC_PREWRITE); 1526 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1527 BUS_DMASYNC_PREREAD); 1528 slot->state = MVS_SLOT_RUNNING; 1529 ch->rslots |= (1 << slot->slot); 1530 /* Issue command to the controller. */ 1531 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); 1532 ATA_OUTL(ch->r_mem, EDMA_REQQIP, 1533 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1534 /* Start command execution timeout */ 1535 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1536 (timeout_t*)mvs_timeout, slot); 1537 return; 1538} 1539 1540/* Must be called with channel locked. */ 1541static void 1542mvs_process_timeout(device_t dev) 1543{ 1544 struct mvs_channel *ch = device_get_softc(dev); 1545 int i; 1546 1547 mtx_assert(&ch->mtx, MA_OWNED); 1548 /* Handle the rest of commands. */ 1549 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1550 /* Do we have a running request on slot? */ 1551 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1552 continue; 1553 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT); 1554 } 1555} 1556 1557/* Must be called with channel locked. */ 1558static void 1559mvs_rearm_timeout(device_t dev) 1560{ 1561 struct mvs_channel *ch = device_get_softc(dev); 1562 int i; 1563 1564 mtx_assert(&ch->mtx, MA_OWNED); 1565 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1566 struct mvs_slot *slot = &ch->slot[i]; 1567 1568 /* Do we have a running request on slot? */ 1569 if (slot->state < MVS_SLOT_RUNNING) 1570 continue; 1571 if ((ch->toslots & (1 << i)) == 0) 1572 continue; 1573 callout_reset(&slot->timeout, 1574 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1575 (timeout_t*)mvs_timeout, slot); 1576 } 1577} 1578 1579/* Locked by callout mechanism. */ 1580static void 1581mvs_timeout(struct mvs_slot *slot) 1582{ 1583 device_t dev = slot->dev; 1584 struct mvs_channel *ch = device_get_softc(dev); 1585 1586 /* Check for stale timeout. */ 1587 if (slot->state < MVS_SLOT_RUNNING) 1588 return; 1589 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1590 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x " 1591 "dma_c %08x dma_s %08x rs %08x status %02x\n", 1592 ATA_INL(ch->r_mem, EDMA_IEC), 1593 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE), 1594 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), 1595 ATA_INL(ch->r_mem, DMA_S), ch->rslots, 1596 ATA_INB(ch->r_mem, ATA_ALTSTAT)); 1597 /* Handle frozen command. */ 1598 mvs_requeue_frozen(dev); 1599 /* We wait for other commands timeout and pray. */ 1600 if (ch->toslots == 0) 1601 xpt_freeze_simq(ch->sim, 1); 1602 ch->toslots |= (1 << slot->slot); 1603 if ((ch->rslots & ~ch->toslots) == 0) 1604 mvs_process_timeout(dev); 1605 else 1606 device_printf(dev, " ... waiting for slots %08x\n", 1607 ch->rslots & ~ch->toslots); 1608} 1609 1610/* Must be called with channel locked. */ 1611static void 1612mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et) 1613{ 1614 device_t dev = slot->dev; 1615 struct mvs_channel *ch = device_get_softc(dev); 1616 union ccb *ccb = slot->ccb; 1617 int lastto; 1618 1619 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1620 BUS_DMASYNC_POSTWRITE); 1621 /* Read result registers to the result struct 1622 * May be incorrect if several commands finished same time, 1623 * so read only when sure or have to. 1624 */ 1625 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1626 struct ata_res *res = &ccb->ataio.res; 1627 1628 if ((et == MVS_ERR_TFE) || 1629 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1630 mvs_tfd_read(dev, ccb); 1631 } else 1632 bzero(res, sizeof(*res)); 1633 } else { 1634 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1635 ch->basic_dma == 0) 1636 ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount; 1637 } 1638 if (ch->numpslots == 0 || ch->basic_dma) { 1639 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1640 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1641 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1642 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1643 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1644 } 1645 } 1646 if (et != MVS_ERR_NONE) 1647 ch->eslots |= (1 << slot->slot); 1648 /* In case of error, freeze device for proper recovery. */ 1649 if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) && 1650 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1651 xpt_freeze_devq(ccb->ccb_h.path, 1); 1652 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1653 } 1654 /* Set proper result status. */ 1655 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1656 switch (et) { 1657 case MVS_ERR_NONE: 1658 ccb->ccb_h.status |= CAM_REQ_CMP; 1659 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1660 ccb->csio.scsi_status = SCSI_STATUS_OK; 1661 break; 1662 case MVS_ERR_INVALID: 1663 ch->fatalerr = 1; 1664 ccb->ccb_h.status |= CAM_REQ_INVALID; 1665 break; 1666 case MVS_ERR_INNOCENT: 1667 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1668 break; 1669 case MVS_ERR_TFE: 1670 case MVS_ERR_NCQ: 1671 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1672 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1673 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1674 } else { 1675 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1676 } 1677 break; 1678 case MVS_ERR_SATA: 1679 ch->fatalerr = 1; 1680 if (!ch->recoverycmd) { 1681 xpt_freeze_simq(ch->sim, 1); 1682 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1683 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1684 } 1685 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1686 break; 1687 case MVS_ERR_TIMEOUT: 1688 if (!ch->recoverycmd) { 1689 xpt_freeze_simq(ch->sim, 1); 1690 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1691 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1692 } 1693 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1694 break; 1695 default: 1696 ch->fatalerr = 1; 1697 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1698 } 1699 /* Free slot. */ 1700 ch->oslots &= ~(1 << slot->slot); 1701 ch->rslots &= ~(1 << slot->slot); 1702 ch->aslots &= ~(1 << slot->slot); 1703 slot->state = MVS_SLOT_EMPTY; 1704 slot->ccb = NULL; 1705 /* Update channel stats. */ 1706 ch->numrslots--; 1707 ch->numrslotspd[ccb->ccb_h.target_id]--; 1708 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1709 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1710 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag); 1711 ch->numtslots--; 1712 ch->numtslotspd[ccb->ccb_h.target_id]--; 1713 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1714 ch->numdslots--; 1715 } else { 1716 ch->numpslots--; 1717 } 1718 } else { 1719 ch->numpslots--; 1720 ch->basic_dma = 0; 1721 } 1722 /* Cancel timeout state if request completed normally. */ 1723 if (et != MVS_ERR_TIMEOUT) { 1724 lastto = (ch->toslots == (1 << slot->slot)); 1725 ch->toslots &= ~(1 << slot->slot); 1726 if (lastto) 1727 xpt_release_simq(ch->sim, TRUE); 1728 } 1729 /* If it was our READ LOG command - process it. */ 1730 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1731 mvs_process_read_log(dev, ccb); 1732 /* If it was our REQUEST SENSE command - process it. */ 1733 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1734 mvs_process_request_sense(dev, ccb); 1735 /* If it was NCQ or ATAPI command error, put result on hold. */ 1736 } else if (et == MVS_ERR_NCQ || 1737 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1738 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1739 ch->hold[slot->slot] = ccb; 1740 ch->holdtag[slot->slot] = slot->tag; 1741 ch->numhslots++; 1742 } else 1743 xpt_done(ccb); 1744 /* If we have no other active commands, ... */ 1745 if (ch->rslots == 0) { 1746 /* if there was fatal error - reset port. */ 1747 if (ch->toslots != 0 || ch->fatalerr) { 1748 mvs_reset(dev); 1749 } else { 1750 /* if we have slots in error, we can reinit port. */ 1751 if (ch->eslots != 0) { 1752 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1753 ch->eslots = 0; 1754 } 1755 /* if there commands on hold, we can do READ LOG. */ 1756 if (!ch->recoverycmd && ch->numhslots) 1757 mvs_issue_recovery(dev); 1758 } 1759 /* If all the rest of commands are in timeout - give them chance. */ 1760 } else if ((ch->rslots & ~ch->toslots) == 0 && 1761 et != MVS_ERR_TIMEOUT) 1762 mvs_rearm_timeout(dev); 1763 /* Unfreeze frozen command. */ 1764 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) { 1765 union ccb *fccb = ch->frozen; 1766 ch->frozen = NULL; 1767 mvs_begin_transaction(dev, fccb); 1768 xpt_release_simq(ch->sim, TRUE); 1769 } 1770 /* Start PM timer. */ 1771 if (ch->numrslots == 0 && ch->pm_level > 3 && 1772 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1773 callout_schedule(&ch->pm_timer, 1774 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1775 } 1776} 1777 1778static void 1779mvs_issue_recovery(device_t dev) 1780{ 1781 struct mvs_channel *ch = device_get_softc(dev); 1782 union ccb *ccb; 1783 struct ccb_ataio *ataio; 1784 struct ccb_scsiio *csio; 1785 int i; 1786 1787 /* Find some held command. */ 1788 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1789 if (ch->hold[i]) 1790 break; 1791 } 1792 ccb = xpt_alloc_ccb_nowait(); 1793 if (ccb == NULL) { 1794 device_printf(dev, "Unable to allocate recovery command\n"); 1795completeall: 1796 /* We can't do anything -- complete held commands. */ 1797 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1798 if (ch->hold[i] == NULL) 1799 continue; 1800 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1801 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 1802 xpt_done(ch->hold[i]); 1803 ch->hold[i] = NULL; 1804 ch->numhslots--; 1805 } 1806 mvs_reset(dev); 1807 return; 1808 } 1809 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1810 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1811 /* READ LOG */ 1812 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 1813 ccb->ccb_h.func_code = XPT_ATA_IO; 1814 ccb->ccb_h.flags = CAM_DIR_IN; 1815 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1816 ataio = &ccb->ataio; 1817 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT); 1818 if (ataio->data_ptr == NULL) { 1819 xpt_free_ccb(ccb); 1820 device_printf(dev, 1821 "Unable to allocate memory for READ LOG command\n"); 1822 goto completeall; 1823 } 1824 ataio->dxfer_len = 512; 1825 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1826 ataio->cmd.flags = CAM_ATAIO_48BIT; 1827 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1828 ataio->cmd.sector_count = 1; 1829 ataio->cmd.sector_count_exp = 0; 1830 ataio->cmd.lba_low = 0x10; 1831 ataio->cmd.lba_mid = 0; 1832 ataio->cmd.lba_mid_exp = 0; 1833 } else { 1834 /* REQUEST SENSE */ 1835 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 1836 ccb->ccb_h.recovery_slot = i; 1837 ccb->ccb_h.func_code = XPT_SCSI_IO; 1838 ccb->ccb_h.flags = CAM_DIR_IN; 1839 ccb->ccb_h.status = 0; 1840 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1841 csio = &ccb->csio; 1842 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 1843 csio->dxfer_len = ch->hold[i]->csio.sense_len; 1844 csio->cdb_len = 6; 1845 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 1846 csio->cdb_io.cdb_bytes[0] = 0x03; 1847 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 1848 } 1849 /* Freeze SIM while doing recovery. */ 1850 ch->recoverycmd = 1; 1851 xpt_freeze_simq(ch->sim, 1); 1852 mvs_begin_transaction(dev, ccb); 1853} 1854 1855static void 1856mvs_process_read_log(device_t dev, union ccb *ccb) 1857{ 1858 struct mvs_channel *ch = device_get_softc(dev); 1859 uint8_t *data; 1860 struct ata_res *res; 1861 int i; 1862 1863 ch->recoverycmd = 0; 1864 1865 data = ccb->ataio.data_ptr; 1866 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1867 (data[0] & 0x80) == 0) { 1868 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1869 if (!ch->hold[i]) 1870 continue; 1871 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1872 continue; 1873 if ((data[0] & 0x1F) == ch->holdtag[i]) { 1874 res = &ch->hold[i]->ataio.res; 1875 res->status = data[2]; 1876 res->error = data[3]; 1877 res->lba_low = data[4]; 1878 res->lba_mid = data[5]; 1879 res->lba_high = data[6]; 1880 res->device = data[7]; 1881 res->lba_low_exp = data[8]; 1882 res->lba_mid_exp = data[9]; 1883 res->lba_high_exp = data[10]; 1884 res->sector_count = data[12]; 1885 res->sector_count_exp = data[13]; 1886 } else { 1887 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1888 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1889 } 1890 xpt_done(ch->hold[i]); 1891 ch->hold[i] = NULL; 1892 ch->numhslots--; 1893 } 1894 } else { 1895 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1896 device_printf(dev, "Error while READ LOG EXT\n"); 1897 else if ((data[0] & 0x80) == 0) { 1898 device_printf(dev, 1899 "Non-queued command error in READ LOG EXT\n"); 1900 } 1901 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1902 if (!ch->hold[i]) 1903 continue; 1904 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1905 continue; 1906 xpt_done(ch->hold[i]); 1907 ch->hold[i] = NULL; 1908 ch->numhslots--; 1909 } 1910 } 1911 free(ccb->ataio.data_ptr, M_MVS); 1912 xpt_free_ccb(ccb); 1913 xpt_release_simq(ch->sim, TRUE); 1914} 1915 1916static void 1917mvs_process_request_sense(device_t dev, union ccb *ccb) 1918{ 1919 struct mvs_channel *ch = device_get_softc(dev); 1920 int i; 1921 1922 ch->recoverycmd = 0; 1923 1924 i = ccb->ccb_h.recovery_slot; 1925 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 1926 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 1927 } else { 1928 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1929 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 1930 } 1931 xpt_done(ch->hold[i]); 1932 ch->hold[i] = NULL; 1933 ch->numhslots--; 1934 xpt_free_ccb(ccb); 1935 xpt_release_simq(ch->sim, TRUE); 1936} 1937 1938static int 1939mvs_wait(device_t dev, u_int s, u_int c, int t) 1940{ 1941 int timeout = 0; 1942 uint8_t st; 1943 1944 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) { 1945 if (timeout >= t) { 1946 if (t != 0) 1947 device_printf(dev, "Wait status %02x\n", st); 1948 return (-1); 1949 } 1950 DELAY(1000); 1951 timeout++; 1952 } 1953 return (timeout); 1954} 1955 1956static void 1957mvs_requeue_frozen(device_t dev) 1958{ 1959 struct mvs_channel *ch = device_get_softc(dev); 1960 union ccb *fccb = ch->frozen; 1961 1962 if (fccb) { 1963 ch->frozen = NULL; 1964 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1965 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1966 xpt_freeze_devq(fccb->ccb_h.path, 1); 1967 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1968 } 1969 xpt_done(fccb); 1970 } 1971} 1972 1973static void 1974mvs_reset_to(void *arg) 1975{ 1976 device_t dev = arg; 1977 struct mvs_channel *ch = device_get_softc(dev); 1978 int t; 1979 1980 if (ch->resetting == 0) 1981 return; 1982 ch->resetting--; 1983 if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) { 1984 if (bootverbose) { 1985 device_printf(dev, 1986 "MVS reset: device ready after %dms\n", 1987 (310 - ch->resetting) * 100); 1988 } 1989 ch->resetting = 0; 1990 xpt_release_simq(ch->sim, TRUE); 1991 return; 1992 } 1993 if (ch->resetting == 0) { 1994 device_printf(dev, 1995 "MVS reset: device not ready after 31000ms\n"); 1996 xpt_release_simq(ch->sim, TRUE); 1997 return; 1998 } 1999 callout_schedule(&ch->reset_timer, hz / 10); 2000} 2001 2002static void 2003mvs_errata(device_t dev) 2004{ 2005 struct mvs_channel *ch = device_get_softc(dev); 2006 uint32_t val; 2007 2008 if (ch->quirks & MVS_Q_SOC65) { 2009 val = ATA_INL(ch->r_mem, SATA_PHYM3); 2010 val &= ~(0x3 << 27); /* SELMUPF = 1 */ 2011 val |= (0x1 << 27); 2012 val &= ~(0x3 << 29); /* SELMUPI = 1 */ 2013 val |= (0x1 << 29); 2014 ATA_OUTL(ch->r_mem, SATA_PHYM3, val); 2015 2016 val = ATA_INL(ch->r_mem, SATA_PHYM4); 2017 val &= ~0x1; /* SATU_OD8 = 0 */ 2018 val |= (0x1 << 16); /* reserved bit 16 = 1 */ 2019 ATA_OUTL(ch->r_mem, SATA_PHYM4, val); 2020 2021 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2); 2022 val &= ~0xf; /* TXAMP[3:0] = 8 */ 2023 val |= 0x8; 2024 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */ 2025 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val); 2026 2027 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1); 2028 val &= ~0xf; /* TXAMP[3:0] = 8 */ 2029 val |= 0x8; 2030 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */ 2031 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val); 2032 } 2033} 2034 2035static void 2036mvs_reset(device_t dev) 2037{ 2038 struct mvs_channel *ch = device_get_softc(dev); 2039 int i; 2040 2041 xpt_freeze_simq(ch->sim, 1); 2042 if (bootverbose) 2043 device_printf(dev, "MVS reset...\n"); 2044 /* Forget about previous reset. */ 2045 if (ch->resetting) { 2046 ch->resetting = 0; 2047 callout_stop(&ch->reset_timer); 2048 xpt_release_simq(ch->sim, TRUE); 2049 } 2050 /* Requeue freezed command. */ 2051 mvs_requeue_frozen(dev); 2052 /* Kill the engine and requeue all running commands. */ 2053 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 2054 ATA_OUTL(ch->r_mem, DMA_C, 0); 2055 for (i = 0; i < MVS_MAX_SLOTS; i++) { 2056 /* Do we have a running request on slot? */ 2057 if (ch->slot[i].state < MVS_SLOT_RUNNING) 2058 continue; 2059 /* XXX; Commands in loading state. */ 2060 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT); 2061 } 2062 for (i = 0; i < MVS_MAX_SLOTS; i++) { 2063 if (!ch->hold[i]) 2064 continue; 2065 xpt_done(ch->hold[i]); 2066 ch->hold[i] = NULL; 2067 ch->numhslots--; 2068 } 2069 if (ch->toslots != 0) 2070 xpt_release_simq(ch->sim, TRUE); 2071 ch->eslots = 0; 2072 ch->toslots = 0; 2073 ch->fatalerr = 0; 2074 ch->fake_busy = 0; 2075 /* Tell the XPT about the event */ 2076 xpt_async(AC_BUS_RESET, ch->path, NULL); 2077 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 2078 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST); 2079 DELAY(25); 2080 ATA_OUTL(ch->r_mem, EDMA_CMD, 0); 2081 mvs_errata(dev); 2082 /* Reset and reconnect PHY, */ 2083 if (!mvs_sata_phy_reset(dev)) { 2084 if (bootverbose) 2085 device_printf(dev, "MVS reset: device not found\n"); 2086 ch->devices = 0; 2087 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2088 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 2089 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 2090 xpt_release_simq(ch->sim, TRUE); 2091 return; 2092 } 2093 if (bootverbose) 2094 device_printf(dev, "MVS reset: device found\n"); 2095 /* Wait for clearing busy status. */ 2096 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 2097 dumping ? 31000 : 0)) < 0) { 2098 if (dumping) { 2099 device_printf(dev, 2100 "MVS reset: device not ready after 31000ms\n"); 2101 } else 2102 ch->resetting = 310; 2103 } else if (bootverbose) 2104 device_printf(dev, "MVS reset: device ready after %dms\n", i); 2105 ch->devices = 1; 2106 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2107 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 2108 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 2109 if (ch->resetting) 2110 callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev); 2111 else 2112 xpt_release_simq(ch->sim, TRUE); 2113} 2114 2115static void 2116mvs_softreset(device_t dev, union ccb *ccb) 2117{ 2118 struct mvs_channel *ch = device_get_softc(dev); 2119 int port = ccb->ccb_h.target_id & 0x0f; 2120 int i, stuck; 2121 uint8_t status; 2122 2123 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 2124 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 2125 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 2126 DELAY(10000); 2127 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 2128 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2129 /* Wait for clearing busy status. */ 2130 if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) { 2131 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2132 stuck = 1; 2133 } else { 2134 status = mvs_getstatus(dev, 0); 2135 if (status & ATA_S_ERROR) 2136 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2137 else 2138 ccb->ccb_h.status |= CAM_REQ_CMP; 2139 if (status & ATA_S_DRQ) 2140 stuck = 1; 2141 else 2142 stuck = 0; 2143 } 2144 mvs_tfd_read(dev, ccb); 2145 2146 /* 2147 * XXX: If some device on PMP failed to soft-reset, 2148 * try to recover by sending dummy soft-reset to PMP. 2149 */ 2150 if (stuck && ch->pm_present && port != 15) { 2151 ATA_OUTB(ch->r_mem, SATA_SATAICTL, 2152 15 << SATA_SATAICTL_PMPTX_SHIFT); 2153 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 2154 DELAY(10000); 2155 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 2156 mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout); 2157 } 2158 2159 xpt_done(ccb); 2160} 2161 2162static int 2163mvs_sata_connect(struct mvs_channel *ch) 2164{ 2165 u_int32_t status; 2166 int timeout, found = 0; 2167 2168 /* Wait up to 100ms for "connect well" */ 2169 for (timeout = 0; timeout < 1000 ; timeout++) { 2170 status = ATA_INL(ch->r_mem, SATA_SS); 2171 if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE) 2172 found = 1; 2173 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 2174 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 2175 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) 2176 break; 2177 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) { 2178 if (bootverbose) { 2179 device_printf(ch->dev, "SATA offline status=%08x\n", 2180 status); 2181 } 2182 return (0); 2183 } 2184 if (found == 0 && timeout >= 100) 2185 break; 2186 DELAY(100); 2187 } 2188 if (timeout >= 1000 || !found) { 2189 if (bootverbose) { 2190 device_printf(ch->dev, 2191 "SATA connect timeout time=%dus status=%08x\n", 2192 timeout * 100, status); 2193 } 2194 return (0); 2195 } 2196 if (bootverbose) { 2197 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2198 timeout * 100, status); 2199 } 2200 /* Clear SATA error register */ 2201 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2202 return (1); 2203} 2204 2205static int 2206mvs_sata_phy_reset(device_t dev) 2207{ 2208 struct mvs_channel *ch = device_get_softc(dev); 2209 int sata_rev; 2210 uint32_t val; 2211 2212 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2213 if (sata_rev == 1) 2214 val = SATA_SC_SPD_SPEED_GEN1; 2215 else if (sata_rev == 2) 2216 val = SATA_SC_SPD_SPEED_GEN2; 2217 else if (sata_rev == 3) 2218 val = SATA_SC_SPD_SPEED_GEN3; 2219 else 2220 val = 0; 2221 ATA_OUTL(ch->r_mem, SATA_SC, 2222 SATA_SC_DET_RESET | val | 2223 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER); 2224 DELAY(1000); 2225 ATA_OUTL(ch->r_mem, SATA_SC, 2226 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2227 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER))); 2228 if (!mvs_sata_connect(ch)) { 2229 if (ch->pm_level > 0) 2230 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE); 2231 return (0); 2232 } 2233 return (1); 2234} 2235 2236static int 2237mvs_check_ids(device_t dev, union ccb *ccb) 2238{ 2239 struct mvs_channel *ch = device_get_softc(dev); 2240 2241 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) { 2242 ccb->ccb_h.status = CAM_TID_INVALID; 2243 xpt_done(ccb); 2244 return (-1); 2245 } 2246 if (ccb->ccb_h.target_lun != 0) { 2247 ccb->ccb_h.status = CAM_LUN_INVALID; 2248 xpt_done(ccb); 2249 return (-1); 2250 } 2251 return (0); 2252} 2253 2254static void 2255mvsaction(struct cam_sim *sim, union ccb *ccb) 2256{ 2257 device_t dev, parent; 2258 struct mvs_channel *ch; 2259 2260 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n", 2261 ccb->ccb_h.func_code)); 2262 2263 ch = (struct mvs_channel *)cam_sim_softc(sim); 2264 dev = ch->dev; 2265 switch (ccb->ccb_h.func_code) { 2266 /* Common cases first */ 2267 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2268 case XPT_SCSI_IO: 2269 if (mvs_check_ids(dev, ccb)) 2270 return; 2271 if (ch->devices == 0 || 2272 (ch->pm_present == 0 && 2273 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2274 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2275 break; 2276 } 2277 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2278 /* Check for command collision. */ 2279 if (mvs_check_collision(dev, ccb)) { 2280 /* Freeze command. */ 2281 ch->frozen = ccb; 2282 /* We have only one frozen slot, so freeze simq also. */ 2283 xpt_freeze_simq(ch->sim, 1); 2284 return; 2285 } 2286 mvs_begin_transaction(dev, ccb); 2287 return; 2288 case XPT_EN_LUN: /* Enable LUN as a target */ 2289 case XPT_TARGET_IO: /* Execute target I/O request */ 2290 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2291 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2292 case XPT_ABORT: /* Abort the specified CCB */ 2293 /* XXX Implement */ 2294 ccb->ccb_h.status = CAM_REQ_INVALID; 2295 break; 2296 case XPT_SET_TRAN_SETTINGS: 2297 { 2298 struct ccb_trans_settings *cts = &ccb->cts; 2299 struct mvs_device *d; 2300 2301 if (mvs_check_ids(dev, ccb)) 2302 return; 2303 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2304 d = &ch->curr[ccb->ccb_h.target_id]; 2305 else 2306 d = &ch->user[ccb->ccb_h.target_id]; 2307 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2308 d->revision = cts->xport_specific.sata.revision; 2309 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2310 d->mode = cts->xport_specific.sata.mode; 2311 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) { 2312 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048, 2313 cts->xport_specific.sata.bytecount); 2314 } 2315 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2316 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags); 2317 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2318 ch->pm_present = cts->xport_specific.sata.pm_present; 2319 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2320 d->atapi = cts->xport_specific.sata.atapi; 2321 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2322 d->caps = cts->xport_specific.sata.caps; 2323 ccb->ccb_h.status = CAM_REQ_CMP; 2324 break; 2325 } 2326 case XPT_GET_TRAN_SETTINGS: 2327 /* Get default/user set transfer settings for the target */ 2328 { 2329 struct ccb_trans_settings *cts = &ccb->cts; 2330 struct mvs_device *d; 2331 uint32_t status; 2332 2333 if (mvs_check_ids(dev, ccb)) 2334 return; 2335 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2336 d = &ch->curr[ccb->ccb_h.target_id]; 2337 else 2338 d = &ch->user[ccb->ccb_h.target_id]; 2339 cts->protocol = PROTO_UNSPECIFIED; 2340 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2341 cts->transport = XPORT_SATA; 2342 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2343 cts->proto_specific.valid = 0; 2344 cts->xport_specific.sata.valid = 0; 2345 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2346 (ccb->ccb_h.target_id == 15 || 2347 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2348 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK; 2349 if (status & 0x0f0) { 2350 cts->xport_specific.sata.revision = 2351 (status & 0x0f0) >> 4; 2352 cts->xport_specific.sata.valid |= 2353 CTS_SATA_VALID_REVISION; 2354 } 2355 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2356// if (ch->pm_level) 2357// cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2358 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2359 cts->xport_specific.sata.caps &= 2360 ch->user[ccb->ccb_h.target_id].caps; 2361 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2362 } else { 2363 cts->xport_specific.sata.revision = d->revision; 2364 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2365 cts->xport_specific.sata.caps = d->caps; 2366 if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* && 2367 (ch->quirks & MVS_Q_GENIIE) == 0*/) 2368 cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN; 2369 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2370 } 2371 cts->xport_specific.sata.mode = d->mode; 2372 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2373 cts->xport_specific.sata.bytecount = d->bytecount; 2374 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2375 cts->xport_specific.sata.pm_present = ch->pm_present; 2376 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2377 cts->xport_specific.sata.tags = d->tags; 2378 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2379 cts->xport_specific.sata.atapi = d->atapi; 2380 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2381 ccb->ccb_h.status = CAM_REQ_CMP; 2382 break; 2383 } 2384 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2385 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2386 mvs_reset(dev); 2387 ccb->ccb_h.status = CAM_REQ_CMP; 2388 break; 2389 case XPT_TERM_IO: /* Terminate the I/O process */ 2390 /* XXX Implement */ 2391 ccb->ccb_h.status = CAM_REQ_INVALID; 2392 break; 2393 case XPT_PATH_INQ: /* Path routing inquiry */ 2394 { 2395 struct ccb_pathinq *cpi = &ccb->cpi; 2396 2397 parent = device_get_parent(dev); 2398 cpi->version_num = 1; /* XXX??? */ 2399 cpi->hba_inquiry = PI_SDTR_ABLE; 2400 if (!(ch->quirks & MVS_Q_GENI)) { 2401 cpi->hba_inquiry |= PI_SATAPM; 2402 /* Gen-II is extremely slow with NCQ on PMP. */ 2403 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0) 2404 cpi->hba_inquiry |= PI_TAG_ABLE; 2405 } 2406 cpi->target_sprt = 0; 2407 cpi->hba_misc = PIM_SEQSCAN; 2408 cpi->hba_eng_cnt = 0; 2409 if (!(ch->quirks & MVS_Q_GENI)) 2410 cpi->max_target = 15; 2411 else 2412 cpi->max_target = 0; 2413 cpi->max_lun = 0; 2414 cpi->initiator_id = 0; 2415 cpi->bus_id = cam_sim_bus(sim); 2416 cpi->base_transfer_speed = 150000; 2417 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2418 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN); 2419 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2420 cpi->unit_number = cam_sim_unit(sim); 2421 cpi->transport = XPORT_SATA; 2422 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2423 cpi->protocol = PROTO_ATA; 2424 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2425 cpi->maxio = MAXPHYS; 2426 if ((ch->quirks & MVS_Q_SOC) == 0) { 2427 cpi->hba_vendor = pci_get_vendor(parent); 2428 cpi->hba_device = pci_get_device(parent); 2429 cpi->hba_subvendor = pci_get_subvendor(parent); 2430 cpi->hba_subdevice = pci_get_subdevice(parent); 2431 } 2432 cpi->ccb_h.status = CAM_REQ_CMP; 2433 break; 2434 } 2435 default: 2436 ccb->ccb_h.status = CAM_REQ_INVALID; 2437 break; 2438 } 2439 xpt_done(ccb); 2440} 2441 2442static void 2443mvspoll(struct cam_sim *sim) 2444{ 2445 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim); 2446 struct mvs_intr_arg arg; 2447 2448 arg.arg = ch->dev; 2449 arg.cause = 2 | 4; /* XXX */ 2450 mvs_ch_intr(&arg); 2451 if (ch->resetting != 0 && 2452 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2453 ch->resetpolldiv = 1000; 2454 mvs_reset_to(ch->dev); 2455 } 2456} 2457 2458