rgephy.c revision 164831 
1/*-
2 * Copyright (c) 2003
3 *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 *    may be used to endorse or promote products derived from this software
18 *    without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/rgephy.c 164831 2006-12-02 19:48:53Z marius $");
35
36/*
37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/if_arp.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/rgephyreg.h>
56
57#include "miibus_if.h"
58
59#include <machine/bus.h>
60#include <pci/if_rlreg.h>
61
62static int rgephy_probe(device_t);
63static int rgephy_attach(device_t);
64
65static device_method_t rgephy_methods[] = {
66	/* device interface */
67	DEVMETHOD(device_probe,		rgephy_probe),
68	DEVMETHOD(device_attach,	rgephy_attach),
69	DEVMETHOD(device_detach,	mii_phy_detach),
70	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
71	{ 0, 0 }
72};
73
74static devclass_t rgephy_devclass;
75
76static driver_t rgephy_driver = {
77	"rgephy",
78	rgephy_methods,
79	sizeof(struct mii_softc)
80};
81
82DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
83
84static int	rgephy_service(struct mii_softc *, struct mii_data *, int);
85static void	rgephy_status(struct mii_softc *);
86static int	rgephy_mii_phy_auto(struct mii_softc *);
87static void	rgephy_reset(struct mii_softc *);
88static void	rgephy_loop(struct mii_softc *);
89static void	rgephy_load_dspcode(struct mii_softc *);
90
91static const struct mii_phydesc rgephys[] = {
92	MII_PHY_DESC(xxREALTEK, RTL8169S),
93	MII_PHY_END
94};
95
96static int
97rgephy_probe(device_t dev)
98{
99
100	return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
101}
102
103static int
104rgephy_attach(device_t dev)
105{
106	struct mii_softc *sc;
107	struct mii_attach_args *ma;
108	struct mii_data *mii;
109	const char *sep = "";
110
111	sc = device_get_softc(dev);
112	ma = device_get_ivars(dev);
113	sc->mii_dev = device_get_parent(dev);
114	mii = device_get_softc(sc->mii_dev);
115	LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
116
117	sc->mii_inst = mii->mii_instance;
118	sc->mii_phy = ma->mii_phyno;
119	sc->mii_service = rgephy_service;
120	sc->mii_pdata = mii;
121
122	mii->mii_instance++;
123
124#define	ADD(m, c)	ifmedia_add(&mii->mii_media, (m), (c), NULL)
125#define PRINT(s)	printf("%s%s", sep, s); sep = ", "
126
127#if 0
128	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
129	    BMCR_LOOP|BMCR_S100);
130#endif
131
132	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
133	sc->mii_capabilities &= ~BMSR_ANEG;
134
135	device_printf(dev, " ");
136	mii_phy_add_media(sc);
137	/* RTL8169S do not report auto-sense; add manually. */
138	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA);
139	PRINT("auto");
140	printf("\n");
141#undef ADD
142#undef PRINT
143
144	rgephy_reset(sc);
145	MIIBUS_MEDIAINIT(sc->mii_dev);
146	return (0);
147}
148
149static int
150rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
151{
152	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
153	int reg, speed, gig, anar;
154
155	switch (cmd) {
156	case MII_POLLSTAT:
157		/*
158		 * If we're not polling our PHY instance, just return.
159		 */
160		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
161			return (0);
162		break;
163
164	case MII_MEDIACHG:
165		/*
166		 * If the media indicates a different PHY instance,
167		 * isolate ourselves.
168		 */
169		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
170			reg = PHY_READ(sc, MII_BMCR);
171			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
172			return (0);
173		}
174
175		/*
176		 * If the interface is not up, don't do anything.
177		 */
178		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
179			break;
180
181		rgephy_reset(sc);	/* XXX hardware bug work-around */
182
183		anar = PHY_READ(sc, RGEPHY_MII_ANAR);
184		anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
185		    RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
186
187		switch (IFM_SUBTYPE(ife->ifm_media)) {
188		case IFM_AUTO:
189#ifdef foo
190			/*
191			 * If we're already in auto mode, just return.
192			 */
193			if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
194				return (0);
195#endif
196			(void) rgephy_mii_phy_auto(sc);
197			break;
198		case IFM_1000_T:
199			speed = RGEPHY_S1000;
200			goto setit;
201		case IFM_100_TX:
202			speed = RGEPHY_S100;
203			anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
204			goto setit;
205		case IFM_10_T:
206			speed = RGEPHY_S10;
207			anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
208setit:
209			rgephy_loop(sc);
210			if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
211				speed |= RGEPHY_BMCR_FDX;
212				gig = RGEPHY_1000CTL_AFD;
213				anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
214			} else {
215				gig = RGEPHY_1000CTL_AHD;
216				anar &=
217				    ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
218			}
219
220			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
221				PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
222				PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
223				PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
224				    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
225				break;
226			}
227
228			/*
229			 * When setting the link manually, one side must
230			 * be the master and the other the slave. However
231			 * ifmedia doesn't give us a good way to specify
232			 * this, so we fake it by using one of the LINK
233			 * flags. If LINK0 is set, we program the PHY to
234			 * be a master, otherwise it's a slave.
235			 */
236			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
237				PHY_WRITE(sc, RGEPHY_MII_1000CTL,
238				    gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
239			} else {
240				PHY_WRITE(sc, RGEPHY_MII_1000CTL,
241				    gig|RGEPHY_1000CTL_MSE);
242			}
243			PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
244			    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
245			break;
246		case IFM_NONE:
247			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
248			break;
249		case IFM_100_T4:
250		default:
251			return (EINVAL);
252		}
253		break;
254
255	case MII_TICK:
256		/*
257		 * If we're not currently selected, just return.
258		 */
259		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
260			return (0);
261
262		/*
263		 * Is the interface even up?
264		 */
265		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
266			return (0);
267
268		/*
269		 * Only used for autonegotiation.
270		 */
271		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
272			break;
273
274		/*
275		 * Check to see if we have link.  If we do, we don't
276		 * need to restart the autonegotiation process.  Read
277		 * the BMSR twice in case it's latched.
278		 */
279		reg = PHY_READ(sc, RL_GMEDIASTAT);
280		if (reg & RL_GMEDIASTAT_LINK)
281			break;
282
283		/*
284		 * Only retry autonegotiation every 5 seconds.
285		 */
286		if (++sc->mii_ticks <= MII_ANEGTICKS)
287			break;
288
289		sc->mii_ticks = 0;
290		rgephy_mii_phy_auto(sc);
291		return (0);
292	}
293
294	/* Update the media status. */
295	rgephy_status(sc);
296
297	/*
298	 * Callback if something changed. Note that we need to poke
299	 * the DSP on the RealTek PHYs if the media changes.
300	 *
301	 */
302	if (sc->mii_media_active != mii->mii_media_active ||
303	    sc->mii_media_status != mii->mii_media_status ||
304	    cmd == MII_MEDIACHG) {
305		rgephy_load_dspcode(sc);
306	}
307	mii_phy_update(sc, cmd);
308	return (0);
309}
310
311static void
312rgephy_status(struct mii_softc *sc)
313{
314	struct mii_data *mii = sc->mii_pdata;
315	int bmsr, bmcr;
316
317	mii->mii_media_status = IFM_AVALID;
318	mii->mii_media_active = IFM_ETHER;
319
320	bmsr = PHY_READ(sc, RL_GMEDIASTAT);
321
322	if (bmsr & RL_GMEDIASTAT_LINK)
323		mii->mii_media_status |= IFM_ACTIVE;
324	bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
325
326	bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
327
328	if (bmcr & RGEPHY_BMCR_LOOP)
329		mii->mii_media_active |= IFM_LOOP;
330
331	if (bmcr & RGEPHY_BMCR_AUTOEN) {
332		if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
333			/* Erg, still trying, I guess... */
334			mii->mii_media_active |= IFM_NONE;
335			return;
336		}
337	}
338
339	bmsr = PHY_READ(sc, RL_GMEDIASTAT);
340	if (bmsr & RL_GMEDIASTAT_1000MBPS)
341		mii->mii_media_active |= IFM_1000_T;
342	else if (bmsr & RL_GMEDIASTAT_100MBPS)
343		mii->mii_media_active |= IFM_100_TX;
344	else if (bmsr & RL_GMEDIASTAT_10MBPS)
345		mii->mii_media_active |= IFM_10_T;
346	else
347		mii->mii_media_active |= IFM_NONE;
348	if (bmsr & RL_GMEDIASTAT_FDX)
349		mii->mii_media_active |= IFM_FDX;
350}
351
352static int
353rgephy_mii_phy_auto(struct mii_softc *mii)
354{
355
356	rgephy_loop(mii);
357	rgephy_reset(mii);
358
359	PHY_WRITE(mii, RGEPHY_MII_ANAR,
360	    BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
361	DELAY(1000);
362	PHY_WRITE(mii, RGEPHY_MII_1000CTL,
363            RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD);
364	DELAY(1000);
365	PHY_WRITE(mii, RGEPHY_MII_BMCR,
366	    RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
367	DELAY(100);
368
369	return (EJUSTRETURN);
370}
371
372static void
373rgephy_loop(struct mii_softc *sc)
374{
375	int i;
376
377	PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
378	DELAY(1000);
379
380	for (i = 0; i < 15000; i++) {
381		if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
382#if 0
383			device_printf(sc->mii_dev, "looped %d\n", i);
384#endif
385			break;
386		}
387		DELAY(10);
388	}
389}
390
391#define PHY_SETBIT(x, y, z) \
392	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
393#define PHY_CLRBIT(x, y, z) \
394	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
395
396/*
397 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
398 * existing revisions of the 8169S/8110S chips need to be tuned in
399 * order to reliably negotiate a 1000Mbps link. This is only needed
400 * for rev 0 and rev 1 of the PHY. Later versions work without
401 * any fixups.
402 */
403static void
404rgephy_load_dspcode(struct mii_softc *sc)
405{
406	int val;
407        uint16_t id2;
408
409	id2 = PHY_READ(sc, MII_PHYIDR2);
410
411	if (MII_REV(id2) > 1)
412		return;
413
414	PHY_WRITE(sc, 31, 0x0001);
415	PHY_WRITE(sc, 21, 0x1000);
416	PHY_WRITE(sc, 24, 0x65C7);
417	PHY_CLRBIT(sc, 4, 0x0800);
418	val = PHY_READ(sc, 4) & 0xFFF;
419	PHY_WRITE(sc, 4, val);
420	PHY_WRITE(sc, 3, 0x00A1);
421	PHY_WRITE(sc, 2, 0x0008);
422	PHY_WRITE(sc, 1, 0x1020);
423	PHY_WRITE(sc, 0, 0x1000);
424	PHY_SETBIT(sc, 4, 0x0800);
425	PHY_CLRBIT(sc, 4, 0x0800);
426	val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
427	PHY_WRITE(sc, 4, val);
428	PHY_WRITE(sc, 3, 0xFF41);
429	PHY_WRITE(sc, 2, 0xDE60);
430	PHY_WRITE(sc, 1, 0x0140);
431	PHY_WRITE(sc, 0, 0x0077);
432	val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
433	PHY_WRITE(sc, 4, val);
434	PHY_WRITE(sc, 3, 0xDF01);
435	PHY_WRITE(sc, 2, 0xDF20);
436	PHY_WRITE(sc, 1, 0xFF95);
437	PHY_WRITE(sc, 0, 0xFA00);
438	val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
439	PHY_WRITE(sc, 4, val);
440	PHY_WRITE(sc, 3, 0xFF41);
441	PHY_WRITE(sc, 2, 0xDE20);
442	PHY_WRITE(sc, 1, 0x0140);
443	PHY_WRITE(sc, 0, 0x00BB);
444	val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
445	PHY_WRITE(sc, 4, val);
446	PHY_WRITE(sc, 3, 0xDF01);
447	PHY_WRITE(sc, 2, 0xDF20);
448	PHY_WRITE(sc, 1, 0xFF95);
449	PHY_WRITE(sc, 0, 0xBF00);
450	PHY_SETBIT(sc, 4, 0x0800);
451	PHY_CLRBIT(sc, 4, 0x0800);
452	PHY_WRITE(sc, 31, 0x0000);
453
454	DELAY(40);
455}
456
457static void
458rgephy_reset(struct mii_softc *sc)
459{
460
461	mii_phy_reset(sc);
462	DELAY(1000);
463	rgephy_load_dspcode(sc);
464}
465