1/*- 2 * Copyright (c) 2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD$"); 35 36/* 37 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 38 */ 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/bus.h> 46 47#include <net/if.h> 48#include <net/if_arp.h> 49#include <net/if_media.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53#include "miidevs.h" 54 55#include <dev/mii/rgephyreg.h> 56 57#include "miibus_if.h" 58 59#include <machine/bus.h> 60#include <pci/if_rlreg.h> 61 62static int rgephy_probe(device_t); 63static int rgephy_attach(device_t); 64 65static device_method_t rgephy_methods[] = { 66 /* device interface */ 67 DEVMETHOD(device_probe, rgephy_probe), 68 DEVMETHOD(device_attach, rgephy_attach), 69 DEVMETHOD(device_detach, mii_phy_detach), 70 DEVMETHOD(device_shutdown, bus_generic_shutdown), 71 DEVMETHOD_END 72}; 73 74static devclass_t rgephy_devclass; 75 76static driver_t rgephy_driver = { 77 "rgephy", 78 rgephy_methods, 79 sizeof(struct mii_softc) 80}; 81 82DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0); 83 84static int rgephy_service(struct mii_softc *, struct mii_data *, int); 85static void rgephy_status(struct mii_softc *); 86static int rgephy_mii_phy_auto(struct mii_softc *, int); 87static void rgephy_reset(struct mii_softc *); 88static void rgephy_loop(struct mii_softc *); 89static void rgephy_load_dspcode(struct mii_softc *); 90 91static const struct mii_phydesc rgephys[] = { 92 MII_PHY_DESC(REALTEK, RTL8169S), 93 MII_PHY_DESC(REALTEK, RTL8251), 94 MII_PHY_END 95}; 96 97static const struct mii_phy_funcs rgephy_funcs = { 98 rgephy_service, 99 rgephy_status, 100 rgephy_reset 101}; 102 103static int 104rgephy_probe(device_t dev) 105{ 106 107 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 108} 109 110static int 111rgephy_attach(device_t dev) 112{ 113 struct mii_softc *sc; 114 struct mii_attach_args *ma; 115 u_int flags; 116 117 sc = device_get_softc(dev); 118 ma = device_get_ivars(dev); 119 flags = 0; 120 if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0) 121 flags |= MIIF_PHYPRIV0; 122 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); 123 124 /* RTL8169S do not report auto-sense; add manually. */ 125 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 126 sc->mii_capmask; 127 if (sc->mii_capabilities & BMSR_EXTSTAT) 128 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 129 device_printf(dev, " "); 130 mii_phy_add_media(sc); 131 printf("\n"); 132 /* 133 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 134 * manual configuration, which is used to work around issues with 135 * certain setups by default, should not be triggered as it may in 136 * turn cause harm in some edge cases. 137 */ 138 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 139 140 PHY_RESET(sc); 141 142 MIIBUS_MEDIAINIT(sc->mii_dev); 143 return (0); 144} 145 146static int 147rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 148{ 149 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 150 int reg, speed, gig, anar; 151 152 switch (cmd) { 153 case MII_POLLSTAT: 154 break; 155 156 case MII_MEDIACHG: 157 /* 158 * If the interface is not up, don't do anything. 159 */ 160 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 161 break; 162 163 PHY_RESET(sc); /* XXX hardware bug work-around */ 164 165 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 166 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 167 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 168 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 169 170 switch (IFM_SUBTYPE(ife->ifm_media)) { 171 case IFM_AUTO: 172#ifdef foo 173 /* 174 * If we're already in auto mode, just return. 175 */ 176 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 177 return (0); 178#endif 179 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 180 break; 181 case IFM_1000_T: 182 speed = RGEPHY_S1000; 183 goto setit; 184 case IFM_100_TX: 185 speed = RGEPHY_S100; 186 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 187 goto setit; 188 case IFM_10_T: 189 speed = RGEPHY_S10; 190 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 191setit: 192 if ((ife->ifm_media & IFM_FLOW) != 0 && 193 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 194 return (EINVAL); 195 196 if ((ife->ifm_media & IFM_FDX) != 0) { 197 speed |= RGEPHY_BMCR_FDX; 198 gig = RGEPHY_1000CTL_AFD; 199 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 200 if ((ife->ifm_media & IFM_FLOW) != 0 || 201 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 202 anar |= 203 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 204 } else { 205 gig = RGEPHY_1000CTL_AHD; 206 anar &= 207 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 208 } 209 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 210 gig |= RGEPHY_1000CTL_MSE; 211 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 212 gig |= RGEPHY_1000CTL_MSC; 213 } else { 214 gig = 0; 215 anar &= ~RGEPHY_ANAR_ASP; 216 } 217 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 218 speed |= 219 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 220 rgephy_loop(sc); 221 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 222 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 223 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 224 break; 225 case IFM_NONE: 226 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 227 break; 228 default: 229 return (EINVAL); 230 } 231 break; 232 233 case MII_TICK: 234 /* 235 * Is the interface even up? 236 */ 237 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 238 return (0); 239 240 /* 241 * Only used for autonegotiation. 242 */ 243 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 244 sc->mii_ticks = 0; 245 break; 246 } 247 248 /* 249 * Check to see if we have link. If we do, we don't 250 * need to restart the autonegotiation process. 251 */ 252 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 253 sc->mii_mpd_rev >= 2) { 254 /* RTL8211B(L) */ 255 reg = PHY_READ(sc, RGEPHY_MII_SSR); 256 if (reg & RGEPHY_SSR_LINK) { 257 sc->mii_ticks = 0; 258 break; 259 } 260 } else { 261 reg = PHY_READ(sc, RL_GMEDIASTAT); 262 if (reg & RL_GMEDIASTAT_LINK) { 263 sc->mii_ticks = 0; 264 break; 265 } 266 } 267 268 /* Announce link loss right after it happens. */ 269 if (sc->mii_ticks++ == 0) 270 break; 271 272 /* Only retry autonegotiation every mii_anegticks seconds. */ 273 if (sc->mii_ticks <= sc->mii_anegticks) 274 return (0); 275 276 sc->mii_ticks = 0; 277 rgephy_mii_phy_auto(sc, ife->ifm_media); 278 break; 279 } 280 281 /* Update the media status. */ 282 PHY_STATUS(sc); 283 284 /* 285 * Callback if something changed. Note that we need to poke 286 * the DSP on the RealTek PHYs if the media changes. 287 * 288 */ 289 if (sc->mii_media_active != mii->mii_media_active || 290 sc->mii_media_status != mii->mii_media_status || 291 cmd == MII_MEDIACHG) { 292 rgephy_load_dspcode(sc); 293 } 294 mii_phy_update(sc, cmd); 295 return (0); 296} 297 298static void 299rgephy_status(struct mii_softc *sc) 300{ 301 struct mii_data *mii = sc->mii_pdata; 302 int bmsr, bmcr; 303 uint16_t ssr; 304 305 mii->mii_media_status = IFM_AVALID; 306 mii->mii_media_active = IFM_ETHER; 307 308 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 309 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 310 if (ssr & RGEPHY_SSR_LINK) 311 mii->mii_media_status |= IFM_ACTIVE; 312 } else { 313 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 314 if (bmsr & RL_GMEDIASTAT_LINK) 315 mii->mii_media_status |= IFM_ACTIVE; 316 } 317 318 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 319 320 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 321 if (bmcr & RGEPHY_BMCR_ISO) { 322 mii->mii_media_active |= IFM_NONE; 323 mii->mii_media_status = 0; 324 return; 325 } 326 327 if (bmcr & RGEPHY_BMCR_LOOP) 328 mii->mii_media_active |= IFM_LOOP; 329 330 if (bmcr & RGEPHY_BMCR_AUTOEN) { 331 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 332 /* Erg, still trying, I guess... */ 333 mii->mii_media_active |= IFM_NONE; 334 return; 335 } 336 } 337 338 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev >= 2) { 339 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 340 switch (ssr & RGEPHY_SSR_SPD_MASK) { 341 case RGEPHY_SSR_S1000: 342 mii->mii_media_active |= IFM_1000_T; 343 break; 344 case RGEPHY_SSR_S100: 345 mii->mii_media_active |= IFM_100_TX; 346 break; 347 case RGEPHY_SSR_S10: 348 mii->mii_media_active |= IFM_10_T; 349 break; 350 default: 351 mii->mii_media_active |= IFM_NONE; 352 break; 353 } 354 if (ssr & RGEPHY_SSR_FDX) 355 mii->mii_media_active |= IFM_FDX; 356 else 357 mii->mii_media_active |= IFM_HDX; 358 } else { 359 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 360 if (bmsr & RL_GMEDIASTAT_1000MBPS) 361 mii->mii_media_active |= IFM_1000_T; 362 else if (bmsr & RL_GMEDIASTAT_100MBPS) 363 mii->mii_media_active |= IFM_100_TX; 364 else if (bmsr & RL_GMEDIASTAT_10MBPS) 365 mii->mii_media_active |= IFM_10_T; 366 else 367 mii->mii_media_active |= IFM_NONE; 368 if (bmsr & RL_GMEDIASTAT_FDX) 369 mii->mii_media_active |= IFM_FDX; 370 else 371 mii->mii_media_active |= IFM_HDX; 372 } 373 374 if ((mii->mii_media_active & IFM_FDX) != 0) 375 mii->mii_media_active |= mii_phy_flowstatus(sc); 376 377 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 378 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 379 mii->mii_media_active |= IFM_ETH_MASTER; 380} 381 382static int 383rgephy_mii_phy_auto(struct mii_softc *sc, int media) 384{ 385 int anar; 386 387 rgephy_loop(sc); 388 PHY_RESET(sc); 389 390 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 391 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 392 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 393 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 394 DELAY(1000); 395 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 396 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 397 DELAY(1000); 398 PHY_WRITE(sc, RGEPHY_MII_BMCR, 399 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 400 DELAY(100); 401 402 return (EJUSTRETURN); 403} 404 405static void 406rgephy_loop(struct mii_softc *sc) 407{ 408 int i; 409 410 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 411 sc->mii_mpd_rev < 2) { 412 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 413 DELAY(1000); 414 } 415 416 for (i = 0; i < 15000; i++) { 417 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 418#if 0 419 device_printf(sc->mii_dev, "looped %d\n", i); 420#endif 421 break; 422 } 423 DELAY(10); 424 } 425} 426 427#define PHY_SETBIT(x, y, z) \ 428 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 429#define PHY_CLRBIT(x, y, z) \ 430 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 431 432/* 433 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 434 * existing revisions of the 8169S/8110S chips need to be tuned in 435 * order to reliably negotiate a 1000Mbps link. This is only needed 436 * for rev 0 and rev 1 of the PHY. Later versions work without 437 * any fixups. 438 */ 439static void 440rgephy_load_dspcode(struct mii_softc *sc) 441{ 442 int val; 443 444 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 445 sc->mii_mpd_rev >= 2) 446 return; 447 448 PHY_WRITE(sc, 31, 0x0001); 449 PHY_WRITE(sc, 21, 0x1000); 450 PHY_WRITE(sc, 24, 0x65C7); 451 PHY_CLRBIT(sc, 4, 0x0800); 452 val = PHY_READ(sc, 4) & 0xFFF; 453 PHY_WRITE(sc, 4, val); 454 PHY_WRITE(sc, 3, 0x00A1); 455 PHY_WRITE(sc, 2, 0x0008); 456 PHY_WRITE(sc, 1, 0x1020); 457 PHY_WRITE(sc, 0, 0x1000); 458 PHY_SETBIT(sc, 4, 0x0800); 459 PHY_CLRBIT(sc, 4, 0x0800); 460 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 461 PHY_WRITE(sc, 4, val); 462 PHY_WRITE(sc, 3, 0xFF41); 463 PHY_WRITE(sc, 2, 0xDE60); 464 PHY_WRITE(sc, 1, 0x0140); 465 PHY_WRITE(sc, 0, 0x0077); 466 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 467 PHY_WRITE(sc, 4, val); 468 PHY_WRITE(sc, 3, 0xDF01); 469 PHY_WRITE(sc, 2, 0xDF20); 470 PHY_WRITE(sc, 1, 0xFF95); 471 PHY_WRITE(sc, 0, 0xFA00); 472 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 473 PHY_WRITE(sc, 4, val); 474 PHY_WRITE(sc, 3, 0xFF41); 475 PHY_WRITE(sc, 2, 0xDE20); 476 PHY_WRITE(sc, 1, 0x0140); 477 PHY_WRITE(sc, 0, 0x00BB); 478 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 479 PHY_WRITE(sc, 4, val); 480 PHY_WRITE(sc, 3, 0xDF01); 481 PHY_WRITE(sc, 2, 0xDF20); 482 PHY_WRITE(sc, 1, 0xFF95); 483 PHY_WRITE(sc, 0, 0xBF00); 484 PHY_SETBIT(sc, 4, 0x0800); 485 PHY_CLRBIT(sc, 4, 0x0800); 486 PHY_WRITE(sc, 31, 0x0000); 487 488 DELAY(40); 489} 490 491static void 492rgephy_reset(struct mii_softc *sc) 493{ 494 uint16_t pcr, ssr; 495 496 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && sc->mii_mpd_rev == 3) { 497 /* RTL8211C(L) */ 498 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 499 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 500 ssr &= ~RGEPHY_SSR_ALDPS; 501 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 502 } 503 } 504 505 if (sc->mii_mpd_rev >= 2) { 506 pcr = PHY_READ(sc, RGEPHY_MII_PCR); 507 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { 508 pcr &= ~RGEPHY_PCR_MDI_MASK; 509 pcr |= RGEPHY_PCR_MDIX_AUTO; 510 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); 511 } 512 } 513 514 mii_phy_reset(sc); 515 DELAY(1000); 516 rgephy_load_dspcode(sc); 517} 518