if_lge.c revision 78287
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/lge/if_lge.c 78287 2001-06-15 19:02:55Z wpaul $ 34 */ 35 36/* 37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 38 * documentation not available, but ask me nicely. 39 * 40 * Written by Bill Paul <william.paul@windriver.com> 41 * Wind River Systems 42 */ 43 44/* 45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 46 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 48 * are three supported methods for data transfer between host and 49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 50 * Propulsion Technology (tm) DMA. The latter mechanism is a form 51 * of double buffer DMA where the packet data is copied to a 52 * pre-allocated DMA buffer who's physical address has been loaded 53 * into a table at device initialization time. The rationale is that 54 * the virtual to physical address translation needed for normal 55 * scatter/gather DMA is more expensive than the data copy needed 56 * for double buffering. This may be true in Windows NT and the like, 57 * but it isn't true for us, at least on the x86 arch. This driver 58 * uses the scatter/gather I/O method for both TX and RX. 59 * 60 * The LXT1001 only supports TCP/IP checksum offload on receive. 61 * Also, the VLAN tagging is done using a 16-entry table which allows 62 * the chip to perform hardware filtering based on VLAN tags. Sadly, 63 * our vlan support doesn't currently play well with this kind of 64 * hardware support. 65 * 66 * Special thanks to: 67 * - Jeff James at Intel, for arranging to have the LXT1001 manual 68 * released (at long last) 69 * - Beny Chen at D-Link, for actually sending it to me 70 * - Brad Short and Keith Alexis at SMC, for sending me sample 71 * SMC9462SX and SMC9462TX adapters for testing 72 * - Paul Saab at Y!, for not killing me (though it remains to be seen 73 * if in fact he did me much of a favor) 74 */ 75 76#include <sys/param.h> 77#include <sys/systm.h> 78#include <sys/sockio.h> 79#include <sys/mbuf.h> 80#include <sys/malloc.h> 81#include <sys/kernel.h> 82#include <sys/socket.h> 83 84#include <net/if.h> 85#include <net/if_arp.h> 86#include <net/ethernet.h> 87#include <net/if_dl.h> 88#include <net/if_media.h> 89 90#include <net/bpf.h> 91 92#include <vm/vm.h> /* for vtophys */ 93#include <vm/pmap.h> /* for vtophys */ 94#include <machine/clock.h> /* for DELAY */ 95#include <machine/bus_pio.h> 96#include <machine/bus_memio.h> 97#include <machine/bus.h> 98#include <machine/resource.h> 99#include <sys/bus.h> 100#include <sys/rman.h> 101 102#include <dev/mii/mii.h> 103#include <dev/mii/miivar.h> 104 105#include <pci/pcireg.h> 106#include <pci/pcivar.h> 107 108#define LGE_USEIOSPACE 109 110#include <dev/lge/if_lgereg.h> 111 112/* "controller miibus0" required. See GENERIC if you get errors here. */ 113#include "miibus_if.h" 114 115#ifndef lint 116static const char rcsid[] = 117 "$FreeBSD: head/sys/dev/lge/if_lge.c 78287 2001-06-15 19:02:55Z wpaul $"; 118#endif 119 120/* 121 * Various supported device vendors/types and their names. 122 */ 123static struct lge_type lge_devs[] = { 124 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 125 { 0, 0, NULL } 126}; 127 128static int lge_probe __P((device_t)); 129static int lge_attach __P((device_t)); 130static int lge_detach __P((device_t)); 131 132static int lge_alloc_jumbo_mem __P((struct lge_softc *)); 133static void lge_free_jumbo_mem __P((struct lge_softc *)); 134static void *lge_jalloc __P((struct lge_softc *)); 135static void lge_jfree __P((caddr_t, void *)); 136 137static int lge_newbuf __P((struct lge_softc *, 138 struct lge_rx_desc *, 139 struct mbuf *)); 140static int lge_encap __P((struct lge_softc *, 141 struct mbuf *, u_int32_t *)); 142static void lge_rxeof __P((struct lge_softc *, int)); 143static void lge_rxeoc __P((struct lge_softc *)); 144static void lge_txeof __P((struct lge_softc *)); 145static void lge_intr __P((void *)); 146static void lge_tick __P((void *)); 147static void lge_start __P((struct ifnet *)); 148static int lge_ioctl __P((struct ifnet *, u_long, caddr_t)); 149static void lge_init __P((void *)); 150static void lge_stop __P((struct lge_softc *)); 151static void lge_watchdog __P((struct ifnet *)); 152static void lge_shutdown __P((device_t)); 153static int lge_ifmedia_upd __P((struct ifnet *)); 154static void lge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 155 156static void lge_eeprom_getword __P((struct lge_softc *, int, u_int16_t *)); 157static void lge_read_eeprom __P((struct lge_softc *, caddr_t, int, 158 int, int)); 159 160static int lge_miibus_readreg __P((device_t, int, int)); 161static int lge_miibus_writereg __P((device_t, int, int, int)); 162static void lge_miibus_statchg __P((device_t)); 163 164static void lge_setmulti __P((struct lge_softc *)); 165static u_int32_t lge_crc __P((struct lge_softc *, caddr_t)); 166static void lge_reset __P((struct lge_softc *)); 167static int lge_list_rx_init __P((struct lge_softc *)); 168static int lge_list_tx_init __P((struct lge_softc *)); 169 170#ifdef LGE_USEIOSPACE 171#define LGE_RES SYS_RES_IOPORT 172#define LGE_RID LGE_PCI_LOIO 173#else 174#define LGE_RES SYS_RES_MEMORY 175#define LGE_RID LGE_PCI_LOMEM 176#endif 177 178static device_method_t lge_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, lge_probe), 181 DEVMETHOD(device_attach, lge_attach), 182 DEVMETHOD(device_detach, lge_detach), 183 DEVMETHOD(device_shutdown, lge_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 191 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 192 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 193 194 { 0, 0 } 195}; 196 197static driver_t lge_driver = { 198 "lge", 199 lge_methods, 200 sizeof(struct lge_softc) 201}; 202 203static devclass_t lge_devclass; 204 205DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 206DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 207 208#define LGE_SETBIT(sc, reg, x) \ 209 CSR_WRITE_4(sc, reg, \ 210 CSR_READ_4(sc, reg) | (x)) 211 212#define LGE_CLRBIT(sc, reg, x) \ 213 CSR_WRITE_4(sc, reg, \ 214 CSR_READ_4(sc, reg) & ~(x)) 215 216#define SIO_SET(x) \ 217 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 218 219#define SIO_CLR(x) \ 220 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 221 222/* 223 * Read a word of data stored in the EEPROM at address 'addr.' 224 */ 225static void lge_eeprom_getword(sc, addr, dest) 226 struct lge_softc *sc; 227 int addr; 228 u_int16_t *dest; 229{ 230 register int i; 231 u_int32_t val; 232 233 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 234 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 235 236 for (i = 0; i < LGE_TIMEOUT; i++) 237 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 238 break; 239 240 if (i == LGE_TIMEOUT) { 241 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 242 return; 243 } 244 245 val = CSR_READ_4(sc, LGE_EEDATA); 246 247 if (addr & 1) 248 *dest = (val >> 16) & 0xFFFF; 249 else 250 *dest = val & 0xFFFF; 251 252 return; 253} 254 255/* 256 * Read a sequence of words from the EEPROM. 257 */ 258static void lge_read_eeprom(sc, dest, off, cnt, swap) 259 struct lge_softc *sc; 260 caddr_t dest; 261 int off; 262 int cnt; 263 int swap; 264{ 265 int i; 266 u_int16_t word = 0, *ptr; 267 268 for (i = 0; i < cnt; i++) { 269 lge_eeprom_getword(sc, off + i, &word); 270 ptr = (u_int16_t *)(dest + (i * 2)); 271 if (swap) 272 *ptr = ntohs(word); 273 else 274 *ptr = word; 275 } 276 277 return; 278} 279 280static int lge_miibus_readreg(dev, phy, reg) 281 device_t dev; 282 int phy, reg; 283{ 284 struct lge_softc *sc; 285 int i; 286 287 sc = device_get_softc(dev); 288 289 /* 290 * If we have a non-PCS PHY, pretend that the internal 291 * autoneg stuff at PHY address 0 isn't there so that 292 * the miibus code will find only the GMII PHY. 293 */ 294 if (sc->lge_pcs == 0 && phy == 0) 295 return(0); 296 297 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 298 299 for (i = 0; i < LGE_TIMEOUT; i++) 300 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 301 break; 302 303 if (i == LGE_TIMEOUT) { 304 printf("lge%d: PHY read timed out\n", sc->lge_unit); 305 return(0); 306 } 307 308 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 309} 310 311static int lge_miibus_writereg(dev, phy, reg, data) 312 device_t dev; 313 int phy, reg, data; 314{ 315 struct lge_softc *sc; 316 int i; 317 318 sc = device_get_softc(dev); 319 320 CSR_WRITE_4(sc, LGE_GMIICTL, 321 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 322 323 for (i = 0; i < LGE_TIMEOUT; i++) 324 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 325 break; 326 327 if (i == LGE_TIMEOUT) { 328 printf("lge%d: PHY write timed out\n", sc->lge_unit); 329 return(0); 330 } 331 332 return(0); 333} 334 335static void lge_miibus_statchg(dev) 336 device_t dev; 337{ 338 struct lge_softc *sc; 339 struct mii_data *mii; 340 341 sc = device_get_softc(dev); 342 mii = device_get_softc(sc->lge_miibus); 343 344 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 345 switch (IFM_SUBTYPE(mii->mii_media_active)) { 346 case IFM_1000_TX: 347 case IFM_1000_SX: 348 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 349 break; 350 case IFM_100_TX: 351 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 352 break; 353 case IFM_10_T: 354 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 355 break; 356 default: 357 /* 358 * Choose something, even if it's wrong. Clearing 359 * all the bits will hose autoneg on the internal 360 * PHY. 361 */ 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 363 break; 364 } 365 366 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 367 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 368 } else { 369 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 370 } 371 372 return; 373} 374 375static u_int32_t lge_crc(sc, addr) 376 struct lge_softc *sc; 377 caddr_t addr; 378{ 379 u_int32_t crc, carry; 380 int i, j; 381 u_int8_t c; 382 383 /* Compute CRC for the address value. */ 384 crc = 0xFFFFFFFF; /* initial value */ 385 386 for (i = 0; i < 6; i++) { 387 c = *(addr + i); 388 for (j = 0; j < 8; j++) { 389 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 390 crc <<= 1; 391 c >>= 1; 392 if (carry) 393 crc = (crc ^ 0x04c11db6) | carry; 394 } 395 } 396 397 /* 398 * return the filter bit position 399 */ 400 return((crc >> 26) & 0x0000003F); 401} 402 403static void lge_setmulti(sc) 404 struct lge_softc *sc; 405{ 406 struct ifnet *ifp; 407 struct ifmultiaddr *ifma; 408 u_int32_t h = 0, hashes[2] = { 0, 0 }; 409 410 ifp = &sc->arpcom.ac_if; 411 412 /* Make sure multicast hash table is enabled. */ 413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 414 415 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 416 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 417 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 418 return; 419 } 420 421 /* first, zot all the existing hash bits */ 422 CSR_WRITE_4(sc, LGE_MAR0, 0); 423 CSR_WRITE_4(sc, LGE_MAR1, 0); 424 425 /* now program new ones */ 426 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 427 if (ifma->ifma_addr->sa_family != AF_LINK) 428 continue; 429 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 430 if (h < 32) 431 hashes[0] |= (1 << h); 432 else 433 hashes[1] |= (1 << (h - 32)); 434 } 435 436 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 437 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 438 439 return; 440} 441 442static void lge_reset(sc) 443 struct lge_softc *sc; 444{ 445 register int i; 446 447 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 448 449 for (i = 0; i < LGE_TIMEOUT; i++) { 450 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 451 break; 452 } 453 454 if (i == LGE_TIMEOUT) 455 printf("lge%d: reset never completed\n", sc->lge_unit); 456 457 /* Wait a little while for the chip to get its brains in order. */ 458 DELAY(1000); 459 460 return; 461} 462 463/* 464 * Probe for a Level 1 chip. Check the PCI vendor and device 465 * IDs against our list and return a device name if we find a match. 466 */ 467static int lge_probe(dev) 468 device_t dev; 469{ 470 struct lge_type *t; 471 472 t = lge_devs; 473 474 while(t->lge_name != NULL) { 475 if ((pci_get_vendor(dev) == t->lge_vid) && 476 (pci_get_device(dev) == t->lge_did)) { 477 device_set_desc(dev, t->lge_name); 478 return(0); 479 } 480 t++; 481 } 482 483 return(ENXIO); 484} 485 486/* 487 * Attach the interface. Allocate softc structures, do ifmedia 488 * setup and ethernet/BPF attach. 489 */ 490static int lge_attach(dev) 491 device_t dev; 492{ 493 int s; 494 u_char eaddr[ETHER_ADDR_LEN]; 495 u_int32_t command; 496 struct lge_softc *sc; 497 struct ifnet *ifp; 498 int unit, error = 0, rid; 499 500 s = splimp(); 501 502 sc = device_get_softc(dev); 503 unit = device_get_unit(dev); 504 bzero(sc, sizeof(struct lge_softc)); 505 506 /* 507 * Handle power management nonsense. 508 */ 509 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 510 u_int32_t iobase, membase, irq; 511 512 /* Save important PCI config data. */ 513 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 514 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 515 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 516 517 /* Reset the power state. */ 518 printf("lge%d: chip is in D%d power mode " 519 "-- setting to D0\n", unit, 520 pci_get_powerstate(dev)); 521 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 522 523 /* Restore PCI config data. */ 524 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 525 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 526 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 527 } 528 529 /* 530 * Map control/status registers. 531 */ 532 pci_enable_busmaster(dev); 533 pci_enable_io(dev, PCIM_CMD_PORTEN); 534 pci_enable_io(dev, PCIM_CMD_MEMEN); 535 command = pci_read_config(dev, PCIR_COMMAND, 4); 536 537#ifdef LGE_USEIOSPACE 538 if (!(command & PCIM_CMD_PORTEN)) { 539 printf("lge%d: failed to enable I/O ports!\n", unit); 540 error = ENXIO;; 541 goto fail; 542 } 543#else 544 if (!(command & PCIM_CMD_MEMEN)) { 545 printf("lge%d: failed to enable memory mapping!\n", unit); 546 error = ENXIO;; 547 goto fail; 548 } 549#endif 550 551 rid = LGE_RID; 552 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 553 0, ~0, 1, RF_ACTIVE); 554 555 if (sc->lge_res == NULL) { 556 printf("lge%d: couldn't map ports/memory\n", unit); 557 error = ENXIO; 558 goto fail; 559 } 560 561 sc->lge_btag = rman_get_bustag(sc->lge_res); 562 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 563 564 /* Allocate interrupt */ 565 rid = 0; 566 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 567 RF_SHAREABLE | RF_ACTIVE); 568 569 if (sc->lge_irq == NULL) { 570 printf("lge%d: couldn't map interrupt\n", unit); 571 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 572 error = ENXIO; 573 goto fail; 574 } 575 576 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 577 lge_intr, sc, &sc->lge_intrhand); 578 579 if (error) { 580 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 581 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 582 printf("lge%d: couldn't set up irq\n", unit); 583 goto fail; 584 } 585 586 /* Reset the adapter. */ 587 lge_reset(sc); 588 589 /* 590 * Get station address from the EEPROM. 591 */ 592 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 593 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 594 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 595 596 /* 597 * A Level 1 chip was detected. Inform the world. 598 */ 599 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 600 601 sc->lge_unit = unit; 602 callout_handle_init(&sc->lge_stat_ch); 603 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 604 605 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 606 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 607 608 if (sc->lge_ldata == NULL) { 609 printf("lge%d: no memory for list buffers!\n", unit); 610 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 611 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 612 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 613 error = ENXIO; 614 goto fail; 615 } 616 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 617 618 /* Try to allocate memory for jumbo buffers. */ 619 if (lge_alloc_jumbo_mem(sc)) { 620 printf("lge%d: jumbo buffer allocation failed\n", 621 sc->lge_unit); 622 contigfree(sc->lge_ldata, 623 sizeof(struct lge_list_data), M_DEVBUF); 624 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 625 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 626 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 627 error = ENXIO; 628 goto fail; 629 } 630 631 ifp = &sc->arpcom.ac_if; 632 ifp->if_softc = sc; 633 ifp->if_unit = unit; 634 ifp->if_name = "lge"; 635 ifp->if_mtu = ETHERMTU; 636 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 637 ifp->if_ioctl = lge_ioctl; 638 ifp->if_output = ether_output; 639 ifp->if_start = lge_start; 640 ifp->if_watchdog = lge_watchdog; 641 ifp->if_init = lge_init; 642 ifp->if_baudrate = 1000000000; 643 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 644 645 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 646 sc->lge_pcs = 1; 647 else 648 sc->lge_pcs = 0; 649 650 /* 651 * Do MII setup. 652 */ 653 if (mii_phy_probe(dev, &sc->lge_miibus, 654 lge_ifmedia_upd, lge_ifmedia_sts)) { 655 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 656 contigfree(sc->lge_ldata, 657 sizeof(struct lge_list_data), M_DEVBUF); 658 lge_free_jumbo_mem(sc); 659 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 660 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 661 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 662 error = ENXIO; 663 goto fail; 664 } 665 666 /* 667 * Call MI attach routine. 668 */ 669 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 670 callout_handle_init(&sc->lge_stat_ch); 671 672fail: 673 splx(s); 674 return(error); 675} 676 677static int lge_detach(dev) 678 device_t dev; 679{ 680 struct lge_softc *sc; 681 struct ifnet *ifp; 682 int s; 683 684 s = splimp(); 685 686 sc = device_get_softc(dev); 687 ifp = &sc->arpcom.ac_if; 688 689 lge_reset(sc); 690 lge_stop(sc); 691 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 692 693 bus_generic_detach(dev); 694 device_delete_child(dev, sc->lge_miibus); 695 696 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 697 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 698 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 699 700 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 701 lge_free_jumbo_mem(sc); 702 703 splx(s); 704 705 return(0); 706} 707 708/* 709 * Initialize the transmit descriptors. 710 */ 711static int lge_list_tx_init(sc) 712 struct lge_softc *sc; 713{ 714 struct lge_list_data *ld; 715 struct lge_ring_data *cd; 716 int i; 717 718 cd = &sc->lge_cdata; 719 ld = sc->lge_ldata; 720 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 721 ld->lge_tx_list[i].lge_mbuf = NULL; 722 ld->lge_tx_list[i].lge_ctl = 0; 723 } 724 725 cd->lge_tx_prod = cd->lge_tx_cons = 0; 726 727 return(0); 728} 729 730 731/* 732 * Initialize the RX descriptors and allocate mbufs for them. Note that 733 * we arralge the descriptors in a closed ring, so that the last descriptor 734 * points back to the first. 735 */ 736static int lge_list_rx_init(sc) 737 struct lge_softc *sc; 738{ 739 struct lge_list_data *ld; 740 struct lge_ring_data *cd; 741 int i; 742 743 ld = sc->lge_ldata; 744 cd = &sc->lge_cdata; 745 746 cd->lge_rx_prod = cd->lge_rx_cons = 0; 747 748 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 749 750 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 751 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 752 break; 753 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 754 return(ENOBUFS); 755 } 756 757 /* Clear possible 'rx command queue empty' interrupt. */ 758 CSR_READ_4(sc, LGE_ISR); 759 760 return(0); 761} 762 763/* 764 * Initialize an RX descriptor and attach an MBUF cluster. 765 */ 766static int lge_newbuf(sc, c, m) 767 struct lge_softc *sc; 768 struct lge_rx_desc *c; 769 struct mbuf *m; 770{ 771 struct mbuf *m_new = NULL; 772 caddr_t *buf = NULL; 773 774 if (m == NULL) { 775 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 776 if (m_new == NULL) { 777 printf("lge%d: no memory for rx list " 778 "-- packet dropped!\n", sc->lge_unit); 779 return(ENOBUFS); 780 } 781 782 /* Allocate the jumbo buffer */ 783 buf = lge_jalloc(sc); 784 if (buf == NULL) { 785#ifdef LGE_VERBOSE 786 printf("lge%d: jumbo allocation failed " 787 "-- packet dropped!\n", sc->lge_unit); 788#endif 789 m_freem(m_new); 790 return(ENOBUFS); 791 } 792 /* Attach the buffer to the mbuf */ 793 m_new->m_data = (void *)buf; 794 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES; 795 MEXTADD(m_new, buf, LGE_MCLBYTES, lge_jfree, 796 (struct lge_softc *)sc, 0, EXT_NET_DRV); 797 } else { 798 m_new = m; 799 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES; 800 m_new->m_data = m_new->m_ext.ext_buf; 801 } 802 803 /* 804 * Adjust alignment so packet payload begins on a 805 * longword boundary. Mandatory for Alpha, useful on 806 * x86 too. 807 */ 808 m_adj(m_new, ETHER_ALIGN); 809 810 c->lge_mbuf = m_new; 811 c->lge_fragptr_hi = 0; 812 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 813 c->lge_fraglen = m_new->m_len; 814 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 815 c->lge_sts = 0; 816 817 /* 818 * Put this buffer in the RX command FIFO. To do this, 819 * we just write the physical address of the descriptor 820 * into the RX descriptor address registers. Note that 821 * there are two registers, one high DWORD and one low 822 * DWORD, which lets us specify a 64-bit address if 823 * desired. We only use a 32-bit address for now. 824 * Writing to the low DWORD register is what actually 825 * causes the command to be issued, so we do that 826 * last. 827 */ 828 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 829 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 830 831 return(0); 832} 833 834static int lge_alloc_jumbo_mem(sc) 835 struct lge_softc *sc; 836{ 837 caddr_t ptr; 838 register int i; 839 struct lge_jpool_entry *entry; 840 841 /* Grab a big chunk o' storage. */ 842 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 843 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 844 845 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 846 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 847 return(ENOBUFS); 848 } 849 850 SLIST_INIT(&sc->lge_jfree_listhead); 851 SLIST_INIT(&sc->lge_jinuse_listhead); 852 853 /* 854 * Now divide it up into 9K pieces and save the addresses 855 * in an array. 856 */ 857 ptr = sc->lge_cdata.lge_jumbo_buf; 858 for (i = 0; i < LGE_JSLOTS; i++) { 859 sc->lge_cdata.lge_jslots[i] = ptr; 860 ptr += LGE_MCLBYTES; 861 entry = malloc(sizeof(struct lge_jpool_entry), 862 M_DEVBUF, M_NOWAIT); 863 if (entry == NULL) { 864 free(sc->lge_cdata.lge_jumbo_buf, M_DEVBUF); 865 sc->lge_cdata.lge_jumbo_buf = NULL; 866 printf("lge%d: no memory for jumbo " 867 "buffer queue!\n", sc->lge_unit); 868 return(ENOBUFS); 869 } 870 entry->slot = i; 871 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 872 entry, jpool_entries); 873 } 874 875 return(0); 876} 877 878static void lge_free_jumbo_mem(sc) 879 struct lge_softc *sc; 880{ 881 int i; 882 struct lge_jpool_entry *entry; 883 884 for (i = 0; i < LGE_JSLOTS; i++) { 885 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 886 free(entry, M_DEVBUF); 887 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 888 } 889 890 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 891 892 return; 893} 894 895/* 896 * Allocate a jumbo buffer. 897 */ 898static void *lge_jalloc(sc) 899 struct lge_softc *sc; 900{ 901 struct lge_jpool_entry *entry; 902 903 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 904 905 if (entry == NULL) { 906#ifdef LGE_VERBOSE 907 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 908#endif 909 return(NULL); 910 } 911 912 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 913 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 914 return(sc->lge_cdata.lge_jslots[entry->slot]); 915} 916 917/* 918 * Release a jumbo buffer. 919 */ 920static void lge_jfree(buf, args) 921 caddr_t buf; 922 void *args; 923{ 924 struct lge_softc *sc; 925 int i; 926 struct lge_jpool_entry *entry; 927 928 /* Extract the softc struct pointer. */ 929 sc = args; 930 931 if (sc == NULL) 932 panic("lge_jfree: can't find softc pointer!"); 933 934 /* calculate the slot this buffer belongs to */ 935 i = ((vm_offset_t)buf 936 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 937 938 if ((i < 0) || (i >= LGE_JSLOTS)) 939 panic("lge_jfree: asked to free buffer that we don't manage!"); 940 941 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 942 if (entry == NULL) 943 panic("lge_jfree: buffer not in use!"); 944 entry->slot = i; 945 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 946 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 947 948 return; 949} 950 951/* 952 * A frame has been uploaded: pass the resulting mbuf chain up to 953 * the higher level protocols. 954 */ 955static void lge_rxeof(sc, cnt) 956 struct lge_softc *sc; 957 int cnt; 958{ 959 struct ether_header *eh; 960 struct mbuf *m; 961 struct ifnet *ifp; 962 struct lge_rx_desc *cur_rx; 963 int c, i, total_len = 0; 964 u_int32_t rxsts, rxctl; 965 966 ifp = &sc->arpcom.ac_if; 967 968 /* Find out how many frames were processed. */ 969 c = cnt; 970 i = sc->lge_cdata.lge_rx_cons; 971 972 /* Suck them in. */ 973 while(c) { 974 struct mbuf *m0 = NULL; 975 976 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 977 rxctl = cur_rx->lge_ctl; 978 rxsts = cur_rx->lge_sts; 979 m = cur_rx->lge_mbuf; 980 cur_rx->lge_mbuf = NULL; 981 total_len = LGE_RXBYTES(cur_rx); 982 LGE_INC(i, LGE_RX_LIST_CNT); 983 c--; 984 985 /* 986 * If an error occurs, update stats, clear the 987 * status word and leave the mbuf cluster in place: 988 * it should simply get re-used next time this descriptor 989 * comes up in the ring. 990 */ 991 if (rxctl & LGE_RXCTL_ERRMASK) { 992 ifp->if_ierrors++; 993 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 994 continue; 995 } 996 997 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 998 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 999 total_len + ETHER_ALIGN, 0, ifp, NULL); 1000 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1001 if (m0 == NULL) { 1002 printf("lge%d: no receive buffers " 1003 "available -- packet dropped!\n", 1004 sc->lge_unit); 1005 ifp->if_ierrors++; 1006 continue; 1007 } 1008 m_adj(m0, ETHER_ALIGN); 1009 m = m0; 1010 } else { 1011 m->m_pkthdr.rcvif = ifp; 1012 m->m_pkthdr.len = m->m_len = total_len; 1013 } 1014 1015 ifp->if_ipackets++; 1016 eh = mtod(m, struct ether_header *); 1017 1018 /* Remove header from mbuf and pass it on. */ 1019 m_adj(m, sizeof(struct ether_header)); 1020 1021 /* Do IP checksum checking. */ 1022 if (rxsts & LGE_RXSTS_ISIP) 1023 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1024 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1025 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1026 if ((rxsts & LGE_RXSTS_ISTCP && 1027 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1028 (rxsts & LGE_RXSTS_ISUDP && 1029 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1030 m->m_pkthdr.csum_flags |= 1031 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1032 m->m_pkthdr.csum_data = 0xffff; 1033 } 1034 1035 ether_input(ifp, eh, m); 1036 } 1037 1038 sc->lge_cdata.lge_rx_cons = i; 1039 1040 return; 1041} 1042 1043void lge_rxeoc(sc) 1044 struct lge_softc *sc; 1045{ 1046 struct ifnet *ifp; 1047 1048 ifp = &sc->arpcom.ac_if; 1049 ifp->if_flags &= ~IFF_RUNNING; 1050 lge_init(sc); 1051 return; 1052} 1053 1054/* 1055 * A frame was downloaded to the chip. It's safe for us to clean up 1056 * the list buffers. 1057 */ 1058 1059static void lge_txeof(sc) 1060 struct lge_softc *sc; 1061{ 1062 struct lge_tx_desc *cur_tx = NULL; 1063 struct ifnet *ifp; 1064 u_int32_t idx, txdone; 1065 1066 ifp = &sc->arpcom.ac_if; 1067 1068 /* Clear the timeout timer. */ 1069 ifp->if_timer = 0; 1070 1071 /* 1072 * Go through our tx list and free mbufs for those 1073 * frames that have been transmitted. 1074 */ 1075 idx = sc->lge_cdata.lge_tx_cons; 1076 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1077 1078 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1079 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1080 1081 ifp->if_opackets++; 1082 if (cur_tx->lge_mbuf != NULL) { 1083 m_freem(cur_tx->lge_mbuf); 1084 cur_tx->lge_mbuf = NULL; 1085 } 1086 cur_tx->lge_ctl = 0; 1087 1088 txdone--; 1089 LGE_INC(idx, LGE_TX_LIST_CNT); 1090 ifp->if_timer = 0; 1091 } 1092 1093 sc->lge_cdata.lge_tx_cons = idx; 1094 1095 if (cur_tx != NULL) 1096 ifp->if_flags &= ~IFF_OACTIVE; 1097 1098 return; 1099} 1100 1101static void lge_tick(xsc) 1102 void *xsc; 1103{ 1104 struct lge_softc *sc; 1105 struct mii_data *mii; 1106 struct ifnet *ifp; 1107 int s; 1108 1109 s = splimp(); 1110 1111 sc = xsc; 1112 ifp = &sc->arpcom.ac_if; 1113 1114 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1115 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1116 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1117 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1118 1119 if (!sc->lge_link) { 1120 mii = device_get_softc(sc->lge_miibus); 1121 mii_tick(mii); 1122 mii_pollstat(mii); 1123 if (mii->mii_media_status & IFM_ACTIVE && 1124 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1125 sc->lge_link++; 1126 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1127 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1128 printf("lge%d: gigabit link up\n", 1129 sc->lge_unit); 1130 if (ifp->if_snd.ifq_head != NULL) 1131 lge_start(ifp); 1132 } 1133 } 1134 1135 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1136 1137 splx(s); 1138 1139 return; 1140} 1141 1142static void lge_intr(arg) 1143 void *arg; 1144{ 1145 struct lge_softc *sc; 1146 struct ifnet *ifp; 1147 u_int32_t status; 1148 1149 sc = arg; 1150 ifp = &sc->arpcom.ac_if; 1151 1152 /* Supress unwanted interrupts */ 1153 if (!(ifp->if_flags & IFF_UP)) { 1154 lge_stop(sc); 1155 return; 1156 } 1157 1158 for (;;) { 1159 /* 1160 * Reading the ISR register clears all interrupts, and 1161 * clears the 'interrupts enabled' bit in the IMR 1162 * register. 1163 */ 1164 status = CSR_READ_4(sc, LGE_ISR); 1165 1166 if ((status & LGE_INTRS) == 0) 1167 break; 1168 1169 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1170 lge_txeof(sc); 1171 1172 if (status & LGE_ISR_RXDMA_DONE) 1173 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1174 1175 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1176 lge_rxeoc(sc); 1177 1178 if (status & LGE_ISR_PHY_INTR) { 1179 sc->lge_link = 0; 1180 untimeout(lge_tick, sc, sc->lge_stat_ch); 1181 lge_tick(sc); 1182 } 1183 } 1184 1185 /* Re-enable interrupts. */ 1186 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1187 1188 if (ifp->if_snd.ifq_head != NULL) 1189 lge_start(ifp); 1190 1191 return; 1192} 1193 1194/* 1195 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1196 * pointers to the fragment pointers. 1197 */ 1198static int lge_encap(sc, m_head, txidx) 1199 struct lge_softc *sc; 1200 struct mbuf *m_head; 1201 u_int32_t *txidx; 1202{ 1203 struct lge_frag *f = NULL; 1204 struct lge_tx_desc *cur_tx; 1205 struct mbuf *m; 1206 int frag = 0, tot_len = 0; 1207 1208 /* 1209 * Start packing the mbufs in this chain into 1210 * the fragment pointers. Stop when we run out 1211 * of fragments or hit the end of the mbuf chain. 1212 */ 1213 m = m_head; 1214 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1215 frag = 0; 1216 1217 for (m = m_head; m != NULL; m = m->m_next) { 1218 if (m->m_len != 0) { 1219 tot_len += m->m_len; 1220 f = &cur_tx->lge_frags[frag]; 1221 f->lge_fraglen = m->m_len; 1222 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1223 f->lge_fragptr_hi = 0; 1224 frag++; 1225 } 1226 } 1227 1228 if (m != NULL) 1229 return(ENOBUFS); 1230 1231 cur_tx->lge_mbuf = m_head; 1232 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1233 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1234 1235 /* Queue for transmit */ 1236 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1237 1238 return(0); 1239} 1240 1241/* 1242 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1243 * to the mbuf data regions directly in the transmit lists. We also save a 1244 * copy of the pointers since the transmit list fragment pointers are 1245 * physical addresses. 1246 */ 1247 1248static void lge_start(ifp) 1249 struct ifnet *ifp; 1250{ 1251 struct lge_softc *sc; 1252 struct mbuf *m_head = NULL; 1253 u_int32_t idx; 1254 1255 sc = ifp->if_softc; 1256 1257 if (!sc->lge_link) 1258 return; 1259 1260 idx = sc->lge_cdata.lge_tx_prod; 1261 1262 if (ifp->if_flags & IFF_OACTIVE) 1263 return; 1264 1265 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1266 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1267 break; 1268 1269 IF_DEQUEUE(&ifp->if_snd, m_head); 1270 if (m_head == NULL) 1271 break; 1272 1273 if (lge_encap(sc, m_head, &idx)) { 1274 IF_PREPEND(&ifp->if_snd, m_head); 1275 ifp->if_flags |= IFF_OACTIVE; 1276 break; 1277 } 1278 1279 /* 1280 * If there's a BPF listener, bounce a copy of this frame 1281 * to him. 1282 */ 1283 if (ifp->if_bpf) 1284 bpf_mtap(ifp, m_head); 1285 } 1286 1287 sc->lge_cdata.lge_tx_prod = idx; 1288 1289 /* 1290 * Set a timeout in case the chip goes out to lunch. 1291 */ 1292 ifp->if_timer = 5; 1293 1294 return; 1295} 1296 1297static void lge_init(xsc) 1298 void *xsc; 1299{ 1300 struct lge_softc *sc = xsc; 1301 struct ifnet *ifp = &sc->arpcom.ac_if; 1302 struct mii_data *mii; 1303 int s; 1304 1305 if (ifp->if_flags & IFF_RUNNING) 1306 return; 1307 1308 s = splimp(); 1309 1310 /* 1311 * Cancel pending I/O and free all RX/TX buffers. 1312 */ 1313 lge_stop(sc); 1314 lge_reset(sc); 1315 1316 mii = device_get_softc(sc->lge_miibus); 1317 1318 /* Set MAC address */ 1319 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1320 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1321 1322 /* Init circular RX list. */ 1323 if (lge_list_rx_init(sc) == ENOBUFS) { 1324 printf("lge%d: initialization failed: no " 1325 "memory for rx buffers\n", sc->lge_unit); 1326 lge_stop(sc); 1327 (void)splx(s); 1328 return; 1329 } 1330 1331 /* 1332 * Init tx descriptors. 1333 */ 1334 lge_list_tx_init(sc); 1335 1336 /* Set initial value for MODE1 register. */ 1337 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1338 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1339 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1340 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1341 1342 /* If we want promiscuous mode, set the allframes bit. */ 1343 if (ifp->if_flags & IFF_PROMISC) { 1344 CSR_WRITE_4(sc, LGE_MODE1, 1345 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1346 } else { 1347 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1348 } 1349 1350 /* 1351 * Set the capture broadcast bit to capture broadcast frames. 1352 */ 1353 if (ifp->if_flags & IFF_BROADCAST) { 1354 CSR_WRITE_4(sc, LGE_MODE1, 1355 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1356 } else { 1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1358 } 1359 1360 /* Packet padding workaround? */ 1361 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1362 1363 /* No error frames */ 1364 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1365 1366 /* Receive large frames */ 1367 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1368 1369 /* Workaround: disable RX/TX flow control */ 1370 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1371 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1372 1373 /* Make sure to strip CRC from received frames */ 1374 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1375 1376 /* Turn off magic packet mode */ 1377 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1378 1379 /* Turn off all VLAN stuff */ 1380 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1381 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1382 1383 /* Workarond: FIFO overflow */ 1384 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1385 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1386 1387 /* 1388 * Load the multicast filter. 1389 */ 1390 lge_setmulti(sc); 1391 1392 /* 1393 * Enable hardware checksum validation for all received IPv4 1394 * packets, do not reject packets with bad checksums. 1395 */ 1396 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1397 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1398 LGE_MODE2_RX_ERRCSUM); 1399 1400 /* 1401 * Enable the delivery of PHY interrupts based on 1402 * link/speed/duplex status chalges. 1403 */ 1404 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1405 1406 /* Enable receiver and transmitter. */ 1407 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1408 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1409 1410 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1411 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1412 1413 /* 1414 * Enable interrupts. 1415 */ 1416 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1417 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1418 1419 lge_ifmedia_upd(ifp); 1420 1421 ifp->if_flags |= IFF_RUNNING; 1422 ifp->if_flags &= ~IFF_OACTIVE; 1423 1424 (void)splx(s); 1425 1426 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1427 1428 return; 1429} 1430 1431/* 1432 * Set media options. 1433 */ 1434static int lge_ifmedia_upd(ifp) 1435 struct ifnet *ifp; 1436{ 1437 struct lge_softc *sc; 1438 struct mii_data *mii; 1439 1440 sc = ifp->if_softc; 1441 1442 mii = device_get_softc(sc->lge_miibus); 1443 sc->lge_link = 0; 1444 if (mii->mii_instance) { 1445 struct mii_softc *miisc; 1446 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1447 miisc = LIST_NEXT(miisc, mii_list)) 1448 mii_phy_reset(miisc); 1449 } 1450 mii_mediachg(mii); 1451 1452 return(0); 1453} 1454 1455/* 1456 * Report current media status. 1457 */ 1458static void lge_ifmedia_sts(ifp, ifmr) 1459 struct ifnet *ifp; 1460 struct ifmediareq *ifmr; 1461{ 1462 struct lge_softc *sc; 1463 struct mii_data *mii; 1464 1465 sc = ifp->if_softc; 1466 1467 mii = device_get_softc(sc->lge_miibus); 1468 mii_pollstat(mii); 1469 ifmr->ifm_active = mii->mii_media_active; 1470 ifmr->ifm_status = mii->mii_media_status; 1471 1472 return; 1473} 1474 1475static int lge_ioctl(ifp, command, data) 1476 struct ifnet *ifp; 1477 u_long command; 1478 caddr_t data; 1479{ 1480 struct lge_softc *sc = ifp->if_softc; 1481 struct ifreq *ifr = (struct ifreq *) data; 1482 struct mii_data *mii; 1483 int s, error = 0; 1484 1485 s = splimp(); 1486 1487 switch(command) { 1488 case SIOCSIFADDR: 1489 case SIOCGIFADDR: 1490 error = ether_ioctl(ifp, command, data); 1491 break; 1492 case SIOCSIFMTU: 1493 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1494 error = EINVAL; 1495 else 1496 ifp->if_mtu = ifr->ifr_mtu; 1497 break; 1498 case SIOCSIFFLAGS: 1499 if (ifp->if_flags & IFF_UP) { 1500 if (ifp->if_flags & IFF_RUNNING && 1501 ifp->if_flags & IFF_PROMISC && 1502 !(sc->lge_if_flags & IFF_PROMISC)) { 1503 CSR_WRITE_4(sc, LGE_MODE1, 1504 LGE_MODE1_SETRST_CTL1| 1505 LGE_MODE1_RX_PROMISC); 1506 } else if (ifp->if_flags & IFF_RUNNING && 1507 !(ifp->if_flags & IFF_PROMISC) && 1508 sc->lge_if_flags & IFF_PROMISC) { 1509 CSR_WRITE_4(sc, LGE_MODE1, 1510 LGE_MODE1_RX_PROMISC); 1511 } else { 1512 ifp->if_flags &= ~IFF_RUNNING; 1513 lge_init(sc); 1514 } 1515 } else { 1516 if (ifp->if_flags & IFF_RUNNING) 1517 lge_stop(sc); 1518 } 1519 sc->lge_if_flags = ifp->if_flags; 1520 error = 0; 1521 break; 1522 case SIOCADDMULTI: 1523 case SIOCDELMULTI: 1524 lge_setmulti(sc); 1525 error = 0; 1526 break; 1527 case SIOCGIFMEDIA: 1528 case SIOCSIFMEDIA: 1529 mii = device_get_softc(sc->lge_miibus); 1530 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1531 break; 1532 default: 1533 error = EINVAL; 1534 break; 1535 } 1536 1537 (void)splx(s); 1538 1539 return(error); 1540} 1541 1542static void lge_watchdog(ifp) 1543 struct ifnet *ifp; 1544{ 1545 struct lge_softc *sc; 1546 1547 sc = ifp->if_softc; 1548 1549 ifp->if_oerrors++; 1550 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1551 1552 lge_stop(sc); 1553 lge_reset(sc); 1554 ifp->if_flags &= ~IFF_RUNNING; 1555 lge_init(sc); 1556 1557 if (ifp->if_snd.ifq_head != NULL) 1558 lge_start(ifp); 1559 1560 return; 1561} 1562 1563/* 1564 * Stop the adapter and free any mbufs allocated to the 1565 * RX and TX lists. 1566 */ 1567static void lge_stop(sc) 1568 struct lge_softc *sc; 1569{ 1570 register int i; 1571 struct ifnet *ifp; 1572 1573 ifp = &sc->arpcom.ac_if; 1574 ifp->if_timer = 0; 1575 untimeout(lge_tick, sc, sc->lge_stat_ch); 1576 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1577 1578 /* Disable receiver and transmitter. */ 1579 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1580 sc->lge_link = 0; 1581 1582 /* 1583 * Free data in the RX lists. 1584 */ 1585 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1586 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1587 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1588 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1589 } 1590 } 1591 bzero((char *)&sc->lge_ldata->lge_rx_list, 1592 sizeof(sc->lge_ldata->lge_rx_list)); 1593 1594 /* 1595 * Free the TX list buffers. 1596 */ 1597 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1598 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1599 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1600 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1601 } 1602 } 1603 1604 bzero((char *)&sc->lge_ldata->lge_tx_list, 1605 sizeof(sc->lge_ldata->lge_tx_list)); 1606 1607 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1608 1609 return; 1610} 1611 1612/* 1613 * Stop all chip I/O so that the kernel's probe routines don't 1614 * get confused by errant DMAs when rebooting. 1615 */ 1616static void lge_shutdown(dev) 1617 device_t dev; 1618{ 1619 struct lge_softc *sc; 1620 1621 sc = device_get_softc(dev); 1622 1623 lge_reset(sc); 1624 lge_stop(sc); 1625 1626 return; 1627} 1628